2010 International Conference on Computer Applications and Industrial Electronics (ICCAIE 2010), December 5-7, 2010, Kuala Lumpur,

Malaysia

FPGA Implementation of Unipolar SPWM for Single

Phase Inverter
A.B. Afarulrazi, M. Zarafi, W. M. Utomo and A. Zar
Department of Electrical Power Engineering
Faculty of Electrical and Electronic Engineering, UTHM
Johore, Malaysia

AbstractNowadays, inverter which is also known as a DC-AC Moreover, the use of FPGA can also solve several problem
converter is one of the most popular parts in electrical devices that interface on source device such as less power
that converts direct (DC) current to alternating current (AC) at consumption, reduce size of circuit, easy to implement
the desired output voltage and frequency. This project presents because can easily changed using the program without any
development of a Unipolar Sinusoidal Pulse Width Modulation
changes in hardware, and flexibility of any changes on the
(SPWM) for single phase full bridge inverter using Field
Programmable Logic Array (FPGA). The Unipolar SPWM is switching parameter.
employed to control the output voltage magnitude of the inverter.
II. SINGLE PHASE SPWM-INVERTER
Altera DE2-70 board with 16 bit serial configuration devices is
used as a controller for the implementation of the SPWM
inverter. Computation of the turn-on and turn-off times of the A. Inverter circuit operation.
SPWM is developed using Matlab. To verify the proposed FPGA- An inverter operates the inverse process of a rectifier. The
SPWM, voltage amplitude regulations are carried. input source of the inverters can be battery, fuel cell, solar cell
or other types of DC source. The output of the inverter has
Keywords- Sinusoidal Pulse Width Modulation; Single Phase square waveform due to the switching pattern. In order to
Inverter; Field Programmable Logic Array
obtain a pure sine wave signal, the filter is used to reduce
harmonic content [5]. The inverter is built from two half-
I. INTRODUCTION bridge inverter which consists of four choppers [6]. The
Inverters are commonly used to supply AC power fed from schematic diagram representation of a single phase full wave
DC sources such as solar panels or batteries. The most famous inverter is shown in Fig. 1. The inverter consists of four
technology that applies this electrical device is Uninterruptible IGBTs as switching devices connected in the form of a
Power Supplies (UPS) [1]. UPS electrical devices are used as bridge.
a battery back-up which provides emergency power when
utility power is unavailable. There are several types of
switching technique such as Single-Pulse Width Modulation,
Multiple-pulse Width Modulation (MPWM) and Sinusoidal
Pulse Width Modulation (SPWM).
In this project, Unipolar SPWM switching is used as a
switching technique. Circuitry of SPWM inverter is
constructed using IGBT (Integrated Gate Bipolar Transistor)
device that is commonly used due to several considerations
such as high power switching frequency and high power rating
devices.
This project presents the implementation of FPGA
technology in designing the SPWM switching signal through
Altera DE2-70 board. It provides a wide range of density, Figure 1. Schematic diagram of single phase full-bridge inverter circuit.
memory, embedded multiplier, and packaging options in a
customer-defined FPGA feature set optimized for low-cost
B. Switching strategies.
applications. Besides that, it also supports a wide range of
common external memory interfaces and I/O protocols There are various techniques to vary the inverter output
common in low-cost applications. The use of FPGA will waveform. In SPWM method, the amplitude of the inverter
produce better control signal phase of full bridge inverter [3]. output voltage is determined by comparing a sinusoidal
The emergence of FPGA has drawn much attention due to its reference (Vref) waveform with a triangular (Vtri) carrier
shorter design cycle, lower cost and higher density [4]. waveform, known as modulation index (ma). The amplitude of
the inverter output voltage proportion with ma, where the ma is
defined as (1),

The authors are with the Department of Electrical Power Engineering,

Faculty of Electrical and Electronic Engineering, Universiti Tun Hussein Onn
Malaysia (UTHM), 86400 Pt. Raja, Bt. Pahat Johore., Malaysia.

978-1-4244-9055-4/10/$26.00 2010 IEEE 671

 Vref
ma (1)
Vtri

In Unipolar SPWM, the switching devices of the full bridge

inverter operate based on a pair technique, whereby if one pair
is closed the other pair is opened. The full bridge Unipolar
PWM switching scheme is shown in Fig. 2. Pattern of on-off
time s of the inverter switching devices is determined by using
intersection between the carrier signal (triangular) and
reference signal (sinusoidal waveform) [7]. The switch
controls for Unipolar SPWM switching scheme given as,
Figure 3. Simulation of single-phase full bridge inverter circuit without filter.
S1 is on when +V sin > V tri
S2 is on when V sin < V tri
S3 is on when V sin > V tri B. Filter design
S4 is on when +V sin < V tri In order to generate a pure sine wave, a filter is needed.

1 (2)
f
2S LC

Equation (2) is used to calculate the suitable combination of

capacitor and inductor.

C. VHDL programming using Quartus II 7.2

Table I shows the data obtained from Matlab simulation.

TABLE I. ON-OFF SWITCHING TIME OF S2 FOR MODULATION INDEX

0.50
Switching time 
 Width (time)
t1 0.00048 0.00104 0.00056
t2 0.00145 0.00208 0.00063
t3 0.00241 0.0031 0.00069
t4 0.00339 0.00412 0.00073
t5 0.00437 0.00512 0.00075
Figure 2. Pulse generation of full bridge Unipolar SPWM scheme. t6 0.00538 0.00612 0.00074
t7 0.00639 0.0071 0.00071
t8 0.00741 0.00807 0.00066
III. METHODOLOGY t9 0.00844 0.00904 0.0006
The SPWM signals are generated by Altera board connect t10 0.00948 0.01 0.00052
t11 0.01052 0.01096 0.00044
to driver circuit. The driver circuit amplifies the signal t12 0.01156 0.01193 0.00037
between ranges of 15 to 18Vdc. The outputs from driver t13 0.01259 0.0129 0.00031
circuits connect to the gate terminal of the IGBTs. The output t14 0.01361 0.01388 0.00027
of inverter is then filtered to produce pure sine wave signal. t15 0.01462 0.01488 0.00026
t16 0.01563 0.01588 0.00025
t17 0.01661 0.0169 0.00029
A. Circuit simulation using Matlab Simulink t18 0.01759 0.01792 0.00033
t19 0.01855 0.01896 0.00041
Referring to switching control scheme, the SPWM signal of t20 0.01952 0.02 0.00048
S4 is the inversion of signal S1 while SPWM signal S2 is the
inversion of signal S3. Therefore, the signal generation must be
divided into two parts which are driver 1 circuit for S1S4 and
driver 2 circuit for S3S2. The output from driver 1 circuit will
connect directly to the gate terminal of S1 and S4 while driver 2
signal connects to S3 and S2. The connection of single phase
full bridge inverter is shown in Fig. 3.

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Figure 4. Block diagram of Quartus II for SPWM signal generator.
Fig. 4 illustrates the block diagram of the complete
Unipolar SPWM generator for modulation index values of
0.50 and 0.75. The block diagram consists of altpll which is
able to generate a 25MHz clock output from the 50MHz
internal clock of Altera DE2-70 board. The clock divider is
applied to divide the input clock into several frequency
ranges, for examples 1MHz, 100 kHz, 10 kHz. Then the 1
MHz out frequency of the clock divider is connected to the
lpm_counter1 and lpm_counter2. Both counter will set to
count from 0 to 19999 over one complete cycle. This means,
one cycle of this frequency represents a period of 20ms. The
on-off signal is created by VHDL programming and converted
to block diagram [3].The block diagram consists of several
blocks which have the different function. Besides that, the
clock divider block to divides the internal clock of Altera DE2
board into several frequency ranges. As an example, the
internal clock frequency can be divided to 25 MHz, 1 MHz,
100 kHz, 1 kHz and etc. Since the switching pulses of S4 and
S2 are inverted from the switching pulse of S1 and S3, only
VHDL programming of S1 and S3 are created. The pulse of S4
and S2 can be created by inverting the pulse created by VHDL
programming of S1 and S3 via not gate.
The output of the SPWM generator is then assigned to the
expansion header of the DE2 board through Pin Planner. The
expansion headers connect directly to 36 pins of the Cyclone
II FPGA.
D. Hardware Design
The hardware design is constructing after simulation part is
successfully done. The hardware design consists of three parts
which are Altera DE2-70, gate driver circuit, inverter circuit
and filter circuit. Fig. 5 shows the complete design hardware.
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Figure 5. Hardware testing session
After the block diagram of SPWM generation in Quartus II
software is successfully compiled, assigned and simulated,
this SPWM signal are downloaded to Altera DE2-70 board via
USB blaster download cable.
The voltage level of the input and output on the expansion
header of Altera DE2-70 board is set to 3.3V. Since to
triggering the IGBTs gate is at the ranges of 13V-18V, driver
circuit is used to step up the voltage as required. The output of
the driver circuits connects to each IGBTs. The filter is
designed based on the calculation and simulation in order to
produce a pure sine wave.
IV. RESULTS AND ANALYSIS
There are two types of software simulation that had been
done in this project which are circuit simulation using Matlab
Simulink and generation of SPWM pulse for Altera DE2-70
board using Quartus II software.
The Matlab Simulink simulation is used to design the
SPWM generator and constructed the single phase full bridge
inverter. The simulation result is used as an indicator to design
the hardware part.
The simulation of Quartus II software is used to check
either the on-off timing data that had been taken is similar
with the Matlab or not. This simulation part is important
because the SPWM generation pulse of Quartus II software
will be used as the SPWM generator to inverter circuit via
Altera DE2-70 board.
After the simulation part is done, the designing hardware
will be analyzed in electrical laboratory. The aim is to ensure
all the hardware results are same with the simulation result.
All the related waveforms are obtained and the values of
voltage are measured.
A. Matlab Simulink simulation results
The designation of SPWM generator is divided into two
parts which are Driver 1 for S1 and S4; and driver 2 for S3 and
S2. The input of inverter circuit is set to 30Vdc. The unfiltered
output for ma=0.75 is shown in Fig. 6.
 from Matlab simulation. Before uploading the program into
Altera DE2-70 Board, the SPWM signal is first simulated by
using Waveform Editor. Fig. 8 shows the generated output
Unipolar SPWM waveforms. The on-off switching times are
compared with the calculated values and any deviations noted
for corrections.

Figure 6. Unfiltered output inverter of resistive load for modulation index

0.75

Fig. 7 show the filtered outputs for ma equal to 0.5 and 0.75. (a)
The peak output voltage and peak to peak of the output
voltage is determined from (3) and (4) respectively.

V0 ma .Vdc (3)

V pp 2.Vo (4)

From the results in Fig. 7, the peak output voltage is (b)

slightly equivalent with the calculation values which are 15V
and 22.5V for ma of 0.50 and 0.75 respectively. Figure 8. Waveform simulation for modulation index
(a) 0.50 and (b) 0.75

C. Experimental hardware results.

Tektronix four channel digital oscilloscope TDS3054B is
used to measure the experimental result from the Altera DE2-
70 board. The experiment is conducted for two modulation
indexes which are 0.5 and 0.75.The output signal of Altera
DE2-70 board is 3.30V. Fig. 9 shows the output signals of S1,
S2, S3 and S4.

(a)

(b)
Figure 9. Output signal of ALTERA DE2-70 for modulation index of 0.50
Figure 7. Filtered output inverter of resistive load for modulation index (a)
0.50 and (b) 0.75
Then, the signals connect to the driver circuit to boost the
signals voltage between ranges of 13V to 18V. Fig. 10 shows
B. Quartus II. the Unipolar SPWM output signals for ma, 0.5 and 0.75.
The simulation of Quartus II is focused on SPWM
switching signal. The turn on-off switching pulse is obtained

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 (a) (b)

Fig. 11. Output voltage for modulation index of 0.50 (a) Unfiltered output (b)
Filtered output

(b)

Figure 10. Unipolar SPWM output signal from driver circuit for modulation
index of (a) 0.50 and (b) 0.75
(a)
The unfiltered and filtered output of inverter circuit that had
been obtained is shown in Fig. 11 and Fig. 12 respectively.
The amplitude of the rapidly on-off switching scheme is same
with the input DC voltage which is 30Vdc.

(b)

Figure 12. Output voltage for modulation index of 0.75 (a) Unfiltered output
(b) Filtered output

(a)

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 V. CONCLUSION
This paper has presented a method to generate the Unipolar
SPWM switching signal using FPGA-Altera DE2-70 Board
for single phase inverter. The simulation using Simulink-
Matlab and experimental result demonstrated that the
development of the proposed project can generate the
sinusoidal output waveform. By using FPGAs, the hardware
design becomes simpler and the project development saves
time.
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