2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

HMFPCC: - Hybrid-Mode Floating Point Conversion

Co-processor
Aneesh R, Vinayak Pati!, Sobha PM, A David selvakumar
{raneesh, vinayakp, sobhapm, david} @cdac.in
Centre for Development of Advanced Computing, Bangalore, INDIA

Abstract-This research and development on conversion co chose single and double precision floating point formats for
processor presents an abstract- level hardware implementation of conversion from one format to another. Based on IEEE
the conversion between various number formats for FPGAs in standard specification, the floating point number representation
modular way. Replacing the floating point expressions with
contains three data fields: - Sign, exponent and mantissa. Fig1
specialized integer or fixed point operations can greatly improve
shows the bit-wise representation of single and double
the system performance in several applications. The replacement
precision floating point number.
requires several types of conversions from one format to another
hidden part
format. The proposed conversion co-processor accelerator can

work in parallel with HOST machine to accept a large amount of 31 3
3O
22 ______

input data and convert to another format and apply fixed point 01 1111111t. 111
sign exponent (a-bit) mantissa (23-bit)
I I
or integer arithmetic operations and the result is converted back radix point

to the floating point or fixed point format. The floating point

conversions unit designs are fully compliant with the IEEE 754- hidden part

2008 standard. The proposed system has been tested on Xilinx B

Virtex 6 xc6vlx550t-2ff1759 FPGA and achieves a throughput of
63 62 52 51

350MFLOPs per second. o I I I I I I I I I I I I.t 'I '-1 '-1 '-1 ------,,--

sign exponent (11-bit)
-, 1 1 "I Imantissa (52-bit)
radix point

Index Terms-IEEE 754 floating point standard, floating point
co-processor, integer conversions, fixed point conversions,
conversion co-processor and FPGA.
I. INTRODUCTION
High end applications like weather forecasting and image
processing requires a conversion of a floating point number
from one format to another format to perform complex
algorithmic calculations. IEEE754-2008 standard [I] specifies
the conversion from floating point to fixed point
conversion between single to double, double to single precision
floating point formats and integer conversions. Most of the
general purpose and special purpose micro-processors are
having the support for the conversion operations
instructions. To support the instructions, hardware based
floating point conversions units are added to the processor core
pipeline to enhance the application performance.
In some cases, especially in complex systems; for instance
in a very large simulation system or in a complex algorithmic
codes, we have to make the conversion between different
number formats. Application developers prefer to implement
conversion algorithms in hardware level instead of software.
Because the hardware implementations causes remarkable
speedup compared with software implementation [7, 9, 10, 11].
For this research work, we chose Field Programmable Gate
Array (FPGA) to implement hardware conversion algorithms.
FPGAs are a very popular type of reconfigurable hardware
combining the flexibility, inherent parallelism and the speed of
specialized hardware [15, 16].
IEEE-754 2008 standard [I] specifies the four set of
floating point number formats: - single, double, extended and
quad precision floating point formats. In this research work, we
Figl: Single and Double precision floating point number
representation
A real number can be represented using one of the floating
point format specified in the IEEE standard [1]. Present work
accepts all type of the number formats such zero, infinity, quite
Not a Number,(QNaN), Signaling Not a Number(SNaN), de
normalized number and Normalized numbers which is
specified in the standard. Design supports rounding modes,
such as "round to zero", "round up" (round towards positive
and infmity), "round down" (round towards negative infmity),
"round ties to odd" and round ties to even.
II. RELATED WORKS
as IEEE-754 2008 standard [1] specifies the conversion of a
floating point number to fixed point and integer and vice versa,
also it specifies the conversion between the floating point
numbers. An automatic software approach [4], to convert the
floating point to fixed point conversion is in-efficient for the
high-performance computing. Main conflicting objective of
the conversion between different formats are: - complexity and
accuracy loss. The paper [8] proposed a high-complexity-high
accuracy and low-complexity-Iow-accuracy implementation of
the floating point to fixed point conversion targeted on micro
controllers. Most of the implementation of the conversion is
targeted on micro-controllers (uses an integer instructions to
implement the floating point instructions) .Field Programmable
Gate Array based conversion co-processor approach is not that
much been explored by the researchers. Our research brings out
the FPGA based implementation of a co-processor for
conversions and their tradeoffs in terms of complexity and
throughput.

978-1-4799-7926-4115/$31.002015 IEEE
 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

III. Top LEVEL ARCHITECTURE OF FLOATING POINT output. The conversion co-processor has 5-exception signal to
CONVERSION CO-PROCESSOR raise the exceptions in the operation. The "comp" signal is to
indicate the completion of the conversion. The exceptions are
The co-processor supports 12-type of conversion functions
raised according the IEEE 754 standard. Table I lists the
(4-bit encoding scheme) from one format to another. The IEEE
opcode and pipeline stage for the conversion operation.
754 standard specifies different types of conversions: - single
precision to double precision, double to single precision
conversion, fixed point to floating point conversion, floating Opcode Conversion Pipeline stage

point to fixed point conversion and integer conversions. Fig. 2 0000 Single precision to double 5
shows the micro-architecture of the conversion co-processor. precision
0001 Double precision to single 5
Data in Round mode opocode op' en rst clk precision

1- 1- "1 J I 1" 0010

0011
Single precision
point (QI6.15)
to

Double precision to fixed

fixed 5

5
Opcode Decoder (4-bit opcode)
point (Q32.31)
(Enable, Data. Round mode] (Enable, Data. Round mode]
0100 Fixed point(QI6.15) to 6

(Data, operation complete J

0101
single precision conversion
Fixed point(Q32.31) to 6
Single Double
to to double precision conversion
Double Single OllO 32-bit unsigned integer to 4
single precision
Fixed 01ll 32-bit unsigned integer to 4
Fixed
to to double precision
Single Double 1000 32-bit signed integer to 5
single precision
Single Double 1001 32-bit signed integer to 4
to to double precision
....
Fixed Fixed
1010 Single precision to signed 4
integer
Unsigned Unsigned
1011 Double precision to signed 4
Integer Integer
----+ to +---- integer
to
Sine:1e Double Table 1: ConversIOn modules and plpelme stages

Signed
Signed
Integer
Integer
----+ to IV. MICRO-ARCHITECTURE OF FLOATING POINT CONVERSIONS
to
Double
Sine:le
A. Single precision to double precision conversion
Double
Single The single to double precision conversion accepts the data
to ....
to
Signed input in the single precision floating point format and outputs
Signed
Intee:er the result in double precision floating point format. The micro
Intee:er
., r
architecture of as-stage pipelined single to double precision

Output De-Multiplexer conversion module is shown in Fig 3.

1 1 1 1 1
Five stage pipelined single precision to double precision
conversion accepts a 32-bit single precision floating point data
input and produces a 64-bit double precision floating point
Data out Comp Zero Invalid Inexact Overf1ow Underflow
output. Number format analyzer classifies the data input as
Fig. 2: Top level architecture of conversion co-processor zero, infmity, QNaN, SNaN, de-normalized number and
Normalized number. Output of the format analyzer is passing

The floating conversion co-processor accepts the data through either "path1" or "path2" based on the data input

inputs through the "data in" pin and a 3-bit as rounding mode classification. If the single precision data input is a de

for operation. The "opcode" (4-bit) field specifies which normalized number, uses the "path1" of the micro-architecture.

conversion to be carried with the data input and rounding Else, if the data input is other than de-normalized number it

mode. The input decoder decodes the opcode and enables the uses the "path2" of the micro-architecture.

specified conversion operation. Output de-multiplexer take the

output from bus along with exception signal and gives the
 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

single_prec_data_in (32-bit)
architecture of a 5-stage pipelined double to single precision

l
conversion is shown in Fig 4.

Number format Analyzer

1
.. ..., . . . . . . . . . . . . . J. . . . . . . . . . . . . . l
Number format Analyzer
Leading one Single precision
algorithm Bias remove
. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .
,

1 1 Leading one
algorithm
Double precision
Bias remove
Leading position Double precision

1 1
calculation Bias addition

1 1 Leading position
calculation
Double precision
Bias addition
Double precision Bypass stage
Bias addition
1 1
oath] t. . . . . . . . . . . . . . . Path2 t. . . . . . . . . . . . . . Rounding De-
normalized
Round
Normalized

J
Double precision number formation

Path]
1 Path2

l
................................. ................................
..

double_p'" _ a_out (64-bit) Double precisIOn number formation

Fig 3: Micro-architecture of single to double precision

conversion
singlerec_data_out (32-bit)

If the data input is a de-normalized number, first calculates Fig 4: Micro-architecture of double to single precision
the leading one of the mantissa including hidden-bit. Then the conversIon
leading one position block calculates the position of the leading
one in the mantissa. Third block adds the double precision bias Number format Analyzer unit, accepts the double precision
(1023) to the leading one position of the mantissa to form the floating point data and analyses the data input such as Zero,
double precision bias value. The final stage forms the double QNaN, SNaN, de-normalized number and normalized number.
precision floating point number based on the sign, exponents, If data input is de-normalized number, then "path1" is used for
and Mantissa. If the input data is a normalized number, it uses the conversion or else "path2" is used for the conversion. In
the "path2" of the micro-architecture to form the double path I, it follows through the leading one algorithm stage to
preCISIOn floating point data output. It removes the single calculate leading one position in the number and calculates the
precision bias value from the exponent and adds the double exponent in the number and adds the single precision bias.
precision bias value. The 23-bit mantissa from the single Since the mantissa of the double precision data input is 53-bit,
precision floating point data is padded with zero's to form the a rounding operation is performed to truncate the mantissa to
52-bit mantissa of the double precision floating point data 23-bit. The final stage concatenates the sign, exponent and
output. The final stages stage uses the sign, exponent and mantissa to form the single precision data output.
mantissa from "path2" to form the 64-bit double precision data
output. If the data input is a normalized number then "path2 is used
The selection of the sign, exponent and mantissa from for conversion. First it removes the double precision bias from
"path I" or "path2" is based on a status signal from the number the single precision exponent by subtracting the 1023, and then
format analyzer. The rounding operation is not required for the it adds the single precision bias value (127). After the exponent
conversion from the single precision to double precision addition, a 52-bit mantissa is truncated to 23-bit by using the
floating point data. rounding mode specified as the input. The final stage
concatenates the sign, exponent and 23-bit mantissa to form the
B. Double precision to single precision conversion
single precision floating point data output.
The double to single precision conversion accepts the data
input in double precision floating point format and outputs the
result in single precision floating point format. The micro-
 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

C. Floating point to fixed point conversion

Single and double precision floating point to fixed point Data_in((Q16.15) or (Q32.31))
conversion unit accepts the input data as either in single or
double precision floating point format and produces the result
in (Q16.15) for single precision and format and (Q32.31) for Absolute value calculation
double precision format. Fig. 5 shows 5-stage pipelined micro
architecture the conversion of floating point number to fixed
point number.
Format analyzer

Data_in(32 or 64)

Leading one algorithm

Preprocessing stage

Leading one position calculation

Shift amount calculation

Exponent calculation

Number decoding stage

Post processing stage

Rounding

Data_out(single or double)

Post processing stage Fig 6: Micro-architecture of floating point to fixed-point

conversIon

Data_out((Q16.15) or Q(32.31)) Absolute value calculation stage accepts the fixed point
input data in 2's complement form and performs the 2's
Fig 5: Micro-architecture of floating point to fixed-point complement operation on input data to make the absolute
conversion value. Format analyzer, analyses the input data in-terms of
zero, de-normalized number and normalized number and sign
Pre-processing stage accepts either single preclSlon or of the data input and provides a 3-bit status register indicator to
double precision floating point data input, and analyses data the consecutive stages. The 2-stage leading one algorithm and
input such as zero, infinity, QNaN, SNaN, de-normalized and leading one position computes the leading one in the input
normalized number. Also this stage separates the sign, fixed point data and calculates the position of the leading one
exponent and Mantissa. Shift amount calculation stage in the data. Exponent calculation stage adds or subtracts the
removes the bias from the exponent (127 for single precision bias value (127 for single precision and 1023 for double
and 1023 for double precision). Number decoding stage precision) to leading one position. If the input data is de
separates the integer part and fractional parts from mantissa normalized number leading one position value is subtracted
based on the shift amount. Rounding operation is performed to from bias value or, if the input data is normalized number bias
make the output in either Q16.15 format or Q32.31 format. value will be added to leading one position. Also in parallel
Post-processing stage check the status of the number and with exponent calculation stage, it will calculate the mantissa
results the appropriate results in 2's complement form. All the of the output from the fixed point data input. The post
results from floating point to fixed point conversions are processing stage forms the single or double precision floating
displayed in 2's complement form. point data by using mantissa, exponent and sign.

D. Fixed point to floating point conversion . Integer to floating point conversion

Fixed point to floating point conversion unit accepts data
input either in Q16.15 or Q32.31form and produces result in
either single and double precision floating point respectively.
Fig. 6 shows the micro-architecture of 6-stage fixed point to
floating point conversion.
The integer to floating point conversion unit accepts 32-bit
signed or unsigned binary number and converts to either single
or double precision floating point number based on the
selection. Fig. 7 shows the micro-architecture of integer to
floating point conversion.
 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

sign of the input floating point data is negative, the fmal result
Data_in(32-bit) is represented in 2's complement form. Also this stage
generates a valid signal to indicate whether the 32-bit data is
valid or not.
Pre-processing unit

Oata_in(32 or 64)

Lead one algorithm unit

Preprocessing stage

Lead one position calculation

Integer formation stage

Rounding unit

Rounding stage

Post processing unit

Post processing stage

Data_out (Single/Double)

Data out (32-bit)

Fig 7: Micro-architecture of integer to floating point
conversIOn
Pre-processing unit accepts a 32-bit signed or unsigned
integer and, if the operation is signed conversion, performs a
2's complement operation on signed data otherwise, bypass
unsigned integer to the next stage. Once the pre-processing is
completed, a 32-bit data from pre-processing unit is passed to
the 2-stage lead one algorithm and position calculation stage to
calculate the exponent and mantissa from the input data. After
the leading one operation, conversion unit performs a rounding
on mantissa based on input rounding mode. The fmal stage,
post processing unit concatenates the sign, exponent and
mantissa for the single or double precision floating point data
conversion.
F. Floating point to integer conversion
The floating point to integer conversion unit accepts double
and single precision floating point data input and produces a
32-bit integer in 2's complement form. Fig.8 shows the micro
architecture of the floating point to integer conversion.
Pre-processing stage accepts either a single or double
precision floating point data input in IEEE 754 format and
Fig 8: Micro-architecture of floating point to integer
conversion
For single precision the maximum exponent supported is 23
and for double precision the maximum exponent supported is
52. The bias above the threshold limit is signaled with
overflow signal.
V. SIMULATION, VERIFICATION, SYNTHESIS AND TESTING
The conversion sub-modules developed using VHDL, are
simulated by using ModelSim and synthesized using Xilinx
ISE 14.l. The conversion co-processor is implemented and
tested on Xilinx Virtex 6 "xc6vlx550t-2ffl759" FPGA. The
input test vectors are generated using a high level language
("c") and applied to the Device Under Test (OUT) and also to
the matlab tool. The matlab tool generated outputs are
considered as the golden output and are compared against the
outputs from the OUT. The comer cases manually applied to
the OUT and verified the functionality. Once the individual
modules are verified, these modules are integrated to the top
modules and assigned with an opcode as specified in the table
1. Fig 9 shows the device utilization summary of the single
core conversion co-processor.
D "' V :1 c "" uti :L i zation !"Jumrnar-y:

analyses the data input format and generates a 4-bit status

(Norm, de-norm, NAN/INF and zero) signal. Also this unit 5 1 ic "" Logic: Utilization:
Nunlb",r 01" 5 1 i """, R "' gi"'t",r",, : 3 2 "15 6 87360

extracts the sign, exponent and mantissa according to the IEEE Nuzub c:: r
Nuntb ", r
01" S 1i c c:
u "' .. d
LOT.,.:
... ,.. LO<;Jic::
67 6 3 313660

754 standard. Integer formation stage removes the bias from 5 1 1 C'"
Nuznb.er
Log.i.C:
01" LOT
Di "" tribut.i.on:
F.l.;1.p F.1. op pair", u", ,,,, d:

the exponent and generates a 31-bit data (mantissa with hidden Nllltlb .. r with a.... unu """,d F1ip F1op: 600
Number with an unu sed LOT: .1374 B 1 37 .16"
Nunlber 01" 1"ul..J..y u ::s ed LOT-FF pai
. r!"J: .l. B7.l. 8 3. 37

bit and 3-bit offset for rounding) also in this stage generates
inexact and overflow exceptions. Rounding stage performs the
1:0 Ueil.i. z .. e i.on:
NlllDb",r- 01" 1:0",,:

rounding based on the rounding inputs. Post processing stage Sp ..c:i1"ic: F.. ... tur '" Ut 1 1 .i. zation:
Nunlb .. r 01" BUFG/ BUFG CT R L ", :

analyses the input form and if the input format is normalized

and generated a 32-bit data based on the sign of the data. If the Fig 9: Device utilization of conversion co-processor
 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

VI. ANALYSIS AND APPLICATIONS REFERENCES

The implemented individual conversion modules are [1] IEEE standards Board and ANSI. IEEE Standards for Binary
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In this research article we proposed a novel architecture for
the conversion co-processor suitable for hybrid computing. The
conversion co-processor is fully compliant with the IEEE-754
2008 standard. The conversion co-processor is implemented
and tested on Virtex 6-xc6vlx550t-2ffl759. The co-processor
achieved a throughput of 350 MFLOPs per second on Virtex-6
FPGA with limited number of pipeline stages.
Future work includes, exploring other ways to improve
flexibility, such as an adaptive muti-mode floating point unit or
reconfiguring the computation components within floating
point conversion units to perform other functions. Furthermore
in our current design only classic floating point conversion
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VIII. ACKNOWLEDGEMENT [14] C. Hinds, "An Enbanced Floating Point Coprocessor for
Embedded Signal Processing and Grapbics Applications,"
The research work presented here was supported by Centre
Conference Record of the Thirty-Third Asilomar Conference on
for Development and Advanced Computing (C-DAC),
Signals, Systems, and Computers, pp. 147-151, 1999
Knowledge Park, Sengaluru. The authors would like to thank
[15] Altera Floating Point Megafunctions.
Dr. N. Sarat Chandra Sabu (Executive Director) for giving the
http://altera.com/products/ipidsp/arithmetic/m-alt-float
opportunity to carry out the research work. point.html.