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Book Title Proceedings of International Conference on ICT for Sustainable Development
Series Title
Chapter Title Bio-inspired Ultralow Power Design of Comparator with Noise Compensation Using Hysteresis Technique
Designed for Biomedical Engineering (Pacemaker)
Copyright Year 2016
Copyright HolderName Springer Science+Business Media Singapore
Corresponding Author Family Name Jain
Particle
Given Name Jubin
Prefix
Suffix
Division
Organization Geetanjali Institute of Technical Studies
Address Udaipur, India
Email jubincb2@gmail.com
Author Family Name Maurya
Particle
Given Name Vijendra
Prefix
Suffix
Division
Organization Geetanjali Institute of Technical Studies
Address Udaipur, India
Email
Author Family Name Mehra
Particle
Given Name Anu
Prefix
Suffix
Division
Organization ASET, Amity University
Address Noida, India
Email

Abstract With the emerging development of advanced trends in biomedical engineering finding its application in
various biomedical electronic devices such as ECG, EEG, temperature sensing, blood pressure, and
pacemaker, the biopotential signals are picked-up in small portable battery operated devices. The major
concerned is about the power consumption of the electronic circuitry used in biomedical devices as well as
the noise obtained from the muscular contraction and expansion, which is responsible for the interference
to the signal to be measured. Hence, compensation circuitry is needed to remove noise. The comparator is
a CMOS VLSI circuit which compares an analog signal with another analog signal and generates digital
output due to comparison. The project is to show case the low power consumption of comparator proposed
for pacemaker device having modest speed and producing less delay. The technique proposed to design the

Keywords (separated by '-')
comparator in order to improve the performance is hysteresis by providing feedback. The advantage of
introducing hysteresis in comparator is to compensate the noise at output signal, when operated in noisy
environment. The comparator using hysteresis is designed in 0.18 CMOS technology operated at bias
voltage of 1.8 V. The circuit is designed and simulated in TANNER EDA.
Power consumption - Hysteresis - Delay - Noise - Biologically inspired - Long battery life of implantable
devices - Analog-to-digital conversion
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1 Bio-inspired Ultralow Power Design

2 of Comparator with Noise Compensation

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3 Using Hysteresis Technique Designed
for Biomedical Engineering (Pacemaker)

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4

5 Jubin Jain, Vijendra Maurya and Anu Mehra

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6 Abstract With the emerging development of advanced trends in biomedical
7 engineering nding its application in various biomedical electronic devices such as
8 ECG, EEG, temperature sensing, blood pressure, and pacemaker, the biopotential
9 signals are picked-up in small portable battery operated devices. The major con-
10 cerned is about the power consumption of the electronic circuitry used in
11 biomedical devices as well as the noise obtained from the muscular contraction and
12

13
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expansion, which is responsible for the interference to the signal to be measured.
Hence, compensation circuitry is needed to remove noise. The comparator is a
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14 CMOS VLSI circuit which compares an analog signal with another analog signal
15 and generates digital output due to comparison. The project is to show case the low
16 power consumption of comparator proposed for pacemaker device having modest
17 speed and producing less delay. The technique proposed to design the comparator
18 in order to improve the performance is hysteresis by providing feedback. The
EC

19 advantage of introducing hysteresis in comparator is to compensate the noise at

20 output signal, when operated in noisy environment. The comparator using hys-
21 teresis is designed in 0.18 CMOS technology operated at bias voltage of 1.8 V.
22 The circuit is designed and simulated in TANNER EDA.

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23 Keywords Power consumption Hysteresis Delay Noise Biologically

24


inspired Long battery life of implantable devices Analog-to-digital conversion
25
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J. Jain (&)
V. Maurya

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Geetanjali Institute of Technical Studies, Udaipur, India

e-mail: jubincb2@gmail.com
A. Mehra
ASET, Amity University, Noida, India

Springer Science+Business Media Singapore 2016 1

S.C. Satapathy et al. (eds.), Proceedings of International Conference
on ICT for Sustainable Development, Advances in Intelligent Systems
and Computing 409, DOI 10.1007/978-981-10-0135-2_28
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2 J. Jain et al.
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26 1 Introduction

With the day by day augmentation in the eld of biomedical implantable devices

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27

28 that are portable and battery-driven devices, power consumption has become a
major issue of research so that the battery life can be enhanced for a longer time

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29

30 period. The rising surge of research in the eld of low power CMOS circuits for
31 implants is supported by the rising need to extend the battery life of portable
32 implants. In accordance to this, sensing biopotentials with various portable elec-
33 tronic devices there is rm requisition of ADCs with high degree of efciency,
34 which can done by optimizing the critical components of ADC among comparator,
as proposed in this paper. Comparators nd their application in analog-to-digital

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35

36 converters (ADCs), data transmitting applications, power regulators based on

37 switching, and many other medical applications. With low voltage supply it has
38 become a difcult task to design a comparator. Under such a situation it is needed to
39 compensate the low voltage supply. The W/L ratio has to be increased, though it
40 will let the area of chip to increase as well power consumption. To operate under
41

42

43
down the power consumption as well at good operating speed.
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low voltage condition the W/L ratios are required to be dened in order to lower

There are two issues that can be improved to achieve great performance of
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44 open-loop comparator with some endeavor. These elds are regarded as input offset
45 voltage and a single transition of comparator in noisy environment, as in the
46 presence of noise during transition extra power consumption is committed. The rst
47 issue can be improved by using auto-zero technique and second issue by intro-
48 ducing hysteresis with essence of bistable circuit.
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49 By feeding back the small portion of output voltage to the positive input, the
50 hysteresis is introduced in comparator circuit. The feedback voltage is added to
51 polarity-sensitive voltage which results in increased threshold voltage and proves to
52 be fruitful on account of causing reduction in circuit sensitivity toward noise and
53 also eradicates the multiple number of transitions when input changes slowly.
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54 The paper is structured as follows: A conventional two-stage open-loop comparator

55 is designed, simulated, and the concerned parameters are analyzed in 0.18 technology
56 operated at 3.3 V. Section 2 is dedicated to improved version of comparator which gives
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57 the paramount parameters such as power consumption, delay, and noise eradication.
58 The conventional and improved version of comparator parameters are compared.

2 Comparator Design
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59

60 2.1 Conventional Design of Two-Stage Open-Loop

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61 Comparator

62 The comparator is the integral part of an ADC design and is used for converting
63 analog-to-digital signal where rst the signal is to be sampled and then compared
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Bio-inspired Ultralow Power Design of Comparator 3

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64 with reference signal considered as 1-bit A/D converter. Op-amp without com-
65 pensation is considered as open-loop comparator. Differential input and sufcient
66 gain is required to achieve the desired gain. The open-loop comparator without

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67 compensation has larger bandwidth in comparison to comparator with compensa-
68 tion as it gives faster response. The conventional two-stage amplier consists of

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69 three stages with the inverter connected to the nal stage. The stage comprises the
70 following stages: differential amplier stage, common-source amplier stage, and
71 the inverting buffer. The bias current provided to the circuit is 1 A. The circuit
72 consists of current mirror which simply copies current from the reference source
73 such that the reference current is mirrored to the rst two gain stages which
74 accounts for the total current at 3 A. The circuit differential stage comprises of

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75 NMOS since the mobility of NMOS is considered to be greater in comparison to
76 PMOS, whereas in circuit IN1 denotes the input analog signal and IN2 is consid-
77 ered as reference signal. With the need for improvement in the gain of rst stage, it
78 is required to lower the input offset voltage by increasing the width of NMOS
79 transistor. In the presence of parasitic capacitance transistor PMOS_3, which is
80 responsible for causing delay in circuit, the area of CS amplier is increased and the
81

82
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inverter buffer stage which is responsible for adding the needed gain along with
risen slew rate simply causes the comparator to operate in high speed applications.
The problems associated with the design are as follows: when the two-analog input
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83

84 goes to zero, even a small amount of noise overrides the signal causing fluctuation in the
85 output of comparator. Due to fluctuation, glitches are produced causing unnecessary
86 power consumption. Hence, output gets affected in the presence of noise in input signal.
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87 2.2 Design of Comparator Using Hysteresis

88 Often it happens that comparator operating in noisy environment needs to detect

transitions at the threshold points. Depending on the frequency of detected signal, if
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89

90 the comparator is fast enough and amplitude of noise is large, the presence of noise
91 will result in the output of comparator. Efforts in modication of transfer charac-
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92 teristics are desired which can be achieved by hysteresis.

93 The previous design characteristics were affected with presence of noise. So as to
94 eradicate noise the concept of hysteresis was introduced, Hysteresis is dened as the
95 difference between the upper threshold voltage (VTH) and the lower threshold
96 voltage (VTL) for which the output switches to a higher value and a lower value
respectively. Circuit sensitivity toward the noise and multiple transitions are
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97

98 reduced at the output using this technique.

99 Hysteresis is considered as the degree of quality for comparator in which input
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100 threshold changes with the change in input signal. When the input crosses the
101 threshold it results in changes in output and subsequently threshold is reduced such
102 that input must return the previous threshold and again the output changes. The
103 intention behind the technique is simply that output needs to follow the low fre-
104 quency signal.
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105 There are many ways by which hysteresis in the comparator can be introduced, all
106 of which make use of positive feedback, categorized as Internal methods and External
107 methods. In internal method internal hysteresis is implemented into comparator while

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108 in external hysteresis, hysteresis is introduced after the circuit is built up.

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109 2.3 Working of Hysteresis-Based Comparator Circuit

110 To reduce the impact of noise on the circuit a small amount of hysteresis is
111 introduced in the conventional comparator circuit design. An unbalanced differ-

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112 ential circuit is added in the comparator circuit. The modied comparator design
113 can be seen in Fig. 3.
114 The goal of achieving hysteresis can be achieved using internal positive feed-
115 back. Basically there are two paths for feedback in the differential input stage
116 design. The rst feedback is attained by NMOS_1 and NMOS_2 transistors, which
117 is current series feedback obtained by CS conguration so that it is considered as a
118

119
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negative feedback. The second path is considered as a positive feedback obtained
from the gate-drain connection of PMOS_2 and NMOS_6, which is simply the
voltage-shunt feedback. If the positive feedback is less than the negative feedback
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120

121 then hysteresis is absent. But in the case the negative feedback becomes lesser than
122 the positive feedback, hysteresis will be introduced in the circuit.
123 The output stage comprises of inverter plus unbalanced differential pair con-
124 gured at input. A second differential pair comprises of two transistors,
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125 NMOS_5-NMOS_6, responsible for unbalancing the input differential pair. It can
126 be seen in the gure that the gates are tied to the output signals, which is
127 responsible for establishing positive feedback.
128 The hysteresis bias current for the second differential stage is provided by the
129 current mirror composed from the transistor denoted by NMOS_8-NMOS_7. The
size of second differential pair must be kept small so as to introduce the little
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130

131 parasitic capacitance at the input differential stage. By varying the hysteresis current
132 the hysteresis can be programmed.
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133 As a result it can be seen from the waveform spike removed which is mainly
134 responsible for causing power consumption at increased rate.

135 2.4 Figures and Tables

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136 2.4.1 Schematic of Two-Stage Comparator Without Hysteresis

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137 The schematic of conventional two-stage comparator is designed using 250 nm

138 technology powered with bias voltage of 3.3 V using S-Edit and waveform is
139 obtained using W-Edit (Fig. 1). AQ1
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Bio-inspired Ultralow Power Design of Comparator 5

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Fig. 1 Schematic of two-stage comparator without hysteresis D
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Fig. 2 Waveform of comparator without hysteresis

140 The waveform indicates the presence of glitch when input time reaches zero and
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141 results in increased power consumption. During zero-crossing multiple transitions

142 take place (Fig. 2).
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143 2.4.2 Design of Comparator Using Hysteresis

144 The schematic of improved design of comparator using hysteresis designed in

145 0.18 technology with bias voltage of 1.8 V (Fig. 3).
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146 Waveform of improved design comparator using hysteresis. Hence, it can be

147 observed the absence of glitch as it is indicated, the circuit is insensitive to the noise
148 present in the input signal. When input IP(+) > In1() the output will be 1.8 V. Vice
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149 versa, if IP(+) < In1(), the output will be 0 V (Fig. 4).
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B & W IN PRINT
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Fig. 3 Schematic of comparator using hysteresis

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Fig. 4 Waveform of comparator using hysteresis

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150 2.4.3 Table for W/L Ratios of Comparator Using Hysteresis

152

153
154 Circuit design Transistor W/L ratio M
155 Input differential PMOS_1, PMOS_2 5.40 /0.18 4
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156
157 pair NMOS_1, NMOS_2 5.40 /0.18 , 2.50 / 4, 1
0.25
/0.18
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158 Differential pair NMOS_5, NMOS_6 3.60 2

159 stage II
160 Current mirror NMOS_7, NMOS_8 5.40 /0.18 2
161 Output buffer PMOS_4, NMOS_10 5.40 /0.18 4, 2
162 inverter
163 Inverter PMOS_5, NMOS_11 5.40 /0.18 , 2.50 / 4, 1
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0.25
164 Switches NMOS_3, NMOS_4, PMOS_3, 5.40 /0.18 2, 2, 4,
NMOS_9 2
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165
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167

168
169 Current source Current
170 Current source_1 1 A
Current source_3 47 nA

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172

173

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174 2.4.4 Comparison and Analysis Table Between Comparators
176

177 Comparator without hysteresis Comparator with hysteresis

178 Technology 250 nm 180 nm

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179 Voltage supply 3.3 V 1.8 V
180 Delay 46.55 ns 43.90533 ns
181 Power consumption 458 nW 411 nW
182 Current consumption 5 A 3.11 A
183 AC_Measure_Gain_1 4.5749e+001 1.2257e+002
184 Bandwidth 1.0000e+006 1.0000e+004
185

186
Slew rate
Trip point (VTRP+, VTRP)
0.22 V/m s
+1.36 V, 1.25 V
D 0.047 V/m s
+ 0.32 V, 0.32 V
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187

188

189 2.4.5 Graphs

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190 See Fig. 5.

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Fig. 5 a Analysis between delay and technology. b Analysis between power consumption and
MOS technology
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191 2.5 Formulas

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192 It is assumed that positive and negative supplies are used such that the NMOS_1 is
193 tied to the input signal and NMOS_2 is tied to the ground. In case input is less than
zero, then NMOS_2 will be turned on and NMOS_1 will be driven to cut-off state.

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194

195 This is responsible for turning on PMOS_1 and PMOS_2 resulting in iNMOS_4 to
196 flow through PMOS_1 and NMOS_1 causing Vout to go high. It is to be noted that
197 NMOS_2 is driven in cut-off state.
198

iPMOS 2 W=LPMOS 2 iNMOS 4 =W=LPMOS 1

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200

201 As the input signal crosses the threshold value some of the tail current starts to
202 flow through NMOS_2 and it will flow till it becomes equal to the current asso-
203 ciated with PMOS_2. As a result beyond it the comparator tends to change the state.
204 It is mathematically represented.
205

iPMOS W=LPMOS 2 iPMOS 1 =W=LPMOS 1

207
2

INMOS 2
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IPMOS 2
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209 INMOS 4 INOMS 1 INMOS 2 INMOS 1 IPMOS 1

211 IPMOS 1 INMOS 4 =1 W=LPMOS 2 =W=LPMOS 1  INMOS 1

INMOS INMOS  INMOS

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213 2 4 1
215

216 When the current through the NMOS_1 and NMOS_2 is known, it becomes
217 possible to calculate the VGS voltages. Since the NMOS_1 gate is ground,
218

Vgs1 2Inmos 1 = 1 VT1

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Vgs2 2Inmos 2 = 1 VT2

220
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221 2.6 Program Code

222 Designed conventional comparator schematic is extracted in T-Spice and spice le

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223 is generated as shown below.

224
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228
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229 3 Conclusion

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230 As a result of simulation and analysis done using TANNER EDA and its tools, it is
231 observed that the noise is eradicated using hysteresis concept in comparator, though
with noise compensation, the bandwidth is reduced. Power consumption is reduced

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232

233 in the circuit due to removal of glitches or spikes that are major factors affecting
234 power consumption, thereby supporting longer battery life of implants. Although
235 the interfering signal mixed with the biomedical signal to be detected does not
236 propose any impact on circuit performance, the circuit is insensitive with respect to
237 noise. The current consumption of comparator using hysteresis is also less. The

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238 circuit is allowed to be operated at lower voltage supply, which is paramount for
239 implantable devices. Finally, some endeavors can be made to reduce delay of the
240 circuit and improve bandwidth. AQ2

241 Acknowledgments The authors would like to thank Geetanjali Institute of Technical Studies,
242 Udaipur for providing support to carry out the project successfully by guiding and providing the
243 design tools.
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244 References

245 1. Babayan-Mashhadi, S., & Lot, R. (2014). Analysis and design of a low-voltage low-power
246 double-tail comparator. IEEE J. VLSI Syst. 22 (2014).
247 2. Chasta, N. K. (2012). High speed, lowpower current comparators with hysteresis. Int. J. VLSI
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248 Design Commun. Syst. 3(1).

249 3. Sarpeshkar, R. (2010). Ultra low power bioelectronics: fundamentals, biomedical
250 applications, bio-inspired signals. Cambridge University Press.
251 4. Kargaran, E., Khosrowjerdi, H., & Ghaffarzadegan, K. A 1.5 V high swing ultra-low-power
252 two stage CMOS OP-AMP in 0.18 m technology. In International Conference on
253 Mechanical and Electronics Engineering (ICMEE 2010).
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254 5. Mesgarani, A., Alam, M. N., Nelson, F. Z., & Ay, S. U. (2010). Supply boosting technique for
255 designing very low-voltage mixed-signal circuits in standard CMOS. In Proceedings of IEEE
256 International Midwest Symposium Circuits System Digital Techniques Papers (2010).
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257 6. Zhang, H., Qin, Y., & Hong, Z. (2009). A 1.8-V 770-nW biopotential acquisition system for
258 portable applications. In IEEE Proceedings Biomedical Circuits and Systems Conference.
259 7. Kulkarni, V. B. Low-Power CMOS Comparators with Programmable Hysteresis. Master
260 Technical Report (2005).
261 8. Sauerbrey, J., Schmitt-Landsiedel, D., & Thewes, R. (2002). A 0.5 V, 1 W successive
262 approximation ADC. IEEE Journal of Solid State Circuit. IEEE.
263 9. Yan, S., & Sanchez-Sinencio, E. (2000). Low voltage analog circuit design techniques: A
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264 tutorial. IEICE Transactions on Analog Integrated Circuits and Systems, E00-A(2).
265 10. Allen, P. E., & Holberg, D. R. CMOS analog circuit design, 2nd edn. Oxford University Press.
266 11. Louis, S. Y., & Wong, R. O. A very low power CMOS mixed-signal IC for implantable
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267 pacemaker applications.

268 12. Geiger, R. L., Allen, P. E., & Strader, N. R. (1990). VLSI design techniques for analog and
269 digital circuits. McGraw-Hill Inc.
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