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CIPS 2016 - 9th International Conference on Integrated Power Electronics Systems

Monitoring of IGBT modules temperature and degradation simula-

Kristian Bonderup Pedersen1, Mads Brincker1, Pramod Ghimire2, Kjeld Pedersen1
Department of Physics and Nanotechnology, Aalborg University, Denmark
Department of Energy Technology, Aalborg University, Denmark

This paper presents an overview of the challenges in online monitoring of on-state voltage in high power insulated gate
bipolar transistor modules used for temperature and degradation assessment. Through a detailed simulation approach,
based on the finite element method, an estimation of the impact on on-state voltage from inhomogeneous temperature
fields and material degradation of interconnects are presented. Temperature estimation from on-state voltage is normal-
ly based on a steady state calibration procedure which compared to real life application with dynamic loads are insuffi-
cient. Similarly, change in on-state voltage from degradation of multiple interconnects is difficult to separate into spe-
cific contributors and thereby apply in lifetime estimation models. Therefore simulation results are sought combined
with experimental data to increase accuracy of estimation of temperature and degradation of individual elements.

1 Introduction mechanical induced degradation of interconnects bond

wire fatigue, solder fatigue, metallization reconstruction,
In power electronic systems, device reliability has always etc. [6]. All of these affect the on-state voltage in different
been a key element. Especially with regard to semicon- ways and thereby online temperature as well as degrada-
ductor devices, being the primary active part of a system, tion assessment.
maintaining a high degree of reliability is crucial [1]. In this paper the potential pitfalls in temperature esti-
While reliability has been greatly improved in recent mation from is discussed from a theoretical perspec-
years the demands are also increasing. Additionally, load tive together with presenting possible monitoring strate-
specifications as well as surrounding environment are
gies trying to overcome this. Additionally, the impact on
continuously changing [2]. Taking this into consideration,
on-state voltage from degradation of interconnects is sim-
monitoring component performance through online pa-
ulated using 3D finite element models (FEM) and are
rameters is an intelligent way to catch possible problems
prior to catastrophic failure by substituting the device or compared to experimental data. This is introduced to fully
calibrate the loading according to device limitations [3]. understand the time evolution of the during a device
Monitoring of collector emitter and forward voltage, lifetime.
respectively ( ), in high power insulated gate bipolar
transistor (IGBT) modules, is commonly used for estimat- 2 Online monitoring
ing load through the semiconductor chip junction temper-
ature and degree of degradation by change in interconnec- The following section is divided into two branches tem-
tion resistance [3], [4] [5]. The reason for monitoring par- perature estimation and degradation assessment from on-
ticularly the junction temperature as the primary stressor state voltage, respectively.
is based on the commonly known impact on device life- Simulation data are compared to online monitoring
time from increase in junction temperature variation ( ). data from two test setups. A standard DC pulse test [10]
The coupling between device lifetime and has for and a more advanced active power cycling setup [11]. The
many years been modelled using the Coffin-Manson former is a standard accelerated test setup where the de-
(CM) model: [6] [7] vice is heated with a high DC current pulse and after-
wards cooled down. The latter simulates conditions simi-
. (1) lar to a doubly fed induction generator for wind power
conversion. Monitoring methodologies are identical for
While the CM model has been updated on several occa- both systems and are discussed in detail in [11].
sions to include additional degradation contributing fac-
tors [6] [8] [9], the CM power law connection between 2.1 Temperature estimation from TSEPs
and number of cycles to failure ( ) remains the same. Temperature estimation from thermoelectric sensitive pa-
This indicates the impact from running a device under el- rameters (TSEPs) is an approach normally used for devic-
evated temperature conditions, and therefore the necessity es in real life operation. Other estimation methods like
of online monitoring. thermocouples or IR thermography is limited by compo-
However, obtaining accurate temperatures as well as nent accessibility or equipment limitation. The general
degradation estimations from on-state voltage is compli- idea of estimation from TSEPs is to use the device chips
cated due to several reasons. Power modules subjected to as sensors (internal gate resistor, gate threshold voltage,
power cycling conditions normally fail from thermo- collector-emitter voltage, etc.) [5]. In field use, it is most

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CIPS 2016 - 9th International Conference on Integrated Power Electronics Systems

convenient to use the to estimate chip temperature connection, the bond wires provide an alternative thermal
( ) from calibration data. The problem with this ap- route but orders of magnitude from the primary path [13].
proach is to determine the proportionality between The difference in the purpose of the interconnections
and [4]. This is normally sought solved by doing a highly reflects the impact on the on-state voltage. Bond
-calibration under steady state conditions, e.g. by wires and metallization are primarily electrical contacts
placing the device on a hot plate at a given temperature and as such degradation of the connections are expected
and obtaining the after reaching steady state. If carried to directly affect the device resistance. In contrast due to
out at several temperatures this yields a calibration matrix the volume of the soldered connection fractures are not
from which the online temperature can be estimated from expected to have significant impact on electrical proper-
ties of the device, but more the thermal impedance.
the [12]:
Therefore changes in are expected to be more indirect
through an increased chip mean temperature [3].
, (2)
For degradation monitoring two strategies are neces-
sary in order to monitor interconnections on both chip
where is the temperature coefficient, and are sides:
the reference parameters from calibration.
In steady state conditions this connection is clear. , (4)
With enough calibration points and a constant tempera-
ture field the linear approximation of Eq. (2) yields accu-
rate results. However, in real life operation the chip tem- , (5)
perature is not homogeneous and a difference in surface
temperature from center to edge of up to is not un- where is the mean on-state voltage at the measure-
common [4], this needs to be corrected for. Additionally, ment current ( ) of the first 100 cycles, and the (+/-) sign
depending on the calibration time another correction indicate the measurement is taken with a time difference
might have to be inserted to ensure contributions from in between but at same current. The time difference there-
power loss heat-up during calibration. Both of these as- by displays the chip thermal impedance. Accordingly,
pects are included in the presently used temperature esti- displays changes in electrical resistance and the
mation model: thermal response.
To use the change in on-state parameters it either has
(3) to be coupled with an absolute failure criteria (increment
of of or of thermal re-
where is the temperature correction from heat-up sistance from [3] and the LV324 standard, respective-
during calibration, and is the contribution from a ly) or lifetime estimation models, see Figure 1.
non-homogeneous chip temperature. The former is in-
cluded directly as a temperature correction to the refer-
ence point and as shown in [11] is approximated well with
a linear thermal network model. The , however, is a
bit more complicated. An IGBT chip consists of millions
of transistor channels [13] and with a non-homogenous
temperature all of these will have a unique local tempera-
ture and thereby a different . The current distribution
will therefore depend highly on the local transistor chan-
nel and evidently affect the measured effective . This is
complicated to model analytically or from a standard elec- Figure 1: On-state from standard DC pulse test setup.
trical network. The present proposition is based on an [10]
electro-thermal FEM model with component geometry
and before mentioned calibration matrix as input.
3 Electro-thermal simulation
2.2 Degradation monitoring The effect on from temperature and interconnection
The on-state voltage used for temperature estimation is degradation is difficult to separate only from absolute
also used to monitor changes in interconnection resistance values. In the present paper the change in is simulated
[3]. In a typical IGBT module architecture the semicon- to overcome this. To simulate effects from temperature
ductor chips are soldered to a direct copper bonded fields and device degradation, these are applied to a spe-
(DCB) substrate using a standard solder paste. This con- cific geometry. Temperature fields are simulated at vary-
nection provides good electrical connection to the ing load conditions to induce a temperature gradient from
pads and the primary thermal path to the DCB backside the hot spot to the edge. Degradation is induced by utiliz-
cooling. Chip topsides are normally connected to adjoin- ing experimental data to change physical proper-
ing pads using heavy bond wires ultrasonically
ties/geometry, accordingly. In [14] and [15] bond wire
bonded to the chip metallization. Similarly to the solder
fatigue and metallization reconstruction, respectively, is
investigated experimentally by electrical parameters as a

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CIPS 2016 - 9th International Conference on Integrated Power Electronics Systems

function of number of cycles. This is implemented into imental values obtained using IR thermography is com-
the electrostatic simulation on the geometry in Figure 2. pared to a simulated curve:
Simulations of the electrostatic potential are carried out
using a finite element approach based on COMSOL mul-
The equations needed to be solved are the general
electrostatic problem and the convection-reaction-
diffusion equation for the temperature field:



where are the electrostatic field and potential, re-

spectively, is the heat flux, is the heat conductivity,
is the density, and is the pressure specific heat capaci-
ty. These equations are ideal for an FEM based approach Figure 3: Calibration heat-up error on DUT HS IGBT.
which reduces the problem to specifying proper boundary The asterisk indicates experimental values obtained by
conditions. In all cases the device backside is simulated IR thermography and the solid curves are simulated.
with a Von Neumann boundary condition to represent di-
rect water cooling [13]. All other external faces are re- The heat-up calibration test presented in Figure 3 is car-
garded as thermally isolated. ried out in the advanced active power cycling setup [11].
The calibration current is raised to as quickly as
possible ( ) and is afterwards allowed to drop together
with the capacitor and inductor bank of the system. The
current drops almost linearly and after the current
is . Chip surface temperature is measured using IR
thermography on an open module painted black. The sim-
ulated heat-up curve is obtained by using a standard linear
thermal network, see [16], where the thermal impedance
values are obtained from FEM simulation on the geome-
try depicted in Figure 2.
With regards to the effect from non-homogeneous
temperature fields linear thermal networks are no longer
sufficient. To incorporate the effect from the local tem-
Figure 2: Illustration of power module geometry with perature a full 3D electro-thermal simulation need to be
regions included in the LS device electrical calculations carried out. In Figure 4 the difference in between
highlighted. Units are in [mm]. steady state conditions and an inhomogeneous tempera-
ture field is presented at various temperature differences
Primarily four problems are considered, effects on on- ( ) from hot spot to edge at several currents and varying
state voltage from: (1) calibration heat-up, (2) inhomoge-
mean temperature. To achieve these conditions the load
neous temperature field compared to calibration condi-
profile is varied while maintaining within standard test
tions, (3) degradation of interconnects, and (4) change of
thermal impedance.

4 Results
4.1 TSEP monitoring correction
Online temperature estimation from TSEPs is carried out
from a steady state calibration procedure. This gives two
clear errors calibration heating and inhomogeneous
fields in real application.
Calibration heat-up depends primarily on two parame-
ters: calibration time and peak current. The mean temper-
ature will cause a shift as well, but this will merely
change the slope of the heat-up curve. In Figure 3 exper-
Figure 4: from inhomogeneous chip temperature.

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CIPS 2016 - 9th International Conference on Integrated Power Electronics Systems

The simulation is carried out with a load current of

Clearly the voltage difference in Figure 4 is non-linear 1000A, similar to test conditions in Figure 1, and a water
and actually has a tendency to change sign. The mean er- cooling temperature of .
ror is observed to be smaller at higher currents and mean
temperatures. 4.3 Solder degradation
Figure 6 presents the simulated change in created by
4.2 Wire fatigue and metallization reconstruction an increase in solder thermal resistance. As previously
In Figure 5 the change in effective resistance of different stated the change in electrical parameters is assumed neg-
bond wires on a chip and the chip metallization induced ligible, and therefore the only effect on chip power loss is
by power cycling conditions are presented. The effective due to an increase in mean temperature due to increase of
resistance is seen to increase proportional to the number thermal resistance. In Figure 6 five curves are presented
of cycles and depends on temperature variation. The rea- for increasing power loss conditions from as
son for spread in the specified in Figure 2 is due to the initial conditions and with a cooling water temperature of
power cycling conditions, see [11]. Furthermore, if one . The effect on chip thermal resistance from
implements the change in relative resistance into the elec- the degree of solder degradation is included as text inserts
tro-thermal model the change in is obtained, see Table in percentage. So prior to reaching the failure criteria
1: the can rise more than depending on monitor-
ing current and cooling temperature.

Figure 6: Change in from increased thermal re-

sistance through solder degradation. The text inserts
show the percentage-wise increase of chip thermal re-
sistance ( ).

5 Discussion
5.1 Temperature estimation
In Figure 3 and Figure 4 the simulated possible errors in
temperature estimation from created by calibration
heat-up and in-homogeneous temperature fields is pre-
Figure 3 presents the simulated chip heat up as a func-
tion of time with calibration current conditions at different
Figure 5: Change in effective resistance of bond wires temperatures. To validate the model experimental values
[7] and metallization sheet resistance [8] induced by ac- are obtained using IR thermography on black painted
tive power cycling (a) and passive thermal cycling (b). modules. There is a general tendency of overshoot in the
beginning and undershooting later. This is accredited to
BW fatigue Met. recon. the thermal response time of the black paint covering the
4.5mV 1.6mV chip which is not included in the thermal model. In gen-
Lift-off (new 12.9mV 3.1mV eral there appears to be good agreement between the sim-
Combined 17.9mV 4.7mV ple 1D thermal network model and the experimental val-
ues. This provides a clear indication that the calibration
Table 1: Degradation effects on from bond wire fa- procedure should be conducted as fast as possible as
tigue and metallization reconstruction. would be expected, but even so there is a clear possibility

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CIPS 2016 - 9th International Conference on Integrated Power Electronics Systems

that the estimated thermal coefficient from Eq. (2) will tions from bond wire lift-off and metallization reconstruc-
provide a temperature overshoot if not corrected. Fur- tion a clear difference in scale is observed. Prior to device
thermore, this overshoot will increase at higher tempera- failure a gradual increase of more than is observed.
tures, which are problematic as this is often the operation This can only be explained through a combined effect of
area of interest. all degrading elements with a primary contribution from
Similarly, to the error created by calibration heat-up the change in thermal resistance through solder degrada-
the difference between steady state calibration and dy- tion. Degradation impact simulations are carried out on
namic inhomogeneous field conditions seen in Figure 4 each interconnection as an isolated case. With all ele-
also present a clear error. As would be expected the dif- ments degrading gradually a cross-coupling effect is to be
ference in mean is proportional to the temperature dif- expected where the increase in effective electrical re-
ference across the chip and is proportional to the load cur- sistance cause an increase in mean temperature and there-
rent. It is clearly necessary to include corrections in the by increase the impact from high thermal resistance. This
temperature estimation equation as the difference between also indicates the problematic of using a simple power
calibration and real life application easily cause an error model as the Coffin-Manson-Arrhenius, see Eq. (1), for
of (the K-factor is normally on the scale of lifetime estimation. The model relies on fitting to experi-
depending on current level). However, the mental data under accelerated conditions and extrapola-
dependence between correction and mean temperature tion to normal operation. However, as clearly indicated
indicates that including it in praxis is a non-trivial task. At the change in on-state voltage and thereby the degree of
present the optimal solution is to conduct detailed 3D device degradation, depend heavily on the balance be-
FEM simulations of the difference under operation condi- tween failure modes which are load, environment, and
tions, see [13]. However, later it might be necessary to device dependent. This also indicate the necessity of a
validate the error estimation by local probing of the chip new monitoring protocol as introduced in Eqs. (4)-(5) to
under transient and steady state conditions. separate change in electrical and thermal resistance.

5.2 Interconnection degradation

6 Conclusion
Sections 4.2 and 0 present the effect on from intercon-
nection degradation through change of electrical and The present paper focus on two aspects in online monitor-
thermal resistance. ing from a theoretical point of view: temperature estima-
Simulation of effects on from degradation of inter- tion and degradation monitoring.
connects verifies earlier theories that metallization degra- The former is focused on temperature estimation from
dation may cause gradual wear over time and lift-off the on-state collector-emitter voltage ( ). The purpose is
cause singular bumps, see [11]. However, the gradual ef- to ensure the device always operate within product speci-
fect from metallization reconstruction is not linear, but fications and to provide information which may be used
more resembling an s-curve with different phases [15]. for device load optimization and lifetime estimation. The
This means the contribution from it flattens out in the fi- commonly used approach is that one calibrates the device
nal phase. Furthermore, wire fatigue also contributes to of interest under steady state conditions and obtains a
gradual increase in due to fracturing of wire interfac- temperature coefficient. Two clear problems arise with
es. If one regards all wires to be degraded at the lowest the concept: calibration heat-up and non-homogeneous
level observed in a wire from experiments the change in temperature fields. These are outlined and investigated
is significant, see Table 1. theoretically. Calibration heat-up is simulated using a
Figure 6 presents the change in from an increasing simple 1D thermal network with good agreement to ex-
chip thermal resistance through solder degradation. By perimental data, see Figure 3. A clear tendency of a cali-
imposing a virtual degradation on the chip solder in the bration error is observed which increases with calibration
geometry depicted in Figure 2 the on-state under dif- load and mean temperature. Similarly, the effect of non-
ferent power loss conditions is obtained. By subtracting homogeneous temperature fields provides a clear error in
the values from the example without solder degradation on-state voltage compared to calibration conditions, see
the voltage increase due to increase of thermal resistance Figure 4. This indicate the necessity to expand the tem-
is obtained. It is seen that depending on load current and perature estimation function to include corrections ob-
mean temperature the can increase above be- tained either through simulations, as suggested presently,
fore reaching the failure criteria of increase of . or by a more detailed calibration procedure.
In contrast to metallization reconstruction and wire lift-off Degradation monitoring is intended as an approach to
the solder degradation is expected to continuously de- avoid early catastrophic events but also to provide early
grade and cause gradual increase in . This is expected estimations of device lifetime through extrapolation. The
because of the compliant nature of the solder layer and the former rely on well-defined failure criteria and the latter
degradation process being more visco-plastic and there- on a good extrapolation model. Both are closely connect-
fore time-dependent [17]. ed to the failure mode. This require significant amount of
However, if one compares the change in observed knowledge on the effect on the on-state voltage from dif-
in a standard DC pulse test, see Figure 1, to the contribu- ferent degradation mechanism to interpret the pattern.

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CIPS 2016 - 9th International Conference on Integrated Power Electronics Systems

These are sought simulated by inducing normally experi- physical model for lifetime estimation of power
enced device degradation in the power module intercon- modules," in Power Electronics Conference (IPEC),
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