1338164557.9062Ch08 Field-Effect Transistors (FETs) (37 PP)

Basic Electronic Devices and Circuits
EE 111
Electrical Engineering
Majmaah University
2nd Semester 1432/1433 H
Chapter 8
Field-Effect Transistors (FETs)
2012 Pearson Education. Upper Saddle River, NJ, 07458.

Electronic Devices, 9th edition
Thomas L. Floyd All rights reserved. 1
Introduction
BJTs (bipolar junction transistors) were covered in previous
chapters.
Now we will discuss the second major type of transistor, the FET
(field-effect transistor).
FETs are unipolar devices because, unlike BJTs that use both
electron and hole current, they operate only with one type of charge
carrier.
The two main types of FETs are

junction field-effect transistor (JFET)
metal oxide semiconductor field-effect transistor (MOSFET).
The term field-effect relates to the depletion region formed in the
channel of a FET as a result of a voltage applied on one of its
terminals (gate).
Recall that a BJT is a current-controlled device; that is, the base
current (IB) controls the amount of collector current (IC).
A FET is a voltage-controlled device, where the voltage between

two of the terminals (gate and source) controls the current through
the device.
A major advantage of FETs is their very high input resistance.
Because of their nonlinear characteristics, they are generally not as

widely used in amplifiers as BJTs except where very high input
impedances are required.
However, FETs are the preferred devices in low-voltage switching

applications because they are generally faster than BJTs when turned
on and off.

The FET
The idea for a field-effect transistor (FET) was first

proposed by Lilienfeld, a physicist and inventor.
In 1930 he was granted a U.S. patent for the device.
His ideas were later refined and

developed into the FET.
Materials were not available at the
time to build his device.
A practical FET was not
constructed until the 1950s.
Today FETs are the most widely
used components in integrated
circuits.
The JFET
The JFET (junction field-effect transistor) is a type of FET

that operates with a reverse-biased pn junction to control
current in a channel.
Depending on their structure, JFETs fall into either of two

categories:
n-channel
p-channel

Basic Structure

Basic Operation
VDD provides a drain-to-source voltage

and supplies current from drain to
source.
VGG sets the reverse-bias voltage

between the gate and the source.
The JFET is always operated with the

gate-source pn junction reverse-biased.
Reverse-biasing of the gate-source junction with a negative gate voltage

produces a depletion region along the pn junction, which extends into the n-
channel and thus increases its resistance by restricting the channel width.
Rchannel = L / A = L / A
The channel width and thus the channel resistance can be controlled by
varying the gate voltage, thereby controlling the amount of drain current, ID.
The JFET
The JFET (or Junction Field Effect Transistor) is a normally ON device.
For the n-channel device illustrated, when the drain is positive with
respect to the source and there is no gate-source voltage (VGS=0), there is
current in the channel. (normally ON means ON even when VGS=0)
When a negative gate voltage is applied to the FET, the electric field
causes the channel to narrow, which in turn causes current to decrease.
The white areas represent the
RD
depletion region created by the
reverse bias. D
The depletion region is wider toward n
the drain end of the channel because G
p p
+
VDD
the reverse-bias voltage between the
n
gate and the drain (VGG +VDDID RD) VGG
+ S
is greater than that between the gate
and the source (VGG).
JFET Symbols
Notice that the arrow on the gate points in for n-channel and out for p-
channel.

The JFET
As in the base of bipolar transistors (BJTs), there are two types

of JFETs: n-channel and p-channel.
The symbol for an n-channel JFET is shown,
along with the proper polarities of the applied
dc voltages.
RD
The dc voltage polarities are opposite for p-
channel. Drain
+
Gate VDD

For an n-channel device, the gate is always Source
VGG
operated with a negative (or zero) voltage +
with respect to the source (VGS 0), in order

to maintain the required reverse-bias
condition.
81 The JFET
Summary
Field-effect transistors are unipolar devices (one-charge
carrier).
The three FET terminals are source, drain, and gate.
The JFET operates with a reverse-biased pn junction (gate-

to-source).
The high input resistance of a JFET is due to the reverse-

biased gate-source junction.
Reverse bias of a JFET produces a depletion region within

the channel, thus increasing channel resistance.
JFET Characteristics and Parameters
There are three regions in the
characteristic curve for a JFET as
shown for the case when VGS = 0V.
Between A and B is the Ohmic ID
region, where current and voltage Ohmic region

are related by Ohms law. B VGS = 0 C
IDSS
From B to C is the active region
(or constant-current) where
current is essentially independent
of VDS.
Beyond C is the breakdown Active region
(constant current)
Breakdown
A
region. Operation here can 0 VP (pinch-off voltage)
VDS
damage the FET.

Consider the case when the gate-to-source voltage is zero (VGS=0V).
This is produced by shorting the gate to the source, where both are
grounded.
Consider the curve between points A and B:
As VDD (and thus VDS) is increased from 0V, ID will increase
proportionally.
In this area, the channel resistance is essentially constant because the
depletion region is not large enough to have significant effect.
This is called the ohmic region because VDS and ID are related by
Ohms law.
Consider point B on the curve:
The curve levels off and enters the active region where ID becomes
essentially constant.
Consider the curve between points B and C:
As VDS increases from point B to point C, the reverse-bias voltage
from gate to drain (VGD) produces a depletion region large enough to
offset the increase in VDS, thus keeping ID relatively constant.
Pinch-Off Voltage
For VGS=0V, the value of VDS at which ID becomes essentially
constant (point B on the curve) is the pinch-off voltage, VP.
For a given JFET, VP has a fixed value.
A continued increase in VDS above the pinch-off voltage produces
an almost constant ID.
This value of drain current is IDSS (Drain to Source current with gate
Shorted).
IDSS is the maximum drain current that a specific JFET can produce
regardless of the external circuit, and it is always specified for the
condition VGS=0V.
Breakdown
Consider point C on the curve:
Breakdown occurs when ID begins to increase very rapidly with any
further increase in VDS.
Breakdown can result in irreversible damage to the device.
Quiz
Q. If an n-channel JFET has a positive drain voltage and

the gate-source voltage is zero, the drain current will be
a. zero
b. IDSS
c. IGSS
d. none of the above

JFET Characteristics and Parameters
When VGS is set to different values, the
relationship between VDS and ID
develops a family of characteristic
curves for the device.
ID
An n-channel
IDSS VGS = 0
characteristic is
illustrated here.
Notice that VP is VGS = 1 V
positive and has

VGS = 2 V
the same
magnitude as VGS = 3 V
VGS(off). VGS = 4 V
VGS = VGS(off) = 5 V
VDS
VP = VGS(off) VP = +5 V

VGS Controls ID
As VGS is set to increasingly more

negative values by adjusting VGG, a
family of drain characteristic curves is
produced.
ID decreases as the magnitude

of VGS is increased to larger negative
values because of the narrowing of the
channel.
For each increase in VGS, the JFET reaches pinch-off (where constant
current begins) at values of VDS < VP.
Therefore, the amount of drain current ID is controlled by VGS.
The term pinch-off is not the same as pinch-off voltage, VP (at VGS=0)
Cutoff Voltage
The value of VGS that makes ID0 is the

cutoff voltage, VGS(off).
The JFET must be operated between
VGS=0 and VGS(off).
For this range of gate-to-source voltages (VGS), ID will
vary from a maximum of IDSS to a minimum of almost
zero.
For an n-channel JFET, the more negative VGS is, the D
smaller ID becomes in the active region.
When VGS has a sufficiently large negative value
(=VGS(off)), ID is reduced to zero.
G
This cutoff effect is caused by the widening of the
depletion region to a point where it completely closes
the channel.
S
Quiz
Q. A set of characteristic curves for a JFET are shown. The

blue lines represent different values of
a. VDS ID
b. VGS
c. VS
d. Vth
VDS

p-channel JFET
The basic operation of a p-channel JFET is the same as for

an n-channel device,
except that a p-channel JFET requires a negative VDS
and a positive VGS.
D
G
+ +
S

Comparison of Pinch-Off Voltage and Cutoff Voltage
As you have seen, there is a difference between pinch-off

and cutoff voltages.
There is also a connection.
The pinch-off voltage VP is the value of VDS at

which ID becomes constant and equal to IDSS
and is always measured at VGS=0V.
However, pinch-off occurs for VDS < VP when

VGS 0.
So, although VP is a constant, the minimum value of VDS at which ID becomes

constant varies with VGS.
VGS(off) and VP are always equal in magnitude but opposite in sign.

VP = VGS(off)
For example, if VGS(off) = 5V then VP = +5 V.

Quiz
Q. For a JFET, two voltages with the same magnitude but

opposite signs are
a. VD and Vp
b. VD and VS
c. VGS(th) and Vcutoff
d. Vp and VGS(off)

ID
D
G +
S

The p-channel JFET requires a positive gate-to-source voltage (VGS).
The more positive the voltage, the less the drain current (ID).
When VGS = 4 V, ID = 0.
Any further increase in VGS keeps the JFET cut off, so ID remains 0.
VP = VGS(off) = 4 V

+ +


The MOSFET
The MOSFET (metal oxide semiconductor field-effect

transistor) is another category of field-effect transistors (FETs).
The MOSFET, different from the JFET, has no pn junction

structure;
instead, the gate of the MOSFET is insulated from the channel
by a silicon dioxide (SiO2) layer.
The two basic types of MOSFETs are enhancement (E) and

depletion (D).
Of the two types, the enhancement MOSFET is more widely

used.
The MOSFET
The metal oxide semiconductor FET uses an insulated gate
to isolate the gate from the channel.
Two types are the enhancement mode (E-MOSFET) and the
depletion mode (D-MOSFET).
The E-MOSFET
An E-MOSFET has no channel E-MOSFET RD
Drain
until it is induced by a voltage ID
applied to the gate, so it SiO2

Induced
n channel n
operates only in enhancement
+
mode. Gate p substrate
+ +
VDD
+
An n-channel type is illustrated +
n + n
here; a positive gate voltage VGG

induces the channel.
Source

The E-MOSFET
The E-MOSFET operates only in the enhancement
mode and has no depletion mode.
It differs in construction from the D-MOSFET in that
it has no structural channel.
The substrate extends completely to the SiO2 layer.
For an n-channel device, a positive
gate voltage above a threshold value
induces a channel by creating a thin
layer of negative charges in the
substrate region adjacent to the SiO2 layer.
The conductivity of the channel is enhanced by
increasing the gate-to-source voltage and thus
pulling more electrons into the channel area.
For any gate voltage below the threshold value,
there is no channel.
E-MOSFET Symbols
The broken lines symbolize the absence of a physical channel.
An inward-pointing substrate arrow is for n channel,

and an outward-pointing arrow is for p channel.

The D-MOSFET
The drain and source are diffused into the substrate material and then
connected by a narrow channel adjacent to the insulated gate.
Since the gate is insulated from the channel, either a positive or a

negative gate voltage can be applied. (no pn junction in MOSFET)
The D-MOSFET
The D-MOSFET has a channel that can be controlled by the
gate voltage.
For an n-channel type,
a negative voltage and a positive voltage
depletes the channel; enhances the channel.
RD
D-MOSFET RD
D-MOSFET can
operate in either n n
depletion (D) mode

+
+
+
+

+ +
or enhancement (E)

+
+
p

VDD
+
+

p

VDD
+ +
mode, depending on
+
+
+
the gate voltage. VGG

+
n VGG

n
operating in D-mode operating in E-mode

Operation of n-channel D-MOSFET
Depletion Mode
Visualize the gate as one plate of a

parallel-plate capacitor
and the channel as the other plate.
The silicon dioxide (SiO2) insulating
layer is the dielectric.
With a negative gate voltage, the negative charges on the gate repel
conduction electrons from the channel,
leaving positive ions in their place.
Thereby, the n channel is depleted of some of its electrons, thus
decreasing the channel conductivity.
The greater the negative voltage on the gate, the greater the depletion of
n-channel electrons.
Depletion Mode (continued)
At a sufficiently negative gate-to-source voltage, VGS(off), the channel is

totally depleted and ID = 0.
Like the n-channel JFET, the n-channel D-MOSFET conducts drain

current for gate-to-source voltages between VGS(off) and zero.
In addition, the D-MOSFET conducts for values of VGS > 0. (next slide)
Enhancement Mode
With a positive gate voltage, more conduction electrons are attracted

into the channel,
thus increasing (enhancing) the channel conductivity.

D-MOSFET Symbols

MOSFET Symbols (Summary)
Notice the broken line (- - -) representing the E-MOSFET

that has an induced channel.
The n-channel has an inward pointing arrow.
E-MOSFETs D-MOSFETs
D D D D
G G G G
S S S S
n-channel p-channel n-channel p-channel

Quiz
outward arrow broken line
Q. The symbol for a p-channel E-MOSFET is
D D D D
G G G G
S S S S
a. b. c. d.
X X X
n-channel D-MOSFET D-MOSFET


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Basic Electronic Devices and Circuits

Field-Effect Transistors (FETs)

2012 Pearson Education. Upper Saddle River, NJ, 07458.

The two main types of FETs are

A FET is a voltage-controlled device, where the voltage between

A major advantage of FETs is their very high input resistance.

Because of their nonlinear characteristics, they are generally not as

However, FETs are the preferred devices in low-voltage switching

2012 Pearson Education. Upper Saddle River, NJ, 07458.

The idea for a field-effect transistor (FET) was first

His ideas were later refined and

The JFET (junction field-effect transistor) is a type of FET

Depending on their structure, JFETs fall into either of two

2012 Pearson Education. Upper Saddle River, NJ, 07458.

2012 Pearson Education. Upper Saddle River, NJ, 07458.

VDD provides a drain-to-source voltage

VGG sets the reverse-bias voltage

The JFET is always operated with the

Reverse-biasing of the gate-source junction with a negative gate voltage

2012 Pearson Education. Upper Saddle River, NJ, 07458.

As in the base of bipolar transistors (BJTs), there are two types

with respect to the source (VGS 0), in order

The three FET terminals are source, drain, and gate.

The JFET operates with a reverse-biased pn junction (gate-

The high input resistance of a JFET is due to the reverse-

Reverse bias of a JFET produces a depletion region within

Between A and B is the Ohmic ID

region, where current and voltage Ohmic region

damage the FET.

Q. If an n-channel JFET has a positive drain voltage and

2012 Pearson Education. Upper Saddle River, NJ, 07458.

positive and has

2012 Pearson Education. Upper Saddle River, NJ, 07458.

As VGS is set to increasingly more

ID decreases as the magnitude

Therefore, the amount of drain current ID is controlled by VGS.

The value of VGS that makes ID0 is the

Q. A set of characteristic curves for a JFET are shown. The

2012 Pearson Education. Upper Saddle River, NJ, 07458.

The basic operation of a p-channel JFET is the same as for

2012 Pearson Education. Upper Saddle River, NJ, 07458.

As you have seen, there is a difference between pinch-off

The pinch-off voltage VP is the value of VDS at

However, pinch-off occurs for VDS < VP when

So, although VP is a constant, the minimum value of VDS at which ID becomes

VGS(off) and VP are always equal in magnitude but opposite in sign.

2012 Pearson Education. Upper Saddle River, NJ, 07458.

Q. For a JFET, two voltages with the same magnitude but

2012 Pearson Education. Upper Saddle River, NJ, 07458.

2012 Pearson Education. Upper Saddle River, NJ, 07458.

2012 Pearson Education. Upper Saddle River, NJ, 07458.

The MOSFET (metal oxide semiconductor field-effect

The MOSFET, different from the JFET, has no pn junction

The two basic types of MOSFETs are enhancement (E) and

Of the two types, the enhancement MOSFET is more widely

applied to the gate, so it SiO2

2012 Pearson Education. Upper Saddle River, NJ, 07458.

The broken lines symbolize the absence of a physical channel.

An inward-pointing substrate arrow is for n channel,

2012 Pearson Education. Upper Saddle River, NJ, 07458.

Since the gate is insulated from the channel, either a positive or a

the gate voltage. VGG

operating in D-mode operating in E-mode