42 views

Uploaded by Hilberto Filho

- The Art of Instrumentation
- _81838a6a20f8aca444_midroot_aid_35296e4735c74a9a963c85a5cb842779_tid_uid_100002000996664_accid_100002000996664_ext_1400750364_hash_AQBVx65zO1H93Ui3iIFBiYCDMcR
- datasheead6652t[1]
- 596b4
- 1-Semi Conductor - Ijsst - High Performance - Narendra Bahadur Singh
- Project Content Prince
- Appnote 49- Interfacing PD243x Alphanum. Programmable Display w. SAB 80515SAB 80535 Microcontroller
- 51790954 Green House Environment Control
- Bz 36459463
- MAX186-MAX188
- RPiMRE
- CHECK_E_BAE.pdf
- Tektronics - Oscilloscope Pocket Guide
- Automatic Street Light Control System
- FT8 Operating Tips
- Proj08 ECG Notes
- [Article] Analog Circuits Benefit Form Scaling Trends
- Labwork1
- FX Analog Datasheet
- Orca MIT

You are on page 1of 11

1, JANUARY 2011 9

Rectifier Controller

Barry A. Mather, Student Member, IEEE, and Dragan Maksimovic, Senior Member, IEEE

AbstractThis paper introduces a single-phase digital power- was introduced in [6]. In the NLC approach, the input voltage vg

factor correction (PFC) control approach that requires no input in the PFC-current-control objective is expressed in terms of the

voltage sensing or explicit current-loop compensation, yet results output voltage Vo and the switch duty cycle d, thus, eliminating

in low-harmonic operation over a universal input voltage range

and loads ranging from high-power operation in continuous con- the need to sense the input voltage. Furthermore, Maksimovic

duction mode down to the near-zero load. The controller is based et al. [6] showed that the resulting reformulated control objec-

on low-resolution A/D converters and digital pulsewidth modu- tive can be realized by relatively simple analog circuitry using

lator, requires no microcontroller or DSP programming, and is a modulator where a periodic carrier waveform is obtained by

well suited for a simple, low-cost integrated-circuit realization, or replacing d with t/Ts in the control objective, where Ts is the

as a hardware description language core suitable for integration

with other power control and power management functions. Ex- switching period. As a result, this approach further eliminated

perimental verification results are shown for a 300-W boost PFC the need for current-loop compensation, and the need for a

rectifier. precision analog multiplier. In the cases considered in [6], non-

Index TermsDigital control, low-harmonic rectifier, power- linear carrier waveforms were employed, which is why the NLC

factor correction (PFC) rectifier, preregulator. term was used to name the approach. Various modifications and

extensions of this approach, including implementations based

on linear carrier waveforms [7][10], and with applications to

I. INTRODUCTION other converters [8], [9], [11] have been reported. Furthermore,

related approaches are now used in commercially available PFC

INGLE-PHASE power-factor correction (PFC) boost rec-

S tifiers are used in a wide range of applications that are

required to meet the EN 61000-3-2 standard [1]. Furthermore,

controllers [12][14].

Digital PFC controllers, offering improved system interface,

power management features, support for multimodule opera-

certification programs, such as 80 Plus [2], specify new power

tion, and improved voltage-loop dynamic responses, have re-

factor minimums at operating powers less than full-rated power.

cently received increased attention. Most of the digital PFC-

At low-to-medium power levels, transition-mode control (i.e.

control techniques reported so far have been based on DSP or mi-

critical conduction mode, or operation at the boundary of con-

crocontroller implementations (see, e.g., [15][23]), or have re-

tinuous conduction mode (CCM) and discontinuous conduction

lied on multiple current samples per switching period [24], [25].

mode (DCM)), which offers simplicity and performance advan-

Hybrid PFC controllers, featuring an analog current loop and a

tages, is widely used and supported by a range of commercially

digital voltage loop, have also been presented with the aim of

available low-cost controllers [3], [4]. At higher power levels

providing high quality current shaping and flexible voltage loop

(above several hundred watts), CCM operation is often preferred

designs in a single controller [26][30].

because of lower conduction losses and reduced electromag-

Based on the approach presented in [6], the purpose of this

netic interference (EMI) filtering requirements. Averaged cur-

paper is to introduce a digital PFC-control approach, called the

rent mode control in combination with a slow voltage control

digital NLC (DNLC)-PFC controller, using a simple current-

loop and a multiplier, which is a well-known control approach

control law that allows operation in CCM without input-voltage

for CCM PFC [5], requires a more complex implementation

sensing. Further objectives are to show how low-harmonic op-

compared to the transition-mode control.

eration over a universal input voltage range and a wide range

With the motivation of simplicity comparable to transition-

in power can be achieved using low-resolution A/D convert-

mode or DCM operation, together with low-harmonic, low-

ers, a low-resolution digital pulsewidth modulator (DPWM)

conduction loss, and low-EMI performance in CCM, a nonlin-

and minimal digital hardware. Fig. 1 shows a block dia-

ear carrier (NLC)-control technique for CCM boost converters

gram of a PFC-boost rectifier with the proposed DNLC-PFC

controller.

The paper is organized as follows. Section II introduces the

Manuscript received January 6, 2010; revised April 13, 2010; accepted May DNLC-PFC current-control law. Section III describes the volt-

9, 2010. Date of current version December 27, 2010. This paper was presented age regulation loop and addresses modeling of the outer voltage

in part at the IEEE Applied Power Electronics Conference, Anaheim, CA,

February 25 to March 1, 2007. Recommended for publication by Associate loop gain when a DNLC-PFC controller is utilized. Section IV

Editor P. Mattavelli. discusses system implementation and quantization issues.

The authors are with the Colorado Power Electronics Center, Department of Experimental results for a 300-W boost DNLC-PFC-controlled

Electrical, Computer and Energy Engineering, University of Colorado, Boulder,

CO 80309 USA (e-mail: matherb@colorado.edu; maksimov@colorado.edu). rectifier are presented in Section V. Section VI concludes the

Digital Object Identifier 10.1109/TPEL.2010.2051458 paper.

10 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011

As shown in Fig. 1, in a PFC rectifier the current-control ob- Fig. 2. Experimental waveforms illustrating the operation of the boost PFC

jective can be written as iL = vg /Re , where vg is the rectified with DNLC-PFC current-control law (3).

line voltage, iL is the low-frequency (average) component of

the inductor current, and Re is the emulated input resistance,

Re = Vg2,rm s /P , where P is the operating power of the PFC ON-time or OFF-time (as in [33] and [34]). The timing of these

rectifier stage [31, p. 661]. Using the quasi-static approxima- signals is facilitated by the use of a triangle-wave DPWM. The

tion, assuming vg is changing slowly compared to the switching current sample instance used to update the duty-cycle command

period Ts , for the CCM boost converter Vo (1 d) = vg , where d[n] by computing (3) is determined by the previous value of

d is the switch duty ratio, the current-control objective can be the duty cycle command, d[n 1]. If d[n 1] > 0.5 the ON-

expressed as time sample instance is used, otherwise the OFF-time sample

instance is used. The implementation of this simple sample

Vo Vo P 1

iL = (1 d) = 2 (1 d) = (1 d) (1) mode logic function effectively maximizes the allowable con-

Re Vg ,rm s u version time of the inductor current sensing A/D. The minimum

where required sampling rate of the inductor current sensing A/D is

4fs . During operation in either sample mode (ON-time or

Vg2,rm s Re

u= = (2) OFF-time sampling), the duty-cycle command d[n] is updated

Vo P Vo immediately after either the respective ON-time or OFF-time

takes the role of a power-control signal. In [6], the steps leading (EOC) occurs.

to (1) were followed by a discussion of analog modulator realiza-

tions aimed at implementing the PFC-current-control objectives A. Stability of the Current Control Loop

reformulated in terms of Vo and d, respectively. In this paper,

a different approach, better suited for digital implementation The small-signal stability of the current control law (3) is

follows by solving (1) for the duty-cycle command d[n] directly examined in this section starting from a discrete-time model

as a function of the current sample iL [n] = iL , where iL [n] based on both the quasi-static approximation, assuming that the

represents a sample of the inductor current ideally in the middle input voltage, vg , can be considered to be constant on the time

of the switch ON-time, or in the middle of switch OFF-time, scale of several switching periods, and the approximation that

and u is the power-control signal the output voltage Vo is constant and not time varying. From the

large-signal relationship [34]

d[n] = 1 uiL [n]. (3)

vg Vo

Equation (3) is the basic version of the proposed DNLC current- iL [n + 1] = iL [n] + Ts (1 d[n])Ts (4)

control law. Note that (3) requires no input-voltage sensing or L L

explicit compensation of the current-control loop. As shown in a small-signal discrete-time relation yields the control-to-

Fig. 1, the DNLC controller presented in this paper requires only current transfer function

current sensing and sensing of the output voltage. It is of interest

to note that an alternative direction in pursuing simplified digital iL (z) Vo Ts

Gid (z) = = . (5)

PFC control is taken in [32], where the input and the output

d(z) L z1

voltage are measured using very simple A/D converters, while a

current estimator removes the need for current A/D conversion. Linearization of (3) gives the effective current-loop compensator

Fig. 2 shows experimental waveforms illustrating operation transfer function

of a DNLC controller based on (3). The current A/D conversion

start (CON V ST ) and end of conversion (EOC) signals show

d(z)

Gic (z) = = u. (6)

how the inductor current is sampled in the middle of the switch iL (z)

SIMPLE DIGITAL POWER-FACTOR CORRECTION RECTIFIER CONTROLLER

MATHER AND MAKSIMOVIC: 11

TABLE I

CURRENT FILTER COEFFICIENTS FOR EXTENDING THE K c rit STABILITY

RANGE OF THE DNLC-PFC CONTROLLER

of the DNLC-PFC controller. (a) Root-locus plot of T i (z) for the basic DNLC-

control law given in (3). (b) Root-locus plot of T i (z) for the DNLC-control law an evolutionary algorithm [35] was employed to determine the

with a two sample current filter 1 = 0.75 and 2 = 0.25, respectively.

optimal filter coefficients.

As Table I shows, all filter coefficients sum to one as to

Combining (2), (5), and (6), the effective discrete-time current- not change the current sensing dc gain. Also, all coefficients

control-loop gain is obtained are monotonically decreasing with higher order. The maximum

stable Kcrit is increased by 1 for every added order of the cur-

R e Ts 1 1

Ti (z) = Gid (z)Gic (z) = = 2Kcrit (7) rent filter. The root-locus plot for the current filter with two

L z1 z1 current samples is shown in Fig. 3(b). The plot indicates that

where Kcrit = Re Ts /2L is a parameter that determines the op- the current loop is stable for Kcrit < 2. This effectively ex-

erating mode (CCM or DCM) of the boost converter in the PFC tends the range of stable CCM operation from Kcrit < 1 to

rectifier [31, p. 643]. Based on (7), the stability of the current- Kcrit < 2 compared to the basic DNLC-PFC-control law given

control loop can be examined using root-locus techniques with in (3). The filter coefficients for the two sample current filter

Kcrit as a gain parameter, as shown in Fig. 3(a). The root-locus are also easily implemented in a digital system without the need

given shows that the current loop is stable (i.e., has a pole inside for additional hardware multipliers as the filter coefficients can

the unit circle) as long as Kcrit < 1, which is the same condi- be implemented by simple bit shifts and additions. Due to the

tion that characterizes the boost PFC rectifier operating in CCM ease of implementation and increased CCM-stability range, the

over the entire line cycle [31, p. 643]. In conclusion, the current DNLC-PFC-control law with an implemented two sample cur-

loop based on (3) is small-signal stable at high power levels rent filter was selected for implementation in the experimental

when the converter always operates in CCM during the entire prototype.

line cycle. At reduced power levels, the boost converter operates

in DCM around the zero crossings of the ac line, and in CCM B. Operation and Stability at Light Loads

around the peak of the ac line. Instability of the current loop During light-load operation, the converter will operate in

during a CCM-operation section of a mixed-mode (DCM and DCM during some portion or all of the input-voltage-line cycle

CCM) line period typically manifests itself as current period- and the power command signal u will be limited to its maximum

doubling. This type of bounded oscillatory behavior results in stability limit um ax , found as

increased line current total harmonic distortion (THD), which

2Kcrit L

may be tolerated. It is nevertheless of the interest to investigate um ax = (9)

modifications of the current-control law to achieve stable oper- Vo Ts

ation in CCM at lighter loads, i.e., for larger values of Kcrit . where Kcrit is determined based on the stability criterion dis-

In particular, the addition of control-law dynamics through the cussed in Section II-A. To maintain voltage regulation in light

inclusion of a current filter prior to the calculation of the duty load conditions when the traditional power command signal has

cycle via (3) is considered. In these cases iL [n] in (3) is replaced reached the stability boundary u = um ax , a further modification

by a filtered current, iL ,ltered [n] that is calculated by is made to the basic DNLC current-control law (3)

resents the maximum allowable duty cycle during any given

where 1 , 2 , . . . , k are the implemented filter coefficients. half-line period. This modification effectively implements the

The filter coefficients (s) that provide the highest CCM stable basic DNLC current-control law given in (3) with a duty-

Kcrit in closed loop for a given filter order are given in Table I. cycle command offset equal to (1 dm ax ) that is adjusted to

The coefficients for the current filters comprised of only two or maintain output voltage regulation. During higher power oper-

three current samples that were found by visual inspection of the ation, when u < um ax , dm ax is equal to 1, thus reducing the

closed-loop root-locus plots, generated numerically, followed by control law given in (10) back to (3). This modification makes

small adjustments to filter coefficients. For higher order filters, voltage regulation possible down to essentially zero load even

12 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011

creased input current distortion at light loads.

A block diagram of a boost rectifier with the complete DNLC-

PFC controller is shown in Fig. 4. Based on the sampled output

voltage error, the voltage-loop compensator Gcv (z) computes Fig. 5. Averaged small signal model of the DNLC-controlled boost PFC output

port.

the power-control signal y[k]. During operation at high power

levels and lower line voltages, u[n] = y[k]. However, as the op-

erating power level is reduced, u[n] is limited to a value of um ax in Fig. 4 as the Line Sync. block. Line synchronization could

as described in the previous section. The power command signal, also be provided by the output voltage loop itself through the

y[k], then continues to increase initiating a reduction of dm ax [k] use of the single comparator A/D approach [37].

via the dm ax control loop. The discrete time sample instances

in the voltage loop are denoted using the letter k as opposed to A. Power Control via u[n]

the letter n to denote a difference in sample frequency. As the Fig. 5 shows a continuous time low-frequency small-signal

bandwidth of the outer voltage loop must be low, at least during model of the PFC output stage obtained by averaging over a half

steady-state operation, it is advantageous to sample the output line cycle [31, p. 669] for the DNLC-PFC current-control law

voltage at a rate synchronous to 2fline . Benefits of sampling at described in Section II when the boost PFC stage operates in

this rate include the fact that input current harmonic distortion CCM during the entire line period. Small-signal perturbations

is unaffected by the output voltage ripple and that voltage loop of the power command signal, PFC output port current, and

limit cycling can be avoided as described in [36]. Furthermore, rectifier output voltage are denoted by u, i2 , and v, respectively.

a satisfactory outer voltage loop PI compensator can be real- This model is valid for frequencies below 2fline and assumes a

ized using less hardware compared to a similar performance PI constant operating point. During CCM always operation u[n] =

compensator designed with a sample rate of fs due to short- y[k] (as u[n] < um ax ) and u[n] and the emulated input resistance

ened register lengths required to implement the compensator. (Re ) are related by (2). Under these operating conditions, the

The requirement for synchronization to the ac line is provided small-signal model parameters are

by generating a clock derived from a digital comparison of ei-

ther the sensed inductor current or duty-cycle command with a P2

j2 = (11)

constant. The generation of the voltage-loop clock vclk is shown Vg2,rm s

SIMPLE DIGITAL POWER-FACTOR CORRECTION RECTIFIER CONTROLLER

MATHER AND MAKSIMOVIC: 13

Fig. 6. Comparison of experimental and simulated inductor current waveforms in DCM always operation, P = 30 W, V g , rm s = 120 V, 60 Hz. (a) Inductor

current waveform collected using the DNLC-PFC controller. (b) Inductor current waveforms computed using the DNLC-PFC simulator and the constant duty-cycle

controller simulator.

and mixed mode and DCM always in operation. Under these oper-

Vo2 ating conditions, the PFC rectifier inductor current is distorted

r2 = (12) from the ideal rectified sine waveform due to several factors:

2P

implementation of a CCM-derived control law as shown in (3),

where P is the average operating power of the PFC rectifier

a duty-cycle command offset applied to this law in order to

stage. The input voltage gain g2 is omitted from calculation

maintain output voltage regulation as shown in (10), and in-

because vg ,rm s = 0 when computing the small-signal control-

accurate sensing of the average inductor current during DCM

to-output gain u to v. Assuming a resistive load of value R =

operation. In DCM, the average inductor current is either over-

Vo2 /P , solving the model results in the control-to-output transfer

estimated during ON-time sampling or underestimated during

function for the DNLC PFC-controlled boost rectifier

OFF-time sampling. The expected input current distortion due

v(s) P Vo2 Rs 1 to these factors indicates that the emulated input resistance Re

Gv u (s) = =

u(s) 3Vg2,rm s 1 + sCR/3 of the PFC rectifier is not constant over a half-line cycle period,

which precludes the use of the averaged small-signal model

1

= Gv y 0 . (13) output port model shown in Fig. 5 and assumes a constant Re

1 + s/p over a half-line cycle period. As there is no closed-form analyt-

This single pole plant transfer function is easily compensated ical link between y[k] and Re for the implemented controller,

with a linear PI compensator, Gcv (z) in Fig. 4, in order to a numerical simulator was used to calculate the expected aver-

achieve a standard slow voltage loop-control bandwidth of age power processed during each half-line cycle period given

10 Hz and a phase margin of 70 under the highest expected the implemented control law (10) and the outer voltage-loop-

dc-loop-gain conditions. Load transient responses for a DNLC- control topology shown in Fig. 4. Additionally, inspection of

controlled PFC rectifier with similar power stage parameters to (10) shows that the implemented controller law becomes equiv-

those given in Table II and a nearly identical digital voltage loop alent to a constant duty-cycle controller as the sensed inductor

implementation to the one described here are shown in [37]. current decreases (iL [n] 0). In this case, the analytical model

developed in [38] applies, and provides a guide for an initial

B. Power Control via dm ax [k] selection of the gain parameter Kd . However, in the absence of

a comprehensive analytical model, numerical simulations were

During rectifier operation at lower power levels and/or higher

necessary to evaluate operation in mixed CCM/DCM and DCM

input voltages, the stage operates in DCM during some or all of

only modes.

the input voltage line cycle. During this type of operation u[n]

Fig. 6(a) and (b), respectively, shows an experimental inductor

is saturated at um ax and the power is controlled via the dm ax

current waveform collected at an operating power of 30 W and

control loop defined by

an rms input voltage of 120 V, 60 Hz, and the corresponding sim-

dm ax [k] = 1 Kd (y[k] um ax ) (14) ulated average current waveforms produced by both the DNLC-

PFC simulator and the constant duty-cycle control simulator.

where Kd is a linear gain term that relates the unsaturated power

Disregarding the experimental inductor currents zero-crossing

command signal y[k], and the secondary power command signal

distortion, the experimental waveform shows characteristics of

dm ax [k]. In order to fully design the outer voltage loop by spec-

both simulated controller techniques. At low current levels, the

ifying Kd , it was of interest to investigate the expected dc gain

inductor current rises sharply as the duty-cycle command is

of the implemented DNLC-PFC controller during CCM/DCM

14 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011

Fig. 7. Control-to-output transfer function dc gains of the outer voltage loop for V g , rm s = 120 V, 60 Hz, and 230 V, 50 Hz, and dm a x control gain K d = 2.0,

basic DNLC-PFC control law given by (3), u m a x = 0.4. (a) V g , rm s = 120 V, 60 Hz, K d = 2.0. (b) V g , rm s = 230 V, 50 Hz, K d = 2.0.

current reduces the duty-cycle command via (10) and results in a

higher quality current waveshape than attainable with a constant

duty-cycle controller alone.

The simulators were further employed to determine the dc

control-to-output transfer function gain as a function of operat-

ing power level, rms input voltage and dm ax control gain Kd .

Fig. 7(a) and (b) shows the resulting dc-transfer function gains

for Vg ,rm s = 120 V, 60 Hz and 230 V, 50 Hz, respectively, and

Kd = 2.0. Fig. 7(a) and (b) also shows experimentally measured

dc control-to-output gains and two computed control-to-output

dc gains from analytical models. The first is the dc gain (Gv y 0 )

from (13). The second (labeled as const. d DCM model in

Fig. 7(a) and (b)) is from the analytical constant duty-cycle- Fig. 8. Outer voltage loop control-to-output dc-transfer function gain for

control model [38] that is valid during DCM always operation. V g , rm s = 120 V, 60 Hz, and dm a x control-loop gains of K d = 2.0 and 0.5.

In Fig. 7(a), the point at which u[n] saturates at um ax is

clearly visible at approximately 95 W. This transition from

u[n] control to dm ax [k] control does not occur exactly at gain curves when the dm ax loop is active. Furthermore, Fig. 8

the mixed mode CCM/DCM and CCM always boundary be- shows that the choice of Kd determines the low-power gain

cause of an implemented stability safety margin on um ax (see characteristics of the DNLC-PFC controller. For the prototype

Section IV-A). Prior to this transition, the simulated, mod- stage tested, a Kd of 2.0 gives an increasing control-to-output dc

eled, and measured control-to-output dc gains are all in close gain as the operating power level decreases below to about 95 W.

agreement. In the DCM always region, the simulated, modeled, However, the dc gain at 10 W (Pm in ) is approximately equal to

and measured gain are also closely matched verifying that the the gain expected in CCM always operation at a maximum

DNLC-PFC controller is approximately a constant duty-cycle output power of 300 W. If the 300-W DNLC-PFC prototype

controller at very low powers. At a higher line voltage, as in were required to meet the PFC no limit cycling criteria given

Fig. 7(b), the DNLC-PFC controller operates under dm ax [k] con- in [36], a Kd of 2.0 would generally provide a faster transient

trol over the entire power range. Again at low powers, the mea- response when operating under dm ax control compared to a Kd

sured dc gain closely matches the gain expected from a constant of 0.5 because the gain profile when Kd = 2.0 has less gain

duty-cycle controller [38]. These control-to-output dc gains are variation across the operating power spectrum and has nearly

specific to the prototype described. Different boost inductances the same maximum gain at upper and lower power limits.

and/or converter operating frequencies will result in different

control-to-output transfer function dc-gain characteristics by C. Modulation of u[n]

shifting the mode transition boundaries (CCMDCM/CCM

and DCM/CCMDCM) to higher or lower operating power In the interest of minimizing the amount of hardware re-

levels. quired to implement the DNLC-PFC controller, it is beneficial

The effect of changing the dm ax loop-design parameter Kd to reduce the word size for the power command u[n], as it

is shown in Fig. 8. The DNLC-PFC simulator, measured, and is directly multiplied with iL [n] or iL ,ltered [n] in the DNLC-

DCM constant duty-cycle controller gains are shown for Kd = PFC controller block. Reducing the word size of u[n] allows

2.0 and 0.5. It is clearly shown that Kd linearly scales the dc- for the use of a smaller digital multiplier and reduces the num-

ber of gates required to implement the DNLC-PFC control law.

SIMPLE DIGITAL POWER-FACTOR CORRECTION RECTIFIER CONTROLLER

MATHER AND MAKSIMOVIC: 15

TABLE II

PROTOTYPE DNLC-PFC PARAMETERS

Fig. 10. Current-loop gain magnitude and phase of the basic DNLC-control

law given in (3) and the two sample current filter DNLC-control law at steady-

state operating power levels corresponding to u m in and 0.8u m a x for a PFC

rectifier with power stage parameters given in Table II.

However, at certain power levels, the power differential between single current sample, and the controller with filtered current

a 1 LSB step in u[n] may become considerably large as shown using two samples with coefficients shown in Table I. Fig. 10

in Fig. 7(a) and (b). Given the large oversampling ratio of u[n] shows the loop gain magnitude and phase responses over a fre-

to y[k] (fs /2fline ), modulation can be very effective in im- quency range from 400 Hz to fs /2. Here, um in is the power

proving the effective resolution of the power command u[n], command signal value when operating at full power with an

with minimal hardware overhead. In the implemented DNLC- rms input voltage of 85 V. The worst-case (minimum) cross-

PFC controller, a simple, first-order modulator (u in over frequency, which is approximately equal to the closed loop

Fig. 4) in the error-feedback configuration [39, p. 531] shown bandwidth of the current control loop, occurs at um in , and is ap-

in Fig. 9 is used to effectively represent a 10-bit (nin ) u[n] using proximately 2.5 kHz (or approximately fs /25). Operation with

only an 8-bit (nout ) word size. a power command of 0.8um ax gives cross-over frequencies of

approximately 19 and 25 kHz (or approximately 2fs /5), for the

IV. SYSTEM IMPLEMENTATION basic and the two sample current filter versions of the DNLC-

PFC control law, respectively. Quality of the resulting current

The experimental prototype consists of a boost-rectifier power

waveshapes, presented in Sections IV-B and V provide further

stage and a digital controller implemented using a Xilinx FPGA

evidence that the bandwidth of the current-control loop can be

development platform with a clock rate of 66.66 MHz. The dig-

considered adequate for the PFC application.

ital controller allows experimentation with the bit resolutions

It should be noted that the discussion here is based on the

of the current sensing A/D (maximum inductor current reso-

simple discrete-time model of Section II-A, which assumes con-

lution: 30 mA) and voltage sensing A/D (maximum output

stant output voltage. For analog PFC controllers based on (1),

voltage resolution: 2 V) through the adjustment of the num-

a more comprehensive study of the current-loop bandwidth and

ber of bits truncated from the native A/D bit resolution. Both

interactions with the output filter capacitor dynamics and rip-

A/Ds are implemented using commercially available, relatively

ple has been presented in [40], where it was concluded that

low-cost 8-bits devices (Analog Devices AD7288) allowing a

effects of the output voltage ripple are relatively minor from the

maximum sample rate of 2 MHz. In a custom-IC implemen-

practical point of view, and that the bandwidth of the consid-

tation of the DNLC-PFC controller, a single multiplexed A/D

ered analog current-control loop should suffice in practical PFC

could be utilized. The DPWM resolution (maximum resolution:

applications.

9 bits) was also adjustable via a communications port interfaced

with the FPGA. Table II lists the power stage parameters for the

DNLC-controlled PFC prototype constructed. B. Quantization Issues

An objective was to meet EN 61000-3-2 Class D standards [1]

A. DNLC-PFC Current-Controller Bandwidth

with the simplest digital implementation possible to yield a

The effective closed-loop bandwidth of the DNLC-PFC con- cost-effective digital PFC controller and reduce the number of

trol law is examined by constructing the Bode plot of the DNLC- connections needed to interface the controller. The effects of

PFC loop gain given in (7) for two values of the steady state various resolutions of the DPWM and the current sensing A/D

power command signal, u = 0.8um ax and u = um in and for two were investigated to this aim.

16 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011

TABLE III

THD MEASUREMENTS FOR VARIOUS CURRENT A/D RESOLUTIONS,

9 BIT DPWM, P = 300 W

variable from 1 bit to 9 bits. During experimentation it was

determined that the 1 bit and 2 bit settings were simply not fea- Fig. 12. Harmonic current levels with and without d dithering imple-

mented, P = 300 W, V g , rm s = 120 V, 60 Hz, 3-bit DPWM, 4-bit current-

sible and produced extreme quantization effects. Implementing sensing A/D.

a first-order modulator (d in Fig. 4) to modulate the

duty-cycle command d[n] allows the DPWM resolution to be

lowered to as low as 3 bits while maintaining EN 61000-3-2 ized harmonic current magnitudes for the same conditions as

Class D current harmonic limit standards at a 300 W power shown in Fig. 11. Normalized harmonic current magnitudes are

level. A DPWM setting of 4 bits, with modulation of an shown for converter operation with and without modula-

additional 5 LSBs is a suitable setting for the operation of the tion of the duty-cycle command enabled. The EN 61000-3-2

boost PFC over the entire range of input voltages and output Class D odd harmonic current limits, scaled for low line voltage

power levels. Reducing the DPWM resolution from 9 bits to operation, are also shown. Without the d block active the

4 bit allows the digital logic clock rate of the DPWM mod- controller operating with a 3-bit DPWM is still capable of pass-

ule to be reduced from 66.66 to 2.08 MHz. With this DPWM ing the harmonic current limits although the amplitude of the

clock rate reduction, the clock rate for the overall controller can 15th harmonic is quite close to surpassing the harmonic current

also be significantly reduced depending on the digital clock rate limit standard. With the duty-cycle command modulator

required by the implemented A/Ds. enabled, with 6 LSBs of error feedback, the 3-bit DPWM easily

Fig. 11 shows line current waveforms with and without passes the harmonic current limits. Furthermore, Fig. 12 shows

modulation of the 4-bit duty-cycle command signal with a full- that the d block is capable of distributing low frequency

current sensing A/D resolution of 8 bits at P = 300 W and current harmonics to higher frequencies. For instance, the third

Vg ,rm s = 120 V, 60 Hz. Fig. 11(a) shows the line current wave- harmonic is reduced using the modulator; however, more

form when d is disabled. No low-frequency limit-cycling harmonic current is seen in the fifth harmonic current than with-

is present, due to a high-effective resolution of u[n] but the out modulation. The overall effect is a redistribution of

line current clearly shows a stair-step like appearance due to harmonic currents to higher harmonic orders.

the quantization of d[n]. With d enabled, Fig. 11(b) shows

a smooth iline (t) waveform that easily meets harmonic current V. EXPERIMENTAL WAVEFORMS

specifications.

2) Current Sensing A/D Resolution: The current sensing A. Operation at High and Moderate Power

A/D had a variable resolution of 3 bits to 8 bits. Table III Fig. 13 shows the experimental rectified line voltage, vg (t),

shows how the current sense resolution affects the THD of the and line current, iline (t), waveforms for nominal line voltages

line current. The increase in the THD at low-current A/D res- of 120 V, 60 Hz, and 230 V, 50 Hz, and operating power levels of

olutions is due to increased zero-crossing distortion due to a 300 W and 50 W. The implemented DPWM has a 4-bit resolution

larger zero current bin and a stair-step like current wave-shape and the current sensing A/D has a resolution of 8 bits. The

producing harmonics at many multiples of the fundamental. duty-cycle command is modulated with 5 LSBs in error

The DPWM resolution was set to a full 9 bits of resolution in feedback. The implemented complete DNLC-PFC controller

order to demonstrate the effects of the current sensing A/D res- requires roughly 3000 equivalent logic gates. At all operating

olution apart from other DPWM resolution effects. The current- points the line current shaping has the characteristics of high

sensing resolution in mA/bit is also presented in Table III. For the power factor and low THD particularly at full operating power,

3-bit current-sensing A/D the current LSB quantization step is P = 300 W, when the converter is in CCM operation for the

nearly 1 A. Nevertheless, at 300 W the EN 61000-3-2 Class D entire line cycle. The EN 61000-3-2 Class D harmonic current

harmonic current limits are not exceeded. limits are met for all specified operating conditions.

3) Combined Quantization Effects: The combined effects of Table IV shows the measured power factor (PF) of the DNLC-

current-sensing A/D resolution and DPWM resolution with and controlled PFC at 100%, 50%, and 20% load for line voltages

without modulation were investigated for a near minimal of 120 V, 60 Hz, and 230 V, 50 Hz. The specified power factor

hardware configuration. Fig. 12 is a plot of the power normal- minimums for the 80 Plus certification program is also listed.

SIMPLE DIGITAL POWER-FACTOR CORRECTION RECTIFIER CONTROLLER

MATHER AND MAKSIMOVIC: 17

Fig. 11. Converter waveforms with and without modulation of the duty-cycle command enabled, P = 300 W, V g , rm s = 120 V, 60 Hz, 4 bit DPWM, 8 bit

current sensing A/D. (a) d modulation disabled. (b) d modulation enabled, 5 LSBs in error feedback.

Fig. 13. Experimental DNLC-PFC waveforms, ilin e (t) and v g (t), for P = 300 W and 50 W, V g , rm s = 120 V, 60 Hz and 230 V, 50 Hz, 4-bit DPWM, 8-bit

current A/D. (a) V g , rm s = 120 V, 60 Hz, P = 300 W. (b) V g , rm s = 230 V, 50 Hz, P = 300 W. (c) V g , rm s = 120 V, 60 Hz, P = 50 W. (d) V g , rm s = 230 V,

50 Hz, P = 50 W.

18 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011

TABLE IV [2] 80 plus certified power supplies and manufacturers, [Online]. Available:

POWER FACTOR MEASUREMENTS FOR THE DNLC-PFC WITH A 4-BIT DPWM http://www.80plus.org/ (Accessed: Jan. 4, 2010).

WITH A 5-BIT d AND AN 8-BIT CURRENT A/D [3] Texas Instruments, Transition mode PFC controller, UCC28051

datasheet, Sep. 2002 (revised Mar. 2009).

[4] STMicroelectronics, Transition-mode PFC controller, L6562 datasheet,

Nov. 2005 (rev. 8).

[5] L. Dixon, High power factor switching preregulator design optimization,

in Proc. Unitrode Power Supply Design Sem., 1990, pp. 7.17.12.

[6] D. Maksimovic, Y. Jang, and R. W. Erickson, Nonlinear-carrier control

for high-power-factor boost rectifiers, IEEE Trans. Power Electron.,

vol. 11, no. 4, pp. 578584, Jul. 1996.

[7] J. P. Gegner and C. Q. Lee, Linear peak current mode control: A simple

active power factor correction control technique for continuous conduction

mode, in Proc. IEEE Power Electron. Spec. Conf., 1996, vol. 1, pp. 196

202.

[8] S. Ben-Yaakov and I. Zeltser, PWM converters with resistive input,

IEEE Trans. Ind. Electron., vol. 45, no. 3, pp. 519520, Jun. 1998.

[9] Z. Lai and K. A. Smedley, A family of continuous-conduction-mode

power-factor-correction controllers based on the general pulse-width mod-

ulator, IEEE Trans. Power Electron., vol. 13, no. 3, pp. 501510, May

1998.

[10] J. Rajagopalan, F. C. Lee, and P. Nora, A general technique for deriva-

tion of average current mode control laws for single-phase power-factor-

correction circuits without input voltage sensing, IEEE Trans. Power

Electron., vol. 14, no. 4, pp. 663672, Jul. 1999.

[11] R. Zane and D. Maksimovic, Nonlinear-carrier control for high-power-

factor rectifiers based on up-down switching converters, IEEE Trans.

Power Electron., vol. 13, no. 2, pp. 213221, Mar. 1998.

[12] International Rectifier, PFC one cycle control PFC IC, IR1150

datasheet (rev. D).

[13] Infineon, Standalone power factor correction (PFC) controller in contin-

uous conduction mode (CCM), ICE1PCS01 datasheet, Feb. 2007.

Fig. 14. Converter waveforms for very light load operation, P = 20 W,

[14] Texas Instruments, 8-pin continuous conduction mode (CCM) PFC con-

V g , rm s = 230 V, 50 Hz, 4-bit DPWM and current sensing A/D.

troller, UCC28019A datasheet, Dec. 2008, [Revised Apr. 2009].

[15] G. Spiazzi, P. Mattavelli, and L. Rossetto, Power factor preregulators

with improved dynamic response, IEEE Trans. Power Electron., vol. 12,

For both input voltage cases, the DNLC-PFC exceeds the mini- no. 2, pp. 343349, Mar. 1997.

mum power factors required for certification with a considerable [16] S. Buso, P. Mattavelli, L. Rossetto, and G. Spiazzi, Simple digi-

tal control improving dynamic performance of power factor preregula-

margin. tors, IEEE Trans. Power Electron., vol. 13, no. 5, pp. 814423, Sep.

1) Operation at Very Low Power: Fig. 14 shows the con- 1998.

verter waveforms at a line voltage of 230 V, 50 Hz, and an [17] S. Bibian and H. Jin, Digital control with improved performance for boost

power factor correction circuits, in Proc. IEEE Appl. Power Electron.

operating power of 20 W. The converter output is still regulated Conf., 2001, vol. 1, pp. 6773.

and the line current is reasonably shaped although current THD [18] K. De Gusseme, D. A. Van de Sype, A. P. Van den Bossche, and

is increased to 28.6%. J. A. Melkebeek, Sample correction for digitally controlled boost PFC

converters operating in both CCM and DMC, in Proc. IEEE Appl. Power

VI. CONCLUSION Electron. Conf., 2003, vol. 1, pp. 389395.

[19] S. Kim and P. N. Enjeti, Control of multiple single-phase PFC modules

This paper has introduced a DNLC-PFC-control approach with a single low-cost DSP, IEEE Trans. Ind. Appl., vol. 39, no. 5,

pp. 13791385, Sep./Oct. 2003.

that requires no input voltage sensing or explicit current-loop [20] W. Zhang, G. Feng, Y. Lui, and B. Wu, A digital power factor correction

compensation, yet results in low-harmonic operation over a uni- (PFC) control strategy optimized for DSP, IEEE Trans. Power Electron.,

versal input voltage range and operating power levels from high- vol. 19, no. 6, pp. 14741485, Dec. 2004.

[21] P. Mattavelli, G. Spiazzi, and P. Tenti, Predictive digital control of power

load operation in continuous conduction mode down to near- factor preregulators with input voltage estimation using disturbance ob-

zero load in discontinuous conduction mode. The controller servers, IEEE Trans. Power Electron., vol. 20, no. 1, pp. 140147, Jan.

architecture, together with simple first-order modulation 2005.

[22] W. Stefanutti, P. Mattavelli, G. Spiazzi, and P. Tenti, Digital control

blocks for control signals, enable the DNLC-PFC controller to of single-phase power factor preregulators based on current and voltage

be realized with a low-resolution DPWM, low-resolution A/D sensing at switch terminals, IEEE Trans. Power Electron., vol. 21, no. 5,

converters and a low-clock rate. The DNLC controller is suit- pp. 13561363, Sep. 2006.

[23] A. Prodic, D. Maksimovic, and R. W. Erickson, Dead-zone digital con-

able for stand-alone low-cost custom-IC implementation, or as trollers for improved dynamic response of low harmonic rectifiers, IEEE

a hardware description language (HDL) module well suited for Trans. Power Electron., vol. 21, no. 1, pp. 173181, Jan. 2006.

integration with other power control and power management [24] P. Zumel, A. de Castro, O. Garcia, T. Riesgo, and J. Uceda, A simple

digital hardware to control a PFC converter, in Proc. IEEE Ind. Electron.

functions. Experimental verification results were shown for a Conf., 2001, pp. 943948.

300-W boost DNLC-PFC rectifier. [25] A. de Castro, P. Zumel, O. Garcia, T. Riesgo, and J. Uceda, Concurrent

and simple digital controller of an AC/DC converter with a power factor

REFERENCES correction based on an FPGA, IEEE Trans. Power Electron., vol. 18,

no. 1, pp. 334343, Jan. 2003.

[1] Electromagnetic compatibility (EMC) part 3-2: Limits for harmonic cur- [26] C. P. Henze and N. Mohan, A digitally controlled AC to DC power

rent emissions (equipment input current 16A per phase), EN 61000-3-2, conditioner that draws sinusoidal input current, in Proc. IEEE Power

2006. Electron. Spec. Conf., 1986, pp. 531540.

SIMPLE DIGITAL POWER-FACTOR CORRECTION RECTIFIER CONTROLLER

MATHER AND MAKSIMOVIC: 19

[27] A. H. Mitwalli, S. B. Leeb, G. C. Verghese, and V. J. Thottuvelil, An Barry A. Mather (S03) received the B.S. and M.S.

adaptive digital controller for a unity power factor converter, IEEE Trans. degrees in electrical engineering from the University

Power Electron., vol. 11, no. 2, pp. 374382, Mar. 1996. of Wyoming, Laramie, WY, in 2001 and 2004 respec-

[28] L. T. Jakobsen, N. Nielsen, C. Wolf, and M. A. E. Anderson, Hy- tively. He is currently completing the Ph.D. degree

brid control method for a single phase PFC using low cost microcon- also in electrical engineering from the University of

troller, in Proc. IEEE Appl. Power Electron. Conf., 2005, pp. 1710 Colorado, Boulder, CO.

1715. In March 2010 he joined the Distributed Energy

[29] S. Ben-Yaakov, I. Zeltser, A. Katz, and G. Golembo, The best of two Systems Integration Group at the National Renew-

worlds: A mixed-mode front-end controller IC, in Proc. Power Electron. able Energy Laboratory, Golden, CO, where he is

Tech. Conf., Long Beach, CA, 2006. currently researching distributed photovoltaic energy

[30] Y. Chen, D. He, and R. M. Nelms, Control of a single-phase PFC pre- system integration issues. His research interests in-

regulator using an 8-bit microcontroller, in Proc. Appl. Power Electron. clude the digital control of power electronics with a focus on power factor

Conf., 2007, pp. 14541460. correction rectifiers and grid-connected inverters as well as power electronic

[31] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics. applications in renewable energy systems.

Norwell, MA: Kluwer, 2001.

[32] F. J. Azcondo, A. de Castro, V. M. Lopez, and O. Garcia, Power factor

correction without current sensor based on digital current rebuilding,

IEEE Trans. Power Electron, Preprints, vol. 25, no. 6, pp. 15271536,

Jun. 2010.

[33] A. Prodic, J. Chen, D. Maksimovic, and R. W. Erickson, Self-tuning

digitally controlled low-harmonic rectifier having fast dynamic re-

sponse, IEEE Trans. Power Electron., vol. 18, no. 1, pp. 420428, Jan. Dragan Maksimovic (M89SM04) received the

2003. B.S. and M.S. degrees in electrical engineering from

[34] H. Peng and D. Maksimovic, Digital current-mode controller for DC- the University of Belgrade, Belgrade, Yugoslavia,

DC converters, in Proc. IEEE Appl. Power Electron. Conf., 2005, vol. 2, in 1984 and 1986, respectively, and the Ph.D. de-

pp. 899905. gree from the California Institute of Technology,

[35] R. L. Haupt and S. E. Haupt, Practical Genetic Algorithms. New York: Pasadena, in 1989.

Wiley, 1998. From 1989 to 1992, he was with the University of

[36] B. A. Mather and D. Maksimovic, Quantization effects and limit cycling Belgrade, Yugoslavia. Since 1992, he has been with

in digitally controlled single-phase PFC rectifiers, in Proc. IEEE Power the Department of Electrical, Computer and Energy

Electron. Spec. Conf., 2008, pp. 12971303. Engineering, University of Colorado, Boulder, where

[37] B. A. Mather and D. Maksimovic, Single comparator based A/D converter he is currently a Professor and the Director of the

for output voltage sensing in power factor correction rectifiers, in Proc. Colorado Power Electronics Center. His research interests include mixed-signal

IEEE Energy Conv. Cong. Expo., 2009, pp. 13311338. integrated circuit design for control of power electronics, digital control tech-

[38] D. S. L. Simonetti, J. L. F. Vieira, and G. C. D. Sousa, Modeling of niques, as well as energy efficiency and renewable energy applications of power

the high-power-factor discontinuous boost rectifiers, IEEE Trans. Ind. electronics.

Electron., vol. 46, no. 4, pp. 788795, Aug. 1999. Prof. Maksimovic received the 1997 National Science Foundation CAREER

[39] D. A. Johns and K. Martin, Analog Integrated Circuit Design. New Award, the Power Electronics Society Transactions Prize Paper Award in 1997

York: Wiley, 1997. and 2008, the Bruce Holland Excellence in Teaching Award in 2004, and the

[40] S. Ben-Yaakov and I. Zeltser, The dynamics of a PWM converter with University of Colorado Inventor of the Year Award in 2006.

resistive input, IEEE Trans. Ind. Electron., vol. 46, no. 3, pp. 613619,

Jun. 1999.

- _81838a6a20f8aca444_midroot_aid_35296e4735c74a9a963c85a5cb842779_tid_uid_100002000996664_accid_100002000996664_ext_1400750364_hash_AQBVx65zO1H93Ui3iIFBiYCDMcRUploaded bydaygon
- datasheead6652t[1]Uploaded bycanhtl34
- 596b4Uploaded byChris Bowen
- Appnote 49- Interfacing PD243x Alphanum. Programmable Display w. SAB 80515SAB 80535 MicrocontrollerUploaded byJulio Fermin
- The Art of InstrumentationUploaded bysyndicate_mauli
- 1-Semi Conductor - Ijsst - High Performance - Narendra Bahadur SinghUploaded byTJPRC Publications
- Project Content PrinceUploaded byprinceofnation_21
- 51790954 Green House Environment ControlUploaded bylupu marius
- MAX186-MAX188Uploaded byradioscribd
- Bz 36459463Uploaded byAnonymous 7VPPkWS8O
- RPiMREUploaded byleoscribd13
- CHECK_E_BAE.pdfUploaded byjogoram219
- Tektronics - Oscilloscope Pocket GuideUploaded byGary Nilges
- Automatic Street Light Control SystemUploaded byHarsha
- FT8 Operating TipsUploaded byPedro Garcia
- Proj08 ECG NotesUploaded byMatthew Hon
- [Article] Analog Circuits Benefit Form Scaling TrendsUploaded byrogiebone11
- Labwork1Uploaded byAteeq Ur Rehman
- FX Analog DatasheetUploaded byYuwarath Suktrakoon
- Orca MITUploaded byMaciek Olszowski
- esd lab file cs.docxUploaded byVivek Dutta
- Tech Appendix Mimolite 05may2015Uploaded byalanbrann
- Raghu ReportUploaded bymaheshfb
- A New Single-Phase Single-Stage Three-Level (2)Uploaded byGururaj Banda
- 1413-pp001_-en-pUploaded byHoussam Zein
- AD9215Uploaded bykopepi
- 2107fbUploaded bydeshon
- High-Efficiency Multiple-Output DC–DC Conversion for Low-Voltage SystemsUploaded byBadr Salhi
- dlc assUploaded byanon_776365175
- 236418fUploaded byrotenolabs

- Doebelin - Measurement Systems Application And Design.pdfUploaded byHilberto Filho
- BP lathiUploaded byriti9903
- Digital Signal Processing 4th edition - Proakis and Manolakis.pdfUploaded byHilberto Filho
- Computer System Architecture (3rd Ed) by M Morris Mano.pdfUploaded byNarasimha Reddy
- Doebelin - Measurement Systems Application And Design.pdfUploaded byHilberto Filho
- A New Induction Motor Vf Control Method Capable of High-performance Regulation at Low SpeedsUploaded byHilberto Filho
- speed control of a three-phase induction motor based on robust optimal preview control theory.pdfUploaded byHilberto Filho
- 70900266-R-Krishnan-Electric-Motor-Drives-Modeling-Analysis-And-Control.pdfUploaded byHilberto Filho
- Feedforward pulse width modulator for switching power converters.pdfUploaded byHilberto Filho
- 06472322Uploaded byKishore Ck
- Full Text 01Uploaded byyiannis_ath84
- Input Filter Design for Multiple-module DC Power SystemsUploaded byHilberto Filho
- Control Techniques for Power Factor CorrectionUploaded bysatya_9145
- Fundamentals of Telecommunications Engineering (TC-101).pdfUploaded byraymon6666

- LabPlanningManual ControlUploaded byApiwat Dattit
- Q2426BUploaded bycurioso207
- 1Uploaded bysh_saraydin3949
- Tuner84 RDA5807M Datasheet v1Uploaded byice_cold
- MK120S_Users_Manual.pdfUploaded byEko Agus Murjito
- Power Supply Tips TricksUploaded byarturo53
- Edan SE-2003 & SE-2012 Holter User ManualUploaded byfpanci
- The Development of the Digital Oscilloscope Based on FPGA.pdfUploaded byivy_publisher
- Fuzzy Logic Applied to Motor Control 2Uploaded byBHARANI DHARAN.K
- Design of Low Power, High Speed 3-Bit Pipelined ADCUploaded byInternational Journal for Scientific Research and Development - IJSRD
- Stationary Random Process and Digital Signal Processing - TheoryUploaded byShivanshu Trivedi
- 4-10 Bit, 0.4-1 v Power Supply, Power Scalable Asynchronous SAR-ADC in 40 Nm-CMOS With Wide Supply Voltage Range SAR ControllerUploaded byPhuc Hoang
- Digital%2520Signal%2520ProcessingUploaded byapi-26581966
- RTU Training DIGSI Training DIGSI001 5Uploaded byRatheesh Kumar
- tms320f28035Uploaded byMadalina-Alexandra Puscasu
- 47642.pdfUploaded byMohamed Hascuri
- UPD703100-33Uploaded bynorbertscribd
- Cognitive RF Front-End ControlUploaded byEyosias Yoseph
- oscilloscopes_basics.pdfUploaded byfptstop
- Lg m2262d Pzl Chassis Ld93aUploaded byvideoson
- RED521Uploaded byvsrikala68
- TTester_1.10k_EN_140409-1Uploaded byDomingo Arroyo
- Er9x ManualUploaded bySuresh Jayachandran
- Energy HarvestingUploaded byமனோஜ் தர்மராஜன்
- D.P.transmitter Spriano 47B ManualUploaded byBruno
- kbpc_240dUploaded byAngel Montellano
- Low-power All-Analog Circuit for Rectangular-typeUploaded byDevaraj Subrmanayam
- REAL-TIME END-TO-END SECURE VOICE COMMUNICATIONS OVER GSM VOICE CHANNELUploaded byVimal Kaurani
- Unit 6Uploaded byNeha Chinni
- Voltage Reference Selection BasicsUploaded bytonyariel