Sie sind auf Seite 1von 10

634 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-18, NO.

6, DECEMBER 1983

A Precision Curvature-Compensated
CMOS Bandgap Reference
BANG-SUP SONG, STUDENTMEMBER,
IEEE,ANDPAUL R. GRAY, FELLOW,IEEE

Ab.~tract A precision curvature-compensated switched-capacitor band- cancellation to achieve experimental typical temperature
gap reference is described which employs a standard digital CMOS process drifts of 13.1 and 25.6 ppm/ 0C over the commercial and
and achieves temperature stability significantly lower than has previously
been reported for CMOS circuits. The theoretically achievable tempera-
military temperature ranges, respectively. In the proposed
ture coefficient approaches 10 ppm/ 0 C over the commercial temperature reference, a temperature-stable voltage is developed by
range utilizing a straightforward room temperature trim procedure. Experi- adding linear and quadratic temperature correction volt-
mental data from monolithic prototype samples are presented which are ages to the forward-biased diode voltage which is obtained
consistent with theoretical predictions. The experimental prototype circuit
from the substrate p-n-p transistor available in CMOS
occupies 3500 milsz and dissipates 12 mWwith+ 5 V powersupplies,The
proposedreferenceis helieved to be suited for use in monolithic data processes. The linear temperature correction voltage is
acquisition systems with resolutions of 10 to 12 bits. proportional to the absolute temperature (commonly called
PTAT) while the quadratic temperature correction voltage
is proportional to the absolute temperature squared
I. INTRODUCTION
(PTAT2). They are independently adjustable to set the
reference output voltage for a minimum temperature drift.
AN essential element of the analog and digital inter-
face function is a voltage reference to control the
scale factor of conversion. The temperature stability of a
The offset voltage of the CMOS op amp is eliminated
using the correlated-double sampling (CDS) technique [9].
reference source is a key factor in the accuracy of the The base current and base spreading resistance of the
native substrate p-n-p transistor are cancelled to the first
overall data acquisition function. Therefore, the ability to
integrate an entire data acquisition system within a single order and the amplification ratio is set by a capacitor ratio
CMOS VLSI chip is contingent upon the ability to realize a rather than a resistor ratio. Due to the cyclic behavior of
CMOS compatible voltage reference with a very low tem- the offset cancellation in this technique, the output refer-
perature drift. Since its introduction by Widlar [1], the ence voltage is not available at all times. However, the
bandgap referencing (BGR) technique has been widely reference can be operated synchronously with other ele-
employed for implementing a voltage reference source in ments of the systems. Since the periodic offset sample and
bipolar integrated circuits. The temperature stability of the subtraction cycle effectively removes the low-frequency l/~
bandgap reference has been continuously improved via noise component of a CMOS op amp along with its offset,
new circuit and technology innovations such as curvature the dominant noise source is the thermal noise of a CMOS
compensation and laser trim [2][5]. In CMOS technology, op amp which is designed to be on the order of 100 pV
the BGR technique has been directly applied [6][8]. How- (rms) at the output in 500 kHz bandwidth.
ever, the development of a high-performance CMOS band- In Sections II and III, the primary limitations in a
conventional CMOS BGR implementation and the temper-
gap reference has been hindered by several limiting factors
attributable to the peculiarities of the bipolar devices avail- ature curvature in bandgap references are discussed. In
Section IV, a curvature-compensated switched-capacitor
able in a standard CMOS process, the high offset and drift
CMOS bandgap reference is introduced. In Section V,
of CMOS op amps that make up the circuit and the
experimental results measured from monolithic prototype
inherent curvature problem in the bandgap reference.
This paper will describe one circuit implementation of a samples are presented and the problems related to the
design of p-n-p transistors are discussed. The theoretical
precision CMOS bandgap reference which overcomes some
analysis of BGR temperature compensation techniques is
of the drawbacks of a standard CMOS process, and em-
bodies curvature compensation and differential offset included in the Appendix.

II. CONVENTIONAL
CMOS BGR IMPLEMENTATION
Manuscript received April 6, 1983; revised August 3, 1983. This work
was supported by the National Science Foundation under Grants ECS-
8023872 and ECS-8120012, IBM Corporation, and the MICRO Project.
One example of a conventional CMOS BGR implemen-
B.-S. Song is with Bell Laboratories, Murray Hill, NJ 07974, tation in an n -well CMOS process is shown in Fig. 1.
P. R. Gray is with the Department of Electrical Engineering and
Computer Science, Electronics Research Laboratory, University of Cali-
Transistors QI and Qz are substrate p-n-p transistors whose
fornia, Berkeley, CA 94720. collectors are always tied to the most negative power

0018-9200/83/1200-0634$01 .00 01983 IEEE


SONGANDGRAY:PRECISIONCURVATURE-COMPENSATED
CMOSBANDGAPREFERENCE 635

Base Emitter
1
R2 R3
t P+ h+
v
0s

Vref
0
-1
%
I 1, +12
V,ef=VBE+(
I+% )(AVBE+Vo~) (a)
I
[ ~ Q, Qz
y- AV,E +?
L L
v Ss
Fig. 1 Example of a conventionalCMOS bandgap reference. rb/A

I
supply because, in an n -well CMOS process, the p+ &
diffusion in the n--well, the n--well itself and the p- I I
substrate form a vertical p-n-p structure as shown in Fig. (b)
2(a). Therefore, it is not possible to sense the collector
Fig. 2, (a) Substrate p-n-p transistor profile. (b) Nonideal parameters in
current directly as in the bipolar bandgap reference so as the PTAT correction voltage generation circuit.
to reduce the error due to the finite current gain [3], [4]. In
a p -well process, a dual circuit incorporating n-p-n tran-
sistors would be used. While many other circuit implemen- this circuit is the emitter current. The third term results
tations are possible, this circuit appears to be as good as from the voltage drop in the finite series base resistance.
any. Therefore, individual error sources will be described The difference between the two emitter-base voltages is
one by one for this circuit in the rest of this section. All given by
resistors are the p -diffusion resistor in the n -well and the
CMOS op amp is assumed to have an infinite gain with the 1
offset voltage of VO,.This assumption is justified because
AVBE = V~ln A + V~ln $ + V~ln ~
l+Fl
CMOS op amps usually have enough gains such that the 1 rlbid
error due to finite-gain effects is negligible for this applica- 1+T2
tion.
Assuming that transistor Q1 in Fig. 1 has an area that is (3)
larger by a factor A than transistor Qz, and both are in the
where 12is the emitter current of transistor Qz and B2is the
forward active region, the output voltage of the reference is
current gain of transistor Qz. If the bipolar transistors used
given by
to implement the reference are ideal in the sense that they
have infinite current gain and zero base resistance, and if
~ef=vBE+
(1
1+:
1
(AVBE+V&) (1) the emitter currents of the transistors are in fact equal,
then only the first terms in (2) and (3) are nonzero.
where VBE is the emitter-base voltage of transistor Q1, However, because of the relatively poor performance of
AVBEis the difference between the emitter-base voltages of CMOS-compatible devices, these terms can strongly in-
transistors Q1 and Q2, and VO,is the input offset voltage of fluence the performance of the reference. The presence of
the operational amplifier. The value of this expression is the operational amplifier offset voltage in the output, mul-
influenced by the nonidealities of the bipolar transistors as tiplied by the gain factor (1+ R ~/R1), which is typically
illustrated in Fig. 2(b). If these are taken into account, the on the order of 10, is also an important degradation.
transistor emitterbase voltage is given by Finally, the variation of the bias currents 11 and Iz with
temperature must be carefully considered. In the following
1 rb11
VBE= FJn # + F~ln~ + (2) subsections, the effects of these nonidealities are examined
S1 A& in more detail.
l+Fl
A. Operational Amplifier Offset
where VT is the thermal voltage kT/q, 11 is the emitter
current of transistor Q1, Isl is the saturation current of The operational amplifier offset is the biggest error
transistor Ql, & is the current gain of transistor Q1 and rb source that causes the nonreproducibility in the output
is the effective series base resistance of Qz. The second voltage temperature coefficient. Normally, a bandgap ref-
term in this expression results from the fact that while erence is trimmed to an output voltage which is prede-
the collector current is a well-defined function of the termined to give a near-zero temperature coefficient of the
emitter-base voltage, the current sensed and controlled by output. Large, non-PTAT components in the output due to
636 CIRCUITS,VOL.SC-18,NO. 6, DECEMRER
IEEEJOURNALOF SOLID-STATE 1983

the op amp offset cause the trimming operation to give an portion can be compensated by simply changing the target
erroneous result. If we assume the offset voltage VO,is trim value of the output voltage. For example, (6) can be
independent of temperature, the resulting temperature used to show that a 1000 ppm/ 0C resistor TC would
coefficient error due to a 5 mV VO$,for example, is result in a 21 ppm/ 0C reference output TC, which
approximately could be removed by simply raising the output voltage trim
target by approximately 8 mV. However, cancellation of
1++ Vo, PTAT2 term precisely requires curvature compensation
(1 1 10 X5mV discussed later.
TC error =
~,f TO = 1.26 VX300K
C. Other Effects
=132 ppm/ C. (4)
The effects of various nonidealities, including base resis-
That is, a temperature coefficient on the order of 132
tance, ~ mismatch, @ variations with temperature, and ~
ppm/ 0C will result in the reference output temperature variations with collect current can be evaluated with the
coefficient from a 5 mV temperature-independent offset use of (l), (2), and (3). Which of these effects is the most
voltage in the operational amplifier if the reference is important in a given circuit application is strongly depen-
trimmed assuming the offset is zero. This offset error dent on the nature of the bipolar transistors in the particu-
contribution can be reduced by making AVBEbigger, in lar technology used. If the well (base) doping is particularly
effect decreasing the gain factor (1+ R2 /R1) as implied by light, as is often the case, then the intrinsic base resistance
(l). One way to achieve this is to obtain AVBEby taking the effect, represented by the last term in (3), may well be the
difference of two cascaded transistor strings discussed later most important. The temperature coefficient in the output
in Section IV. In this work, however, offset cancellation due to this term is given by
technique is employed to further reduce this error while the
cascading scheme is used for the PTAT current generation.

B. Bias Current Variation


cerrOr=(l+wwb*+@
+2a (7)
If the resistors RI, R2, and R3 have a zero temperature
For example, assuming a 2 kfl base resistance with 1000
coefficient, then the bias currents in transistors QI and Qz
ppm/ 0C TC, a 30 PA PTAT bias current level, a /3 of 150,
must be PTAT since the voltage across RI is PTAT. The
and a ~ TC of 7000 ppm/ 0C, an output TC of 8.6
finite temperature coefficient of actual resistors formed
ppm/ 0C results. As in the case of the bias current varia-
from the source-drain diffusion or from polysilicon layers
tion, this can be partly compensated by modifying the trim
results in non-PTAT variation of the bias current. This in
target voltage if these parameters are reproducible. The
turn causes an additional component in the temperature
other errors mentioned above are negligible if transistor
variation of the V~~ term in the output. If only the first
performance is reasonably good. Another error source re-
two terms of (2) and (3) are taken, the V~~ is given by
sults from the temperature coefficient of the ratio of the
VJn A diffused resistors RI and R2. Data presented later show
V~~ = V~ln #- = V~ln ~ that for resistors used in this experimental work a differen-
S1 1 S1
tial ratio TC of 1 to 2 percent is achieved. Fortunately, this
V~ln A Rl(%)
= VJn (5) error is negligible compared to those already discussed.
Rl(To)~sl Vin RI(T)

where TOis the reference temperature, usually room tem- III. CURVATURE IN BANDGAP REFERENCES
perature. Note that the first term is the V~~ variation that
For a bandgap reference which is ideal in the sense that
results when there is no resistor temperature coefficient,
the operational amplifier is ideal, the bipolar transistors
and the second is that which results when a temperature
have infinite current gain, zero intrinsic base resistance,
coefficient is present, Further insight can be obtained by
and have perfect exponential junction relationships, and
expanding this second term as a Taylor series in tempera-
the bandgap of silicon varies linearly with temperature, the
ture about TO,and neglecting higher order terms:
output voltage is typically given by [10]
BE = BEl,dezd T

.;$$ ~(T-To)-VT&
0
$ $T-TO)2-
.
... . (6)
V,c~=VgO+V~(4na)
()
l+ln$
0
(8)

where VgOis the extrapolated silicon bandgap at O K, n is


From this relation it can be seen that even a purely linear the exponent of the mobility variation in the base of the
variation in resistor value with temperature results in an bipolar transistor (typically about 0,8), a is the exponent of
output temperature variation with both PTAT and PTAT2 the temperature variation of the bias current (1 for PTAT
temperature variation components. Assuming the resistor bias current, for example), and TOis the temperature at
temperature behavior is known and reproducible, the PTAT which the reference output temperature coefficient is zero,
SONGANDGRAY:PRECISIONCURVATURE-COMPENSATED
CMOSBANDGAPREFERENCE 637

usually chosen to be near room temperature. Equation (21) KV~ , FV;

derived in the Appendix is the more general form of (8).


This relation illustrates the well-known fact that even for
an ideal bandgap with an optimally chosen TO,the output I

voltage as a function of temperature displays a curvature


which causes it to decrease both for temperatures higher or
lower than TO.Usually, the practical performance aspect of
interest is the maximum total variation of the output
~vref
voltage over the range of temperatures. A further complica-
tion is the fact that the bandgap of silicon in fact does vary 1

Emi!r
with T2, as well as linearly with temperature [11], [12]. This
higher order temperature variation adds a curvature term,
increasing the effective TC even for optimally adjusted
-references. These effects together combine to give a best
TO T To T T. T
achievable TC of about 25 ppm/ 0C for a temperature
range of 55 C to 125 C. Fig. 3. Curvature-compensationconcept (not seated).
Several approaches have been suggested for curvature
correction. If the quantity (4 n a) in (8) could be made
I Temp Indep [Tll I ID
zero, then there would be no curvature other than the
Current
curvature of the silicon bandgap. This could be achieved I Generator ,b----l I
for example by using a very strongly temperature-depen-
dent bias current or by linearizing V~~directly [5]. Several I
authors have proposed simply adding in higher order tem-
perature-dependent terms in the output to cancel the
PTAT2 term of the output voltage variation [4]. This is the
approach used in this paper to be described in the next
section.

IV. PRECISION SWITCHED-CAPACITOR CMOS BGR Fig. 4, Overall schematic of the curvature-compensatedswitched-capa-
citor CMOS bandgap reference.
TECHNIQUE

In order to implement voltage references in CMOS tech- block is determined by the capacitor ratio C2/Cl. The
nology which have performance approaching that achiev- current 10 is temperature-independent (TI) while 1~ is
able in bipolar technology, special steps must be taken to PTAT. The bias current 1~ is also TI.
counteract the relatively poor performance of CMOS op If the effects of the base current and the base spreading
amps and CMOS compatible bipolar transistors. In addi- resistance are neglected, the reference output V,~fis given
tion, curvature compensation, already widely applied in by
bipolar references, must be incorporated. In this section,
the implementation of the techniques in CMOS technology (9)
is described.

where
A. Curvature Compensation

The overall concept of BGR temperature compensation


is illustrated in Fig. 3 and general BGR temperature com-
pensation techniques are described in the Appendix. The
first step is to add a PTAT correction voltage KVT to V~~
to cancel out the linear temperature variation of V~~.After
vT1nA+2v&)+M:
r+ 10)
the PTAT correction voltage is added, the reference output The inclusion of the PTAT2 voltage means that the trim
V,efwill exhibit mostly the quadratic temperature variation procedure for the reference consists of two steps, one to
as shown in Fig, 3. If a PTAT2 correction voltage IV; is give the correct output voltage for the uncompensated
added to that to cancel out the quadratic temperature reference, and one to trim the value of the PTAT2 voltage
variation of 1~~,the final reference output V,efshould drift that is added in. A key advantage of the circuit configura-
only due to higher order temperature variations and a zero tion chosen is that it allows the PTAT2 component to be
temperature coefficient is achieved at TO.One implementa- adjusted independently from the basic reference. The first
tion of a switched-capacitor bandgap reference which em- part of the trim procedure is to disconnect the PTAT2
bodies curvature compensation as well as offset-cancelled component (set 1~ to zero), and trim the absolute output
amplification is illustrated in Fig. 4. The gain G of the gain voltage. In the particular experimental device described
638 CIRCUITS,VOL.SC-18,NO. 6, DECEMBER
IEEEJOURNALOF SOLID-STATE 1983

Voo

Vss
Fig 5. PTAT and TI current generators for the bias currents IT and 10.

here, it is most convenient to do this with a combination of


a capacitor array to adjust the Cz/C1 ratio, and a resistor
Io=+(~+vm2) (12)
3
string to provide fine adjustment through adjustment of
the bias current Id. Even though two different physical and
trim arrays are involved, in effect one trim operation is
performed and a total resolution of approximately 12 bits ID=+(K+V.J,
4
(13)
is achieved in the absolute value of the final output voltage.
Next the PTAT current 1~ is turned on and its ratio to 10 is The factor 2 in (11) results from cascading transistors
adjusted with another resistor string to give a change in the Q4 - Qti and Q5- Q7 @ reduce the error contribution of the
output equal to the desired PTAT2 compensation value. mismatch voltage V*l. For this application, cascading of
Both trimming operations are done at room temperature. two devices is enough for the PTAT current generation.
The currents lT and 10 are generated using the circuit Depending on applications, several transistors can be
shown in Fig. 5, The bias current ID is generated in the cascaded to reduce the offset error contribution in such a
same manner as the TI current 10. The stacked-cascode BGR implementation, discussed in Section II. Substituting
connection formed by transistors Ml to kf~ causes the (11), (12), and (13) into (9) and (10), and neglecting higher
emitter currents of transistors Q6 and Q, to be equal. orders, we obtain
The same scheme is also employed for the matching of the
emitter currents of transistors Qg and QIO. Transistors J4g
and &l10form a start-up circuit for this self-biased circuit.
As indicated, transistors Q1 and Q6 have emitter areas
= BEl,deil + ~vT + ~v; + ~ (14)
larger by a factor of A than the remaining transistors.
Therefore, the voltage developed across the resistor RI is where
PTAT and the current Z~ through RI is also PTAT. The
voltage VOformed by the transistor Qg and the resistor R ~ ~= ~++ ,(vT-vT)T+2yJ5vJ#vm,
is approximately temperature independent. The tempera- 0 o 110
ture stability of POis not critical because it affects only the
C2R3V~ln A
PTAT2 component of the output voltage (not PTAT). The 4 cRv~ V.2+5VV. 3 (15)
TI voltage VOis developed across R3 and the current 10 110
through R ~ is also TI. Therefore, the current ratio 1~/10 is
easily trimmed by R ~. The constant u represents the standard deviation (%) of the
In the presence of the mismatches of Ml M2 and temperature coefficient of R4. The error voltage V, is less
J411 M12 transistor pairs, the voltages across RI and R ~ than 1 mV at room temperature. Therefore, the tempera-
deviate from the ideal values. If the gate-source voltage ture coefficient uncertainty resulting from the mismatch
mismatches of MOS transistor pairs inclusive in the bias voltages is 50 times smaller than the uncertainty caused by
circuit of Fig. 5 are assumed to be V~l, V~2, and V~3, the op amp offset of existing designs given by (4).
respectively, and current mirrors and p-n-p transistors are
assumed to be ideal, the three bias currents 1=, 10, and ID B. Offset- Cancelled Amplification
are given by
In order to remove dc offsets from the amplifier, it is
divided into two stages as shown in Fig. 6. In the first
1~ = ~ (2V~ln A + V~l), (11)
1 offset-storage mode, all the MOS switches are closed to
SONGANDGRAY:PRECISIONCURVATURE-COMPENSATED
CMOSBANDGAPREFERENCE 639

s,

M,9 Me M12 M9 M13


1 1
I k I I 4 i
UI ~111

I
M,e
I I

[ M6 M,

Vf I

iiiK5W
2FF+P+ v Ss

Fig. 7. Amplifier configurationfor Al and A~.

pensation capacitor between the high impedance node and


- Input Referred h .q = Vfz J I%
the ac ground ~,. When the two op amps are cascaded and
(c)
the feedback loop closed around the composite amplifier, a
Fig. 6. Gam block which embodies offset-cancelled am Iification. (a) Miller capacitance is switched in from the high impedance
First offset-storagemode. (b) Second offset-storage moc?e. (c) Amplifi-
cation mode. node of the second stage to the same node of the first stage
to achieve a pole-splitting compensation.

sample the offset voltages of the individual op amps. In the


C. Base Current Cancellation
process of opening the MOS switches $ and S2, the
channel charges are injected into the op amp summing In the CMOS process used, the current gain of substrate
nodes to load the capacitors Cl and Cz, The charge injec- p-n-p transistors is often limited and highly variable.
tion differential voltage Vfl due to the mismatch of switches Therefore, to compensate for the difference between the
S1 and S2 is sampled across Cl and C2 along with the offset collector current and the emitter current, the base current
voltage VO,l. In the second offset-storage mode, the first has to be returned to the emitter as shown in Fig. 8(a).
gain stage charges the coupling capacitor to compensate However, a simpler approach is to replicate the base cur-
for the input differential voltage VI, After the switches S3 rent and allow it to flow into the emitter as shown in Fig.
and Sd are opened, two stages are connected in a feedback 8(b). The base current is cancelled with an accuracy of
amplification mode, and the amplification of AV~~ takes about 90 percent because the base currents typically match
place by the capacitor ratio C2/C1. When referred to each other within 10 percent for the adjacent transistors on
input, the feedthrough difference of the switches S3 and SJ a single chip.
is reduced by the open-loop gain of the first stage. Note the
bottom plate of one capacitor Cl should be connected to D. Base Resistance Cancellation
the diode voltage in the actual reference as shown in Fig. 4.
A single-pole folded-cascode CMOS op amp configura- The effective series base resistance of the bipolar transis-
tion for Al and Az is shown in Fig. 7. Two amplifiers are tors consists of that produced by lateral flow in the base
identical and designed to meet the following requirements: region under the emitter, and the extrinsic base resistance
1) moderate gain for each stage (100 to 300); between the base contact and the active base. The former is
2) single dominant pole per stage; bias dependent and difficult to predict, while the latter is
3) inherent zero systematic offset voltage; and more straightforward to predict given device geomet~. The
4) capacitor driving capability (15 pF for one stage and approach taken here is to include a lumped resistor R ~O~P
100 pF for two stages). made of the same n -well diffusion material so as to
Transistors Mlp M21 form a bias string for the ampli- achieve approximate tracking with temperature and pro-
fier. The replica bias circuit formed by transistors Mlq MIT cess variations. The value of Rcompin Fig. 9 should be
performs a level shift and a differential to single-ended
conversion, and reduces the inherent systematic offset. In
order to limit the gain of each stage, the lower part
composed of transistors J4d Mj is not cascoded while the
-=(+3-+ (16)

upper part Iv& Mg is. The class-A source follower stages For the process used here, the magnitude of the extrinsic
formed by transistors Al10- M13 are added to meet the compensation resistance is about one quarter of the mea-
capacitor driving capability. In the offset-storage modes, sured intrinsic base resistance of p-n-p transistors with the
each op amp is stabilized by connecting a frequency com- same geometry.
640 CIRCUITS,VOL.SC-18,NO. 6, DECEMBER
IEEEJOURNALOF SOLID-STATE 1983

~. i J
(a) (b)
Fig. 8. Basecurrent cancellationschemes.(a) lB returning. (b) ZBrepli-
cation.

rbi
Intrinsic Base Resise
h

+
,.

~
. INTRINSIC RESISTANCE

-
p._.__J ?~? 1
+

Extrinsic Compensation Resistance


- w,,, Fig. 10. Chip photo of the experimental prototype.
~.

%iw = %,b
= rbl rb,lA COMPENSATION RESISTANCE

(a) (b)
Fig. 9. Base resistance cancellation. (a) Extrinsic compensation resis-
tance R .Omp. (b) llifference between intrinsic base resistance and
extrinsic compensation resistance.

V. EXPERIMENTAND DISCUSSIONS

The experimental prototype circuit implementing the


proposed reference was fabricated employing a self-aligned
single-poly Si-gate CMOS process on a 20-30 0. cm
boron-doped p-type (100) substrate. The gate oxide is 0.07
pm thick and the drawn minimum feature is 6 pm. Fig. 10
shows the microphotograph of the prototype chip and Fig. Fig. 11. Waveforms. (a) Output sync clock. (b) Vref.
11 shows its output waveform as well as output sync pulse.
Experimental daka were gathered from seven representa-
tive samples from one wafer. Every experimental chip at room temperature to an output voltage predetermined
contains three types of reference voltages. The Type 1 from the first sample. Statistical data from seven samples
reference has no curvature compensation, no base current are summarized in Table I for three types of reference
cancellation. no base resistance cancellation. and no offset voltages. The optimum values of the PTAT 2 correction
cancellation, and amplification is performed by a resistor voltage, the first-order corrected and second-order cor-
ratio. The Type 1[ reference which uses a capacitor-ratio rected V,,fs at 250 C were found to be 61 mV, 1.256 and
amplification has the cancellations of offset, base current 1.192 V, respectively. Estimating from the measured data,
and base resistance, but no curvature compensation. How- the parameters J&l, Vg02, and 4 n a necessary for
ever, the Type 111[reference which also uses a capacitor specifying the prototype bandgap reference were 1.181,
ratio amplification has all components of the Type II 1.158, and 2.623 V, respectively.
reference plus curvature compensation. Note that the offset-cancelled amplification and com-
Following the procedure described in Section IV and the pensation of rb and ~ effects give a factor of 5 improve-
Appendix, one sample was adjusted to give a minimum ment in temperature stability and its deviation over the
temperature drift and the other six samples were trimmed approach without any compensation. By curvature com-
SONGANDGRAY:PREC1S1ON
CURVATURE-COMPENSATED
CMOSBANDGAPREFERENCE 64 I

TABLE I
STATISTICS
OFMEASURED
TEMPERATURE COEFFICIENTS
OF7 SAMPLES
(ppm C)

Standard
oto70c: Mean Deviation Minimum Maximum
Type I 105 43 42 167
Type II 22.3 10.8 11.1 42
T~e III 13.1 7.1 5.6 25.7
55 to 125 C:
TWe I 185 56.5 107 273
Type II 35.1 18.8 17.6 66.7
Type III 25.6 10.5 12.1 39.9

0 (a)

AVre, ~p: 1 \
[mV) I
I I i t
-5 Type I

1 I I L I I I I I I I
50 0
TEMPERATURE
50
(C )

Fig. 12. Typicaf measured temperature variations of three types of


references when they are optimally compensated.
I 00

UB=r (b)
Fig. 13. Substrate p-n-p transistor. (a) A unit cell. (b) Drawn dime]n-
sions of a unit cell (~m).
TABLE II
PERFORMANCE
SUMMARY
V,ef 1.192V*lmVat25 C current range. The current gain ~ is also relatively constant
TC SeeTable I
Power 12 mW with + 5 V supply
within this range. However, in the emitter current range
Load 100 pF capacitor over 100 p A, the base crowding effect is severe. Also, in
Cycle time 5 ps the emitter current range below 1 PA, the current gain ~
+ PSRR 50 dB (de) decreases due to space charge recombination in the
PSRR 60 dB (de) emitter-base junction. The unit cells of Fig. 13 were con-
Clock RR 75 dB
nected in parallel to obtain a multiple-emitter device. The
Output noise 400 pV (500 kHz)
current gain /3 is minimum at 550 C and the average
value at room temperature is 175. Temperature data for the
pensation, a factor of 2 further improvement was obtained. p-n-p transistors and p+ diffused resistors in the n--well in
Fig. 12 compares graphically those three types of optim- the particular technology used here are listed in Table III.
ally-compensated bandgap references. The experimental The temperature coefficients of diffused resistors match
results are summarized in Table II. To improve the power each other within 1.2 percent.
supply rejection ratio (PSRR), the base of all p-n-p transis- One potential problem in the use of the substrate p-n-p
tors should be biased at a constant voltage relative to the transistor is the fact that the dc collector current flows into
negative supply line, Otherwise, the base width modulation the substrake. If this current gives rise to a large enough
(Early effect) will limit the PSRR of the reference, ohmic drop in the substrate, it could initiate latchup. To
The critical aspect of the design is the substrate p-n-p minimize the likelihood of this, each n -well (base) was
transistor because the n -well in CMOS processes usually surrounded by the p+ diffusion (collector) as shown in Fig.
has a relatively high resistivity. In order to minimize the 13. No latchup was observed during experimental measure-
intrinsic base spreading resistance, the base contact sur- ments even under transient conditions.
rounds the emitter junction as shown in Fig. 13, The
emitter junction and the base contact plug are separated by
9 pm. By the surrounding base, the intrinsic base resistance VI. CONCLUSION
is reduced by a factor of 6 when compared to the parallel
contact of emitter and base. For the process used here, the A precision curvature-compensated switched-capacitor
estimated rb of this geometry is about 1.5 kfl. With this CMOS bandgap reference is reported whose monolithic
geometry, the observed emitter area reduction due to the prototype exhibits average temperature drifts of 13.1 and
base crowding is insignificant over the 1 to 100 PA emitter 25.6 ppm/ 0 C over the commercial and military tempera-
CIRCUJTS,VOL.SC-18,NO. 6, DECEMBER
IEEEJOURNALOF SOLID-STATE 1983

TABLE III
TEMPERATUJW AND p-n-p TRANSISTORS
DATAOFDIFFUSEDFWSISTORS
(-55 to125c)

Standard
Diffused Resistors: Mean Deviation Minimum Maumum
Sheet resistance (Q/square) 68.9 3.1 64.6 72.1
TCor R* 886 27.9 849 917
Ratio of 6R /R** 5.952 0.02 5.9304 5.9794
TC of 6R/R* 10.6 2,2 8.9 13.6
p-n-p Transistors:
Current gain /? at IE = 30 pA 175 83 91 273
TCoffl* 6503 872 5471 7792

*TC unrt is ppm/ 0 C.


**R and 6R are composedOf 40 and 240 squares of 6 pm-wide p + diffusion.

ture ranges, respectively, employing a straightforward room A. First-Order Temperature Compensation


temperature trim procedure without thin-film resistor and
laser trim. The design features second-order temperature If only the linear temperature variation of V~~in (17) is
compensation, simple room temperature trim up to 12-bit compensated by adding the first-order correction voltage
accuracy and complete cancellation of the offset and long- KVT to V~~, the reference output V,cfis
term offset drift of CMOS op amps. A reference voltage is Vre.= VBE+ KVT
obtained by systematically adding first-order and second-
=Vg V~(4na)ln T
order correction voltages to the emitter-base potential of
the substrate p-n-p transistor. Each correction voltage is -t(K+H+h13G)vT LV;. (20)
individually trimmable to minimize temperature drift. The
proposed reference is compatible with a standard digital By equating the derivative of fi,f at TO to zero and
CMOS process and is applicable to high-resolution mono- eliminating the unknown constants, we obtain
lithic CMOS data acquisition systems.
dVg
f= g -dT TO+vT4-n-a)(l+ln~)
APPENDIX
BGR TEMPERATURECOMPENSATIONTECHNIQUES
-L++). (21)
Employing (6) and neglecting higher orders, the for- The first two terms and the last term of (21) result from the
ward-biased diode voltage is given by [10] nonlinearity of the Si bandgap over temperature and the
bias current variation, respectively, and will not disappear
V~~=Vg V~[(4n a)ln Tln EG]+HV~ LV~
until higher order temperature variations are compensated.
(17) Without these, (21) @ identical to (8). Tsividis [12] recently
explained the Si bandgap temperature dependence employ-
where Vgis the bandgap of silicon which is a function of ing equations from Bludau et al.s [11]. From (21), the
base doping [13] and temperature [11], [12], n and a are nominal voltage at TOis therefore
parameters illustrated in (8), E and G are the parameters
whose magnitude are insignificant in the temperature anal- reflTO= Vgol + TO(4 n ~)+LV~ (22)
ysis [10], and H and L are defined from (6)
where
H=T 1 dR
and (18)
ORdTTO dVg
vgol=vg(To) ~ To =1.205 V. (23)
To
(19)
As commonly called, V,Ol is the linearly-extrapolated Si
bandgap voltage at T= O K. Equation (22) indicates that
That is, if the bias current variation and the silicon band- the bias variation resulting from the temperature coeffi-
gap curvature discussed in Sections II and III are included, cient of diffused resistors causes the nominal voltage differ-
the V~~in (17) is the actual diode voltage whose tempera- ent from a theoretical value.
ture variation is to be compensated to give a temperature
stable reference voltage. In the next two subsections, first- B. Second-Order Temperature Compensation
and secondl-order temperature compensation techniques
are discussed in more detail. If the linear and the quadratic temperature variations of
SONGANDGRAY:PRECISIONCURVATURE-COMPENSATED
CMOSBANDGAPREFERENCE 643

V~~ in (17) are compensated as illustrated in Fig. 3 by REFERENCES


adding both the first-order correction voltage KV~ and the
[1] R. J. Widlar, New developments in IC voltage regulators, IEEE
second-order correction voltage FV~ to V~~, the reference J. Solid-State Circuits, vol. SC-6, pp. 2-7, Feb. 1971.
output Vr~fis [2] K. E. Kujik, A precision reference voltage source, IEEE J.
Solid-State Circuits, vol. SC-8, pp. 222-226, June 1973.
[3] A. P. Brokaw, A simple three-terminaf bandgap reference, IEEE
~ef = VBE+ KVT + Fv; J. Solid-State Circuits, vol. SC-9, pp. 288-393, Dec. 1974.
[4] C. R. Palmer and R. C. Dobkin, A curvature corrected micro-
=~ V~(4na)ln7 power voltage reference, in Proc. Int. Solid-State Circuits Conf.,
Feb. 1981, pp. 58-59.
+( K+ H+ln EG)V~+(F L)V~. (24) [5] G. C, M. Meijer, P. C. Schmafe, and K. van Zalinge, A new
curvature-corrected bandgap reference, IEEE J. Solid-State Cir-
cuits, vol. SC-17, p . 11391143, Dec. 1982.
By equating the first-order and the second-order deriva- [6] Y. P. Tsividis an c? R. W. Ulmer, A CMOS voltage reference,
tives of V,,f at TO to zero and eliminating the unknown IEEE J. Solid-State Circuits, vol. SC-13, pp. 774-778, Dec. 1978.
[7] E. A. Vittoz and O. Neyroud, A low-voltage CMOS bandgap
constants. we obtain reference, IEEE J. Solid-State Circuits, vol. SC-14, pp. 573577,
June 1979.
d% 1 d2Vg [8] R. Gregorian, G. A. Wegner, and W. E. Nicholson, Jr., An
J&f = Vg- Tz 12; integrated single-chip PCM voice codec with filters, IEEE J.
dT TOT ~ dT2 () Solid-State Circuits, vol. SC-16 p .322-333, Aug. 1981.
To [9] W. H. White, D. R. Lam ~ e, F.z Blaha, and I. A. Mack, Char-
acterization of surface c annel CCD image arrays at low light
levels, IEEEJ. Solid-State Circuits, vol. SC-9, pp. 1-14, Feb. 1974.
+VT(4fr-a)ln$++$ . (25) [10] P. R. Gray and R. G. Meyer, Ana@ris and Design of Analog
( 0 ) Integrated Circuits. New York: Wiley, 1977, pp. 256.
[11] W. Bludau, A. Onton, and W. Heinke, Temperature dependence
Therefore, the nominal voltage at TOis of the band~ap in Si, J. Appl. Phys., vol. 45, pp. 1846-1848, 1974.
,[12] Y, P. Tsividls, Accurate anafysis of temperature effects in Ic V~F
characteristics with application to bandgap reference source,; IEEE
(26) J. Solid-State Circuits, vol. SC-15, pp. 1076-1084, Dec. 1980.
~eflTo=vgo2 + ~VT~4 n (.X)
[13] J. W. Slotboom Wd H. C. DeGraaf, Measurements of bandgap
narrowing m Si bipolar tranwstors, Solid-State Electron., vol. 19,
where pp. 857-862, 1976.

dVg 1 d2Vg ~,,


,/,,.
~$:, Bang-Sup Song (S79) was born in Kunsan,
T: =1.179 V. ,,, ,$
~<;
J&2 = vg(To) ~ TTo+y~ Korea. He received the B.S. degree in electronic
. To engineering from the Seoul National University,
: Korea, in 1973, the M.S. degree in electrical
(27) ~, , engineering from the Korea Advanced Institute
+ .,%
~ ,,,,: of Science, Korea, in 1975, and the Ph.D. degree
Now Vg02 is the quadratically-extrapolated Si bandgap ... in electrical engineering from the University of
voltage at T = O K. The voltage Vg02 is closer to the Si %<, r California, Berkeley, in 1983.
From 1975 to 1978, he was a member of a
bandgap at T= O K than VgO1of (23). The theoretical value research staff in the Electronics and Communica-
....., 1
of Vg(OK) is approximately 1.179 V [12]. The bias current tions Division of the Agency for Defense Devel-
variation no longer affects (26) because it is compensated opment, Korea. During 1979, he was a graduate student at the University
of Texas, Austin. At present, he is working at Bell Laboratones, Murray
by the PTAT2 correction voltage.
Hill, NJ. His interest is in MOS integrated circuit design.
Only after the PTAT voltage is added, the intermediate
voltage at TOis
Paul R. Crav (S65M69SM76F80) was born
in Jonesbo;o; AK, on December 8,1942. He
1 d2Vg received the B.S., MS., and Ph.D. degrees from
(V,, +KVT)lTO=Vgo2+ ~~ T: - LV;. (28)
the University of Arizona, Tucson, AZ, in 1963,
To 1965, and 1969, respectively.
In 1969 he joined the Research and Develop-
Correspondingly, the magnitude of the PTAT2 voltage ment Laboratory, Fairchild Semiconductor, Palo
FV~ at TOis obtained by subtracting (28) from (26): Alto, CA, where he was involved in the applica-
tion of new technologies for analog integrated
circuits, including power integrated circuits and
1 d2Vg data conversion circuits. In 1971 he joined the
FV;ITO= ;VTO(4 n a) T:+ LV;. (29)
2 dT2 Department of Electrical Engineering and Computer Sciences, University
To
of California, Berkeley, where he is now a Professor. His research interests
during this period have included bipolar and MOS circuit design, electro-
This PTAT2 correction voltage includes the inherent Si thermal interactions in integrated circuits, device modeling, telecommuni-
bandgap curvature as well as the bias current variation. cations circuits, and analog-digital interfaces in VLSI systems. He is the
coauthor of a college textbook on anrdog integrated circuits. He has been
Other error sources neglected can be included in (29) easily corecipient of Best Paper Awards at the Intemationaf Solid-State Circuits
in the same manner as the bias current variation. No Conference, the European Solid-State Circuits Conference, and was core-
matter how many error sources are included, the final V~~f cipient of the IEEE R. W. G. Baker Prize in 1980. He served as Editor of
the IEEE JOURNALOF SOLID-STATECIRCUITSfrom 1977 through 1979,
given by (25) is independent of these instabilities as far as and as Program Chairman of the 1982 Intemationaf Sotid-State Circuits
their temperature variations are compensated properly. Conference.