6, DECEMBER 1983
A Precision CurvatureCompensated
CMOS Bandgap Reference
BANGSUP SONG, STUDENTMEMBER,
IEEE,ANDPAUL R. GRAY, FELLOW,IEEE
Ab.~tract A precision curvaturecompensated switchedcapacitor band cancellation to achieve experimental typical temperature
gap reference is described which employs a standard digital CMOS process drifts of 13.1 and 25.6 ppm/ 0C over the commercial and
and achieves temperature stability significantly lower than has previously
been reported for CMOS circuits. The theoretically achievable tempera
military temperature ranges, respectively. In the proposed
ture coefficient approaches 10 ppm/ 0 C over the commercial temperature reference, a temperaturestable voltage is developed by
range utilizing a straightforward room temperature trim procedure. Experi adding linear and quadratic temperature correction volt
mental data from monolithic prototype samples are presented which are ages to the forwardbiased diode voltage which is obtained
consistent with theoretical predictions. The experimental prototype circuit
from the substrate pnp transistor available in CMOS
occupies 3500 milsz and dissipates 12 mWwith+ 5 V powersupplies,The
proposedreferenceis helieved to be suited for use in monolithic data processes. The linear temperature correction voltage is
acquisition systems with resolutions of 10 to 12 bits. proportional to the absolute temperature (commonly called
PTAT) while the quadratic temperature correction voltage
is proportional to the absolute temperature squared
I. INTRODUCTION
(PTAT2). They are independently adjustable to set the
reference output voltage for a minimum temperature drift.
AN essential element of the analog and digital inter
face function is a voltage reference to control the
scale factor of conversion. The temperature stability of a
The offset voltage of the CMOS op amp is eliminated
using the correlateddouble sampling (CDS) technique [9].
reference source is a key factor in the accuracy of the The base current and base spreading resistance of the
native substrate pnp transistor are cancelled to the first
overall data acquisition function. Therefore, the ability to
integrate an entire data acquisition system within a single order and the amplification ratio is set by a capacitor ratio
CMOS VLSI chip is contingent upon the ability to realize a rather than a resistor ratio. Due to the cyclic behavior of
CMOS compatible voltage reference with a very low tem the offset cancellation in this technique, the output refer
perature drift. Since its introduction by Widlar [1], the ence voltage is not available at all times. However, the
bandgap referencing (BGR) technique has been widely reference can be operated synchronously with other ele
employed for implementing a voltage reference source in ments of the systems. Since the periodic offset sample and
bipolar integrated circuits. The temperature stability of the subtraction cycle effectively removes the lowfrequency l/~
bandgap reference has been continuously improved via noise component of a CMOS op amp along with its offset,
new circuit and technology innovations such as curvature the dominant noise source is the thermal noise of a CMOS
compensation and laser trim [2][5]. In CMOS technology, op amp which is designed to be on the order of 100 pV
the BGR technique has been directly applied [6][8]. How (rms) at the output in 500 kHz bandwidth.
ever, the development of a highperformance CMOS band In Sections II and III, the primary limitations in a
conventional CMOS BGR implementation and the temper
gap reference has been hindered by several limiting factors
attributable to the peculiarities of the bipolar devices avail ature curvature in bandgap references are discussed. In
Section IV, a curvaturecompensated switchedcapacitor
able in a standard CMOS process, the high offset and drift
CMOS bandgap reference is introduced. In Section V,
of CMOS op amps that make up the circuit and the
experimental results measured from monolithic prototype
inherent curvature problem in the bandgap reference.
This paper will describe one circuit implementation of a samples are presented and the problems related to the
design of pnp transistors are discussed. The theoretical
precision CMOS bandgap reference which overcomes some
analysis of BGR temperature compensation techniques is
of the drawbacks of a standard CMOS process, and em
bodies curvature compensation and differential offset included in the Appendix.
II. CONVENTIONAL
CMOS BGR IMPLEMENTATION
Manuscript received April 6, 1983; revised August 3, 1983. This work
was supported by the National Science Foundation under Grants ECS
8023872 and ECS8120012, IBM Corporation, and the MICRO Project.
One example of a conventional CMOS BGR implemen
B.S. Song is with Bell Laboratories, Murray Hill, NJ 07974, tation in an n well CMOS process is shown in Fig. 1.
P. R. Gray is with the Department of Electrical Engineering and
Computer Science, Electronics Research Laboratory, University of Cali
Transistors QI and Qz are substrate pnp transistors whose
fornia, Berkeley, CA 94720. collectors are always tied to the most negative power
Base Emitter
1
R2 R3
t P+ h+
v
0s
Vref
0
1
%
I 1, +12
V,ef=VBE+(
I+% )(AVBE+Vo~) (a)
I
[ ~ Q, Qz
y AV,E +?
L L
v Ss
Fig. 1 Example of a conventionalCMOS bandgap reference. rb/A
I
supply because, in an n well CMOS process, the p+ &
diffusion in the nwell, the nwell itself and the p I I
substrate form a vertical pnp structure as shown in Fig. (b)
2(a). Therefore, it is not possible to sense the collector
Fig. 2, (a) Substrate pnp transistor profile. (b) Nonideal parameters in
current directly as in the bipolar bandgap reference so as the PTAT correction voltage generation circuit.
to reduce the error due to the finite current gain [3], [4]. In
a p well process, a dual circuit incorporating npn tran
sistors would be used. While many other circuit implemen this circuit is the emitter current. The third term results
tations are possible, this circuit appears to be as good as from the voltage drop in the finite series base resistance.
any. Therefore, individual error sources will be described The difference between the two emitterbase voltages is
one by one for this circuit in the rest of this section. All given by
resistors are the p diffusion resistor in the n well and the
CMOS op amp is assumed to have an infinite gain with the 1
offset voltage of VO,.This assumption is justified because
AVBE = V~ln A + V~ln $ + V~ln ~
l+Fl
CMOS op amps usually have enough gains such that the 1 rlbid
error due to finitegain effects is negligible for this applica 1+T2
tion.
Assuming that transistor Q1 in Fig. 1 has an area that is (3)
larger by a factor A than transistor Qz, and both are in the
where 12is the emitter current of transistor Qz and B2is the
forward active region, the output voltage of the reference is
current gain of transistor Qz. If the bipolar transistors used
given by
to implement the reference are ideal in the sense that they
have infinite current gain and zero base resistance, and if
~ef=vBE+
(1
1+:
1
(AVBE+V&) (1) the emitter currents of the transistors are in fact equal,
then only the first terms in (2) and (3) are nonzero.
where VBE is the emitterbase voltage of transistor Q1, However, because of the relatively poor performance of
AVBEis the difference between the emitterbase voltages of CMOScompatible devices, these terms can strongly in
transistors Q1 and Q2, and VO,is the input offset voltage of fluence the performance of the reference. The presence of
the operational amplifier. The value of this expression is the operational amplifier offset voltage in the output, mul
influenced by the nonidealities of the bipolar transistors as tiplied by the gain factor (1+ R ~/R1), which is typically
illustrated in Fig. 2(b). If these are taken into account, the on the order of 10, is also an important degradation.
transistor emitterbase voltage is given by Finally, the variation of the bias currents 11 and Iz with
temperature must be carefully considered. In the following
1 rb11
VBE= FJn # + F~ln~ + (2) subsections, the effects of these nonidealities are examined
S1 A& in more detail.
l+Fl
A. Operational Amplifier Offset
where VT is the thermal voltage kT/q, 11 is the emitter
current of transistor Q1, Isl is the saturation current of The operational amplifier offset is the biggest error
transistor Ql, & is the current gain of transistor Q1 and rb source that causes the nonreproducibility in the output
is the effective series base resistance of Qz. The second voltage temperature coefficient. Normally, a bandgap ref
term in this expression results from the fact that while erence is trimmed to an output voltage which is prede
the collector current is a welldefined function of the termined to give a nearzero temperature coefficient of the
emitterbase voltage, the current sensed and controlled by output. Large, nonPTAT components in the output due to
636 CIRCUITS,VOL.SC18,NO. 6, DECEMRER
IEEEJOURNALOF SOLIDSTATE 1983
the op amp offset cause the trimming operation to give an portion can be compensated by simply changing the target
erroneous result. If we assume the offset voltage VO,is trim value of the output voltage. For example, (6) can be
independent of temperature, the resulting temperature used to show that a 1000 ppm/ 0C resistor TC would
coefficient error due to a 5 mV VO$,for example, is result in a 21 ppm/ 0C reference output TC, which
approximately could be removed by simply raising the output voltage trim
target by approximately 8 mV. However, cancellation of
1++ Vo, PTAT2 term precisely requires curvature compensation
(1 1 10 X5mV discussed later.
TC error =
~,f TO = 1.26 VX300K
C. Other Effects
=132 ppm/ C. (4)
The effects of various nonidealities, including base resis
That is, a temperature coefficient on the order of 132
tance, ~ mismatch, @ variations with temperature, and ~
ppm/ 0C will result in the reference output temperature variations with collect current can be evaluated with the
coefficient from a 5 mV temperatureindependent offset use of (l), (2), and (3). Which of these effects is the most
voltage in the operational amplifier if the reference is important in a given circuit application is strongly depen
trimmed assuming the offset is zero. This offset error dent on the nature of the bipolar transistors in the particu
contribution can be reduced by making AVBEbigger, in lar technology used. If the well (base) doping is particularly
effect decreasing the gain factor (1+ R2 /R1) as implied by light, as is often the case, then the intrinsic base resistance
(l). One way to achieve this is to obtain AVBEby taking the effect, represented by the last term in (3), may well be the
difference of two cascaded transistor strings discussed later most important. The temperature coefficient in the output
in Section IV. In this work, however, offset cancellation due to this term is given by
technique is employed to further reduce this error while the
cascading scheme is used for the PTAT current generation.
where TOis the reference temperature, usually room tem III. CURVATURE IN BANDGAP REFERENCES
perature. Note that the first term is the V~~ variation that
For a bandgap reference which is ideal in the sense that
results when there is no resistor temperature coefficient,
the operational amplifier is ideal, the bipolar transistors
and the second is that which results when a temperature
have infinite current gain, zero intrinsic base resistance,
coefficient is present, Further insight can be obtained by
and have perfect exponential junction relationships, and
expanding this second term as a Taylor series in tempera
the bandgap of silicon varies linearly with temperature, the
ture about TO,and neglecting higher order terms:
output voltage is typically given by [10]
BE = BEl,dezd T
.;$$ ~(TTo)VT&
0
$ $TTO)2
.
... . (6)
V,c~=VgO+V~(4na)
()
l+ln$
0
(8)
Emi!r
with T2, as well as linearly with temperature [11], [12]. This
higher order temperature variation adds a curvature term,
increasing the effective TC even for optimally adjusted
references. These effects together combine to give a best
TO T To T T. T
achievable TC of about 25 ppm/ 0C for a temperature
range of 55 C to 125 C. Fig. 3. Curvaturecompensationconcept (not seated).
Several approaches have been suggested for curvature
correction. If the quantity (4 n a) in (8) could be made
I Temp Indep [Tll I ID
zero, then there would be no curvature other than the
Current
curvature of the silicon bandgap. This could be achieved I Generator ,bl I
for example by using a very strongly temperaturedepen
dent bias current or by linearizing V~~directly [5]. Several I
authors have proposed simply adding in higher order tem
peraturedependent terms in the output to cancel the
PTAT2 term of the output voltage variation [4]. This is the
approach used in this paper to be described in the next
section.
IV. PRECISION SWITCHEDCAPACITOR CMOS BGR Fig. 4, Overall schematic of the curvaturecompensatedswitchedcapa
citor CMOS bandgap reference.
TECHNIQUE
In order to implement voltage references in CMOS tech block is determined by the capacitor ratio C2/Cl. The
nology which have performance approaching that achiev current 10 is temperatureindependent (TI) while 1~ is
able in bipolar technology, special steps must be taken to PTAT. The bias current 1~ is also TI.
counteract the relatively poor performance of CMOS op If the effects of the base current and the base spreading
amps and CMOS compatible bipolar transistors. In addi resistance are neglected, the reference output V,~fis given
tion, curvature compensation, already widely applied in by
bipolar references, must be incorporated. In this section,
the implementation of the techniques in CMOS technology (9)
is described.
where
A. Curvature Compensation
Voo
Vss
Fig 5. PTAT and TI current generators for the bias currents IT and 10.
s,
I
M,e
I I
[ M6 M,
Vf I
iiiK5W
2FF+P+ v Ss
upper part Iv& Mg is. The classA source follower stages For the process used here, the magnitude of the extrinsic
formed by transistors Al10 M13 are added to meet the compensation resistance is about one quarter of the mea
capacitor driving capability. In the offsetstorage modes, sured intrinsic base resistance of pnp transistors with the
each op amp is stabilized by connecting a frequency com same geometry.
640 CIRCUITS,VOL.SC18,NO. 6, DECEMBER
IEEEJOURNALOF SOLIDSTATE 1983
~. i J
(a) (b)
Fig. 8. Basecurrent cancellationschemes.(a) lB returning. (b) ZBrepli
cation.
rbi
Intrinsic Base Resise
h
+
,.
~
. INTRINSIC RESISTANCE

p._.__J ?~? 1
+
%iw = %,b
= rbl rb,lA COMPENSATION RESISTANCE
(a) (b)
Fig. 9. Base resistance cancellation. (a) Extrinsic compensation resis
tance R .Omp. (b) llifference between intrinsic base resistance and
extrinsic compensation resistance.
V. EXPERIMENTAND DISCUSSIONS
TABLE I
STATISTICS
OFMEASURED
TEMPERATURE COEFFICIENTS
OF7 SAMPLES
(ppm C)
Standard
oto70c: Mean Deviation Minimum Maximum
Type I 105 43 42 167
Type II 22.3 10.8 11.1 42
T~e III 13.1 7.1 5.6 25.7
55 to 125 C:
TWe I 185 56.5 107 273
Type II 35.1 18.8 17.6 66.7
Type III 25.6 10.5 12.1 39.9
0 (a)
AVre, ~p: 1 \
[mV) I
I I i t
5 Type I
1 I I L I I I I I I I
50 0
TEMPERATURE
50
(C )
UB=r (b)
Fig. 13. Substrate pnp transistor. (a) A unit cell. (b) Drawn dime]n
sions of a unit cell (~m).
TABLE II
PERFORMANCE
SUMMARY
V,ef 1.192V*lmVat25 C current range. The current gain ~ is also relatively constant
TC SeeTable I
Power 12 mW with + 5 V supply
within this range. However, in the emitter current range
Load 100 pF capacitor over 100 p A, the base crowding effect is severe. Also, in
Cycle time 5 ps the emitter current range below 1 PA, the current gain ~
+ PSRR 50 dB (de) decreases due to space charge recombination in the
PSRR 60 dB (de) emitterbase junction. The unit cells of Fig. 13 were con
Clock RR 75 dB
nected in parallel to obtain a multipleemitter device. The
Output noise 400 pV (500 kHz)
current gain /3 is minimum at 550 C and the average
value at room temperature is 175. Temperature data for the
pensation, a factor of 2 further improvement was obtained. pnp transistors and p+ diffused resistors in the nwell in
Fig. 12 compares graphically those three types of optim the particular technology used here are listed in Table III.
allycompensated bandgap references. The experimental The temperature coefficients of diffused resistors match
results are summarized in Table II. To improve the power each other within 1.2 percent.
supply rejection ratio (PSRR), the base of all pnp transis One potential problem in the use of the substrate pnp
tors should be biased at a constant voltage relative to the transistor is the fact that the dc collector current flows into
negative supply line, Otherwise, the base width modulation the substrake. If this current gives rise to a large enough
(Early effect) will limit the PSRR of the reference, ohmic drop in the substrate, it could initiate latchup. To
The critical aspect of the design is the substrate pnp minimize the likelihood of this, each n well (base) was
transistor because the n well in CMOS processes usually surrounded by the p+ diffusion (collector) as shown in Fig.
has a relatively high resistivity. In order to minimize the 13. No latchup was observed during experimental measure
intrinsic base spreading resistance, the base contact sur ments even under transient conditions.
rounds the emitter junction as shown in Fig. 13, The
emitter junction and the base contact plug are separated by
9 pm. By the surrounding base, the intrinsic base resistance VI. CONCLUSION
is reduced by a factor of 6 when compared to the parallel
contact of emitter and base. For the process used here, the A precision curvaturecompensated switchedcapacitor
estimated rb of this geometry is about 1.5 kfl. With this CMOS bandgap reference is reported whose monolithic
geometry, the observed emitter area reduction due to the prototype exhibits average temperature drifts of 13.1 and
base crowding is insignificant over the 1 to 100 PA emitter 25.6 ppm/ 0 C over the commercial and military tempera
CIRCUJTS,VOL.SC18,NO. 6, DECEMBER
IEEEJOURNALOF SOLIDSTATE 1983
TABLE III
TEMPERATUJW AND pnp TRANSISTORS
DATAOFDIFFUSEDFWSISTORS
(55 to125c)
Standard
Diffused Resistors: Mean Deviation Minimum Maumum
Sheet resistance (Q/square) 68.9 3.1 64.6 72.1
TCor R* 886 27.9 849 917
Ratio of 6R /R** 5.952 0.02 5.9304 5.9794
TC of 6R/R* 10.6 2,2 8.9 13.6
pnp Transistors:
Current gain /? at IE = 30 pA 175 83 91 273
TCoffl* 6503 872 5471 7792
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