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Homework rules:
Homework assignments are to be completed individually.
Informal consultation with other students from the class is permitted and even
encouraged, but the copying of anothers work or any portion of it is strictly forbidden.
Any deviations from the above rules will be treated strictly per university guidelines for
student conduct.
Homework solutions should document the students thought process by including all
necessary steps as well as textual comments. Grading will be based primarily on a
demonstration of ability to provide the correct steps toward a solution rather then the
solution itself.
LATE HOMEWORK can receive a maximum of 75 pts. No homework will be accepted
after solutions are posted.
4) Double click on the Repeating Sequency in your model to open the parameter dialog for
this block.
5) Change the time values and output values to match what is shown below.
6) Under Simulink, select Ports & Subsystems. Place a Subsystem into your model.
7) Rename your Subsystem to be SVPWM.
8) Double click on the Subsystem you just added to open it. Rename the Inport to Angle
and delete the Outport.
10) Double click on the Trigonometric Function block to open the parameter dialog.
11) Change the function to sincos.
12) Connect the output of the Inport block to the input of the Trig. Function block.
13) Under Math Operations, add a Gain block to your model.
14) Under Signal Routing add a From block to your model.
15) Copy and connect the Gain and From blocks as shown below. Change the Gain value to
55 (from peak phase voltage specification).
Step 2: Determining the Sector Number
3) Change the Output data type of the Compare to Constant block to uint8.
4) Add a Sum block to the subsystem.
5) Change the List of signs of the Sum block as shown below.
6) Add a Constant block and change the Output data type to uint8.
7) Copy and paste the blocks and change the parameters as needed to create the subsystem
as shown below. The values for the Compare to Constant values are:
pi/3, 2*pi/3, pi, 4*pi/3, and 5*pi/3
15) In each Sector subsystem, model the appropriate equation from the SVPWM notes in
class.
Example: Modeling SVPWM Duty Cycle Calculations (Sector 1)
1) To program equations, the easiest way is to type the equation into a Fcn block.
3) For this example, u(1) is V_alpha, u(2) is V_beta, and u(3) is 2/3*V_dc.
4) In Sector 1, the two non-zero Switch states being used are [1 0 0] and [1 1 0]. t1/T
corresponds to [1 0 0], and t2/T corresponds to [1 1 0]. The remaining normalized time
(t0/T) is 1 t1/T t2/T. Half of this time will be spent in state [0 0 0], and half will be
spent in [1 1 1]. Therefore:
The duty cycle for phase A is t1/T + t2/T + (1/2)*(t0/T).
The duty cycle for phase B is t2/T + (1/2)*(t0/T).
The duty cycle for phase C is (1/2)*(t0/T).
The model looks like this.
5) Since the duty cycle outputs are being merged, a Signal Conversion block is required for
the top output. The reason for this is that all input signals to a Merge block must only be
connected to that Merge block. The Signal Conversion block is under Signal Attributes.
6) Use the equations for each individual Sector and the same logic for determining the duty
cycle of each phase.
7) Go to the top level of your model. Right click on your SVPWM subsystem and select
Block Parameters.
8) Check the box to Treat as atomic unit. Change the Sample time to 1/5000 (switching
period).
Step 4: Creating the Gate Signals
3) Open the GateSignals subsystem. Copy and paste the Inports and Outports and rename
them as shown below.
4) To create the gate signals, the compare value with respect to the duty cycle is required.
The compare value is 1 Duty Cycle.
5) If the carrier wave is greater than the compare value, the top switch of that phase will be
on. If the carrier wave is less than the compare value, the bottom switch of that phase
will be on.
6) Repeat this for all 3 phases as shown below.
9) Connect the output of the SVPWM subsystem to the inputs of the GateSignals subsystem.
10) Replace the connections to the gates for the MOSFETs with the outputs of the
GateSignals subsystem.