Sie sind auf Seite 1von 40

Not logged in Talk Contributions Create account Log in

Article Talk Read Edit More Search

Flip-flop (electronics)
From Wikipedia, the free encyclopedia

Main page This article includes a list of references, but its sources remain unclear
because it has insufficient inline citations. Please help to improve this
Featured content
Current events
article by introducing more precise citations. (May 2013) (Learn how and when
Random article to remove this template message)
Donate to Wikipedia
Wikipedia store
In electronics, a flip-flop or latch is a circuit that has two stable states
and can be used to store state information. A flip-flop is a bistable
multivibrator. The circuit can be made to change state by signals
applied to one or more control inputs and will have one or two outputs. It
About Wikipedia
Community portal is the basic storage element in sequential logic. Flip-flops and latches
Recent changes are fundamental building blocks of digital electronics systems used in
Contact page computers, communications, and many other types of systems.
Tools Flip-flops and latches are used as data storage elements. A flip-flop
What links here stores a single bit (binary digit) of data; one of its two states represents
Related changes a "one" and the other represents a "zero". Such data storage can be
Upload file An animated interactive SR latch
used for storage of state, and such a circuit is described as sequential (R1, R2 = 1 k R3, R4 = 10 k).
Special pages
Permanent link logic. When used in a finite-state machine, the output and next state
Page information depend not only on its current input, but also on its current state (and
Wikidata item hence, previous inputs). It can also be used for counting of pulses, and
Cite this page for synchronizing variably-timed input signals to some reference timing
Print/export signal.
Create a book Flip-flops can be either simple (transparent or opaque) or clocked
Download as PDF
(synchronous or edge-triggered). Although the term flip-flop has
Printable version
historically referred generically to both simple and clocked circuits, in
In other projects modern usage it is common to reserve the term flip-flop exclusively for
Wikimedia Commons discussing clocked circuits; the simple ones are commonly called An SR latch, constructed from a pair
Wikiversity of cross-coupled NOR gates.
Using this terminology, a latch is level-sensitive, whereas a flip-flop is

Azrbaycanca edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes
on a single type (positive going or negative going) of clock edge.

Contents [hide]
Bosanski 1 History
Catal 2 Implementation
etina 3 Flip-flop types
Dansk 3.1 Simple set-reset latches
Deutsch 3.1.1 SR NOR latch
3.1.2 SR NAND latch

3.1.3 SR AND-OR latch
3.1.4 JK latch
Franais 3.2 Gated latches and conditional transparency
3.2.1 Gated SR latch
3.2.2 Gated D latch
Hrvatski 3.2.3 Earle latch
Bahasa Indonesia 3.3 D flip-flop
Italiano 3.3.1 Classical positive-edge-triggered D flip-flop
3.3.2 Masterslave edge-triggered D flip-flop
3.3.3 Edge-triggered dynamic D storage element
3.4 T flip-flop
3.5 JK flip-flop
4 Timing considerations
4.1 Timing parameters
Nederlands 4.2 Metastability
4.3 Propagation delay
Norsk bokml 5 Generalizations
Polski 6 See also
7 References

Simple English
8 External links
/ srpski History [ edit ]
Suomi The first electronic flip-flop was invented in 1918 by the British physicists
William Eccles and F. W. Jordan.[3][4] It was initially called the Eccles

Trke Jordan trigger circuit and consisted of two active elements (vacuum
tubes).[5] The design was used in the 1943 British Colossus codebreaking
Ting Vit computer[6] and such circuits and their transistorized versions were
common in computers even after the introduction of integrated circuits,
Edit links
though flip-flops made from logic gates are also common now.[7][8] Early
flip-flops were known variously as trigger circuits or multivibrators.
According to P. L. Lindley, an engineer at the US Jet Propulsion
Laboratory, the flip-flop types detailed below (RS, D, T, JK) were first
discussed in a 1954 UCLA course on computer design by Montgomery
Phister, and then appeared in his book Logical Design of Digital
Computers.[9][10] Lindley was at the time working at Hughes Aircraft under
Eldred Nelson, who had coined the term JK for a flip-flop which changed
states when both inputs were on (a logical "one"). The other names were
coined by Phister. They differ slightly from some of the definitions given Flip-flop schematics from the
Eccles and Jordan patent filed
below. Lindley explains that he heard the story of the JK flip-flop from 1918, one drawn as a cascade of
Eldred Nelson, who is responsible for coining the term while working at amplifiers with a positive feedback
Hughes Aircraft. Flip-flops in use at Hughes at the time were all of the type path, and the other as a symmetric
cross-coupled pair
that came to be known as J-K. In designing a logical system, Nelson
assigned letters to flip-flop inputs as follows: #1: A & B, #2: C & D, #3: E &
F, #4: G & H, #5: J & K. Nelson used the notations "j-input" and "k-input" in a patent application filed in 1953.[11]

Implementation [ edit ]
Flip-flops can be either simple (transparent or asynchronous) or clocked
(synchronous); the transparent ones are commonly called latches.[1] The
word latch is mainly used for storage elements, while clocked devices are
described as flip-flops.[2]
Simple flip-flops can be built around a pair of cross-coupled inverting
elements: vacuum tubes, bipolar transistors, field effect transistors,
inverters, and inverting logic gates have all been used in practical circuits.
Clocked devices are specially designed for synchronous systems; such A traditional flip-flop circuit
devices ignore their inputs except at the transition of a dedicated clock based on bipolar junction
signal (known as clocking, pulsing, or strobing). Clocking causes the flip-
flop either to change or to retain its output signal based upon the values of
the input signals at the transition. Some flip-flops change output on the rising edge of the clock, others on the
falling edge.
Since the elementary amplifying stages are inverting, two stages can be connected in succession (as a
cascade) to form the needed non-inverting amplifier. In this configuration, each amplifier may be considered as
an active inverting feedback network for the other inverting amplifier. Thus the two stages are connected in a
non-inverting loop although the circuit diagram is usually drawn as a symmetric cross-coupled pair (both the
drawings are initially introduced in the EcclesJordan patent).

Flip-flop types [ edit ]

Flip-flops can be divided into common types: the SR ("set-reset"), D ("data" or "delay"[12]), T ("toggle"), and JK
types are the common ones. The behavior of a particular type can be described by what is termed the
characteristic equation, which derives the "next" (i.e., after the next clock pulse) output, Qnext in terms of the
input signal(s) and/or the current output, .
Simple set-reset latches [ edit ]
SR NOR latch [ edit ]
When using static gates as building blocks, the most fundamental latch
is the simple SR latch, where S and R stand for set and reset. It can be
constructed from a pair of cross-coupled NOR logic gates. The stored
bit is present on the output marked Q.
While the R and S inputs are both low, feedback maintains the Q and Q
outputs in a constant state, with Q the complement of Q. If S (Set) is
pulsed high while R (Reset) is held low, then the Q output is forced high,
and stays high when S returns to low; similarly, if R is pulsed high while An animation of a SR latch,
S is held low, then the Q output is forced low, and stays low when R constructed from a pair of cross-
returns to low. coupled NOR gates. Red and black
mean logical '1' and '0', respectively.
SR latch operation[13]
Characteristic table Excitation table
S R Qnext Action Q Qnext S R
0 0 Q hold state 0 0 0 X
0 1 0 reset 0 1 1 0
1 0 1 set 1 0 0 1
1 1 X not allowed 1 1 X 0

Note: X means don't care, that is, either 0 or 1 is a valid value. An animated SR latch. Black and
white mean logical '1' and '0',
The R = S = 1 combination is called a restricted combination or a respectively.
forbidden state because, as both NOR gates then output zeros, it (A) S = 1, R = 0: set
(B) S = 0, R = 0: hold
breaks the logical equation Q = not Q. The combination is also
(C) S = 0, R = 1: reset
inappropriate in circuits where both inputs may go low simultaneously (D) S = 1, R = 1: not allowed
(i.e. a transition from restricted to keep). The output would lock at either The restricted combination (D) leads to
1 or 0 depending on the propagation time relations between the gates an unstable state.
(a race condition).
To overcome the restricted combination, one can add gates to the inputs that would convert (S,R) = (1,1) to
one of the non-restricted combinations. That can be:
Q = 1 (1,0) referred to as an S (dominated)-latch
Q = 0 (0,1) referred to as an R (dominated)-latch
This is done in nearly every programmable logic controller.
Keep state (0,0) referred to as an E-latch
Alternatively, the restricted combination can be made to toggle the output. The result is the JK latch.
Characteristic: Q+ = R'Q + R'S or Q+ = R'Q + S.[14]

SR NAND latch [ edit ]

This is an alternate model of the simple SR latch which is built with
NAND logic gates. Set and reset now become active low signals,
denoted S and R respectively. Otherwise, operation is identical to that
of the SR latch. Historically, SR-latches have been predominant despite
the notational inconvenience of active-low inputs.[citation needed]

SR latch operation An SR latch

S R Action
0 0 Not allowed
0 1 Q=1
Symbol for an
1 0 Q=0 SR NAND latch
1 1 No change

SR AND-OR latch [ edit ]

From the teaching point of view, SR latches realised as a pair of cross-
coupled components (transistors, gates, tubes, etc.) are rather hard to
understand for beginners. A didactically easier to understand model
uses a feedback loop instead of the cross-coupling. The following is an
SR latch built with an AND gate with one inverted input and an OR gate.
An SR AND-OR latch. Light green
SR AND-OR latch operation means logical '1' and dark green
means logical '0'. The latch is currently
S R Action in hold mode (no change).
0 0 No change
1 0 Q=1
X 1 Q=0

JK latch [ edit ]
The JK latch is much less frequently used than the JK flip-flop. The JK latch follows the following state table:

JK latch truth table

J K Qnext Comment
0 0 Q No change
0 1 0 Reset
1 0 1 Set
1 1 Q Toggle

Hence, the JK latch is an SR latch that is made to toggle its output (oscillate between 0 and 1) when passed the
input combination of 11.[15] Unlike the JK flip-flop, the 11 input combination for the JK latch is not very useful
because there is no clock that directs toggling.[16]

Gated latches and conditional transparency [ edit ]

Latches are designed to be transparent. That is, input signal changes cause immediate changes in output;
when several transparent latches follow each other, using the same enable signal, signals can propagate
through all of them at once. Alternatively, additional logic can be added to a simple transparent latch to make it
non-transparent or opaque when another input (an "enable" input) is not asserted. By following a transparent-
high latch with a transparent-low (or opaque-high) latch, a masterslave flip-flop is implemented.

Gated SR latch [ edit ]

A synchronous SR latch (sometimes clocked SR flip-flop)
can be made by adding a second level of NAND gates to
the inverted SR latch (or a second level of AND gates to
the direct SR latch). The extra NAND gates further invert
the inputs so the simple SR latch becomes a gated SR
latch (and a simple SR latch would transform into a gated
SR latch with inverted enable).
A gated SR latch circuit diagram constructed from
With E high (enable true), the signals can pass through the NOR gates.
input gates to the encapsulated latch; all signal
combinations except for (0,0) = hold then immediately
reproduce on the (Q,Q) output, i.e. the latch is transparent.
With E low (enable false) the latch is closed (opaque) and remains in the state it was left the last time E was
The enable input is sometimes a clock signal, but more often a read or write strobe.

Gated SR latch operation

E/C Action
0 No action (keep state)
1 The same as non-clocked SR latch Symbol for a
gated SR latch
Gated D latch [ edit ]
This latch exploits the fact that, in the two active input
combinations (01 and 10) of a gated SR latch, R is the
complement of S. The input NAND stage converts the two D
input states (0 and 1) to these two input combinations for
the next SR latch by inverting the data input signal. The low
state of the enable signal produces the inactive "11"
combination. Thus a gated D-latch may be considered as a
one-input synchronous SR latch. This configuration A gated D latch based on an SR NAND latch
prevents application of the restricted input combination. It is
also known as transparent latch, data latch, or simply gated
latch. It has a data input and an enable signal (sometimes
named clock, or control). The word transparent comes from
the fact that, when the enable input is on, the signal
propagates directly through the circuit, from the input D to
the output Q.
Transparent latches are typically used as I/O ports or in
asynchronous systems, or in synchronous two-phase A gated D latch based on an SR NOR latch
systems (synchronous systems that use a two-phase
clock), where two latches operating on different clock
phases prevent data transparency as in a masterslave
Latches are available as integrated circuits, usually with
multiple latches per chip. For example, 74HC75 is a
quadruple transparent latch in the 7400 series.

An animated gated D latch.

(A) D = 1, E = 1: set
(B) D = 1, E = 0: hold
(C) D = 0, E = 0: hold
(D) D = 0, E = 1: reset

Gated D latch truth table

E/C D Q Q Comment
0 X Qprev Qprev
1 0 0 1 Reset Symbol for a
gated D latch
1 1 1 0 Set

A gated D latch in pass transistor logic, similar to

The truth table shows that when the enable/clock input is 0, the ones in the CD4042 or the CD74HC75 integrated
the D input has no effect on the output. When E/C is high, circuits.
the output equals D.

Earle latch [ edit ]

The classic gated latch designs have some undesirable
characteristics.[17] They require double-rail logic or an inverter. The
input-to-output propagation may take up to three gate delays. The
input-to-output propagation is not constant some outputs take
two gate delays while others take three.
Designers looked for alternatives.[18] A successful alternative is the
Earle latch. It requires only a single data input, and its output takes
a constant two gate delays. In addition, the two gate levels of the
Earle latch can, in some cases, be merged with the last two gate
levels of the circuits driving the latch because many common Earle latch uses complementary enable
computational circuits have an OR layer followed by an AND layer inputs: enable active low (E_L) and enable
active high (E_H)
as their last two levels. Merging the latch function can implement
the latch with no additional gate delays.[17] The merge is commonly
exploited in the design of pipelined computers, and, in
fact, was originally developed by J. G. Earle to be used
in the IBM System/360 Model 91 for that purpose.[19]
The Earle latch is hazard free.[20] If the middle NAND
gate is omitted, then one gets the polarity hold latch,
which is commonly used because it demands less
logic.[20][21] However, it is susceptible to logic hazard.
Intentionally skewing the clock signal can avoid the

An animated Earle latch.

(A) D = 1, E_H = 1: set
(B) D = 0, E_H = 1: reset
(C) D = 1, E_H = 0: hold
(D) D = 1, E_H = 1: set

D flip-flop [ edit ]
The D ip-op is widely used. It is also known as a "data" or "delay" flip-flop.
The D flip-flop captures the value of the D-input at a definite portion of the clock cycle
(such as the rising edge of the clock). That captured value becomes the Q output. At other
times, the output Q does not change.[22][23] The D flip-flop can be viewed as a memory cell,
a zero-order hold, or a delay line.[24]
Truth table: D flip-flop symbol

Clock D Qnext
Rising edge 0 0
Rising edge 1 1
Non-Rising X Q

('X' denotes a Don't care condition, meaning the signal is irrelevant)

Most D-type flip-flops in ICs have the capability to be forced to the set or reset state (which ignores the D and
clock inputs), much like an SR flip-flop. Usually, the illegal S = R = 1 condition is resolved in D-type flip-flops. By
setting S = R = 0, the flip-flop can be used as described above. Here is the truth table for the others S and R
possible configurations:

Inputs Outputs
S R D > Q Q'
0 1 X X 0 1
1 0 X X 1 0
1 1 X X 1 1

These flip-flops are very useful, as they form the basis for shift
registers, which are an essential part of many electronic devices. The
advantage of the D flip-flop over the D-type "transparent latch" is that
the signal on the D input pin is captured the moment the flip-flop is
4-bit serial-in, parallel-out (SIPO)
clocked, and subsequent changes on the D input will be ignored until shift register
the next clock event. An exception is that some flip-flops have a "reset"
signal input, which will reset Q (to zero), and may be either
asynchronous or synchronous with the clock.
The above circuit shifts the contents of the register to the right, one bit position on each active transition of the
clock. The input X is shifted into the leftmost bit position.
Classical positive-edge-triggered D flip-flop [ edit ]
This circuit[25] consists of two stages implemented by SR NAND latches.
The input stage (the two latches on the left) processes the clock and
data signals to ensure correct input signals for the output stage (the
single latch on the right). If the clock is low, both the output signals of
the input stage are high regardless of the data input; the output latch is
unaffected and it stores the previous state. When the clock signal
changes from low to high, only one of the output voltages (depending
on the data signal) goes low and sets/resets the output latch: if D = 0,
the lower output becomes low; if D = 1, the upper output becomes low. If
the clock signal continues staying high, the outputs keep their states
regardless of the data input and force the output latch to stay in the
corresponding state as the input logical zero (of the output stage) A positive-edge-triggered D flip-flop
remains active while the clock is high. Hence the role of the output latch
is to store the data only while the clock is low.
The circuit is closely related to the gated D latch as both the circuits convert the two D input states (0 and 1) to
two input combinations (01 and 10) for the output SR latch by inverting the data input signal (both the circuits
split the single D signal in two complementary S and R signals). The difference is that in the gated D latch
simple NAND logical gates are used while in the positive-edge-triggered D flip-flop SR NAND latches are used
for this purpose. The role of these latches is to "lock" the active output producing low voltage (a logical zero);
thus the positive-edge-triggered D flip-flop can also be thought of as a gated D latch with latched input gates.

Masterslave edge-triggered D flip-flop [ edit ]

A masterslave D flip-flop is created by connecting two
gated D latches in series, and inverting the enable input to
one of them. It is called masterslave because the second
latch in the series only changes in response to a change in
the first (master) latch.
For a positive-edge triggered masterslave D flip-flop,
A masterslave D flip-flop. It responds on the
when the clock signal is low (logical 0) the "enable" seen by falling edge of the enable input (usually a clock)
the first or "master" D latch (the inverted clock signal) is
high (logical 1). This allows the "master" latch to store the
input value when the clock signal transitions from low to
high. As the clock signal goes high (0 to 1) the inverted
"enable" of the first latch goes low (1 to 0) and the value
seen at the input to the master latch is "locked". Nearly
simultaneously, the twice inverted "enable" of the second An implementation of a masterslave D flip-flop
or "slave" D latch transitions from low to high (0 to 1) with that is triggered on the rising edge of the clock
the clock signal. This allows the signal captured at the
rising edge of the clock by the now "locked" master latch to pass through the "slave" latch. When the clock
signal returns to low (1 to 0), the output of the "slave" latch is "locked", and the value seen at the last rising
edge of the clock is held while the "master" latch begins to accept new values in preparation for the next rising
clock edge.
By removing the leftmost inverter in the circuit at side, a D-type flip-flop that strobes on the falling edge of a
clock signal can be obtained. This has a truth table like this:

D Q > Qnext
0 X Falling 0
1 X Falling 1

Edge-triggered dynamic D storage element [ edit ]

An efficient functional alternative to a D flip-flop can be made with dynamic circuits (where information is stored
in a capacitance) as long as it is clocked often enough; while not a true flip-flop, it is still called a flip-flop for its
functional role. While the masterslave D element is triggered on the edge of a clock, its components are each
triggered by clock levels. The "edge-triggered D flip-flop", as it is called even though it is not a true flip-flop,
does not have the masterslave properties.
Edge-triggered D flip-flops are often implemented in integrated high-speed operations using dynamic logic. This
means that the digital output is stored on parasitic device
capacitance while the device is not transitioning. This
design of dynamic flip flops also enables simple resetting
since the reset operation can be performed by simply
discharging one or more internal nodes. A common
dynamic flip-flop variety is the true single-phase clock
(TSPC) type which performs the flip-flop operation with little
power and at high speeds. However, dynamic flip-flops will
typically not work at static or low clock speeds: given
A CMOS IC implementation of a "true single-phase
enough time, leakage paths may discharge the parasitic edge-triggered flip-flop with reset"
capacitance enough to cause the flip-flop to enter invalid

T flip-flop [ edit ]
If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is
strobed. If the T input is low, the flip-flop holds the previous value. This behavior is
described by the characteristic equation:
(expanding the XOR operator)
and can be described in a truth table: A circuit symbol
for a T-type flip-
T flip-flop operation[26] flop
Characteristic table Excitation table
Comment Comment
0 0 0 hold state (no clk) 0 0 0 No change
0 1 1 hold state (no clk) 1 1 0 No change
1 0 1 toggle 0 1 1 Complement
1 1 0 toggle 1 0 1 Complement

When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock frequency is 4 MHz,
the output frequency obtained from the flip-flop will be 2 MHz. This "divide by" feature has application in various
types of digital counters. A T flip-flop can also be built using a JK flip-flop (J & K pins are connected together
and act as T) or a D flip-flop (T input XOR Qprevious drives the D input).

JK flip-flop [ edit ]
The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting
the J = K = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K
= 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the
flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its
output to the logical complement of its current value. Setting J = K = 0 maintains the current
state. To synthesize a D flip-flop, simply set K equal to the complement of J. Similarly, to A circuit symbol
for a positive-
synthesize a T flip-flop, set K equal to J. The JK flip-flop is therefore a universal flip-flop,
because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop. JK flip-flop
The characteristic equation of the JK flip-flop is:

and the corresponding truth table is:

JK flip-flop operation[26]
Characteristic table Excitation table A JK flip-flop made
J K Comment Qnext Q Qnext Comment J K of NAND gates

0 0 hold state Q 0 0 No Change 0 X

0 1 reset 0 0 1 Set 1 X
1 0 set 1 1 0 Reset X 1
1 1 toggle Q 1 1 No Change X 0

JK flip-flop timing diagram

Timing considerations [ edit ]
Timing parameters [ edit ]
The input must be held steady in a period around the rising edge of the
clock known as the aperture. Imagine taking a picture of a frog on a lily-
pad.[27] Suppose the frog then jumps into the water. If you take a picture
of the frog as it jumps into the water, you will get a blurry picture of the
frog jumping into the waterit's not clear which state the frog was in.
But if you take a picture while the frog sits steadily on the pad (or is
steadily in the water), you will get a clear picture. In the same way, the
input to a flip-flop must be held steady during the aperture of the flip-
Setup time is the minimum amount of time the data input should be
held steady before the clock event, so that the data is reliably sampled Flip-flop setup, hold and clock-to-
output timing parameters
by the clock.
Hold time is the minimum amount of time the data input should be held
steady after the clock event, so that the data is reliably sampled by the clock.
Aperture is the sum of setup and hold time. The data input should be held steady throughout this time
Recovery time is the minimum amount of time the asynchronous set or reset input should be inactive before
the clock event, so that the data is reliably sampled by the clock. The recovery time for the asynchronous set or
reset input is thereby similar to the setup time for the data input.
Removal time is the minimum amount of time the asynchronous set or reset input should be inactive after the
clock event, so that the data is reliably sampled by the clock. The removal time for the asynchronous set or
reset input is thereby similar to the hold time for the data input.
Short impulses applied to asynchronous inputs (set, reset) should not be applied completely within the
recovery-removal period, or else it becomes entirely indeterminable whether the flip-flop will transition to the
appropriate state. In another case, where an asynchronous signal simply makes one transition that happens to
fall between the recovery/removal time, eventually the flip-flop will transition to the appropriate state, but a very
short glitch may or may not appear on the output, dependent on the synchronous input signal. This second
situation may or may not have significance to a circuit design.
Set and Reset (and other) signals may be either synchronous or asynchronous and therefore may be
characterized with either Setup/Hold or Recovery/Removal times, and synchronicity is very dependent on the
design of the flip-flop.
Differentiation between Setup/Hold and Recovery/Removal times is often necessary when verifying the timing of
larger circuits because asynchronous signals may be found to be less critical than synchronous signals. The
differentiation offers circuit designers the ability to define the verification conditions for these types of signals

Metastability [ edit ]
Main article: metastability in electronics
Flip-flops are subject to a problem called metastability, which can happen when two inputs, such as data and
clock or clock and reset, are changing at about the same time. When the order is not clear, within appropriate
timing constraints, the result is that the output may behave unpredictably, taking many times longer than normal
to settle to one state or the other, or even oscillating several times before settling. Theoretically, the time to
settle down is not bounded. In a computer system, this metastability can cause corruption of data or a program
crash if the state is not stable before another circuit uses its value; in particular, if two different logical paths use
the output of a flip-flop, one path can interpret it as a 0 and the other as a 1 when it has not resolved to stable
state, putting the machine into an inconsistent state.[28]
The metastability in flip-flops can be avoided by ensuring that the data and control inputs are held valid and
constant for specified periods before and after the clock pulse, called the setup time (tsu) and the hold time
(th) respectively. These times are specified in the data sheet for the device, and are typically between a few
nanoseconds and a few hundred picoseconds for modern devices. Depending upon the flip-flop's internal
organization, it is possible to build a device with a zero (or even negative) setup or hold time requirement but
not both simultaneously.
Unfortunately, it is not always possible to meet the setup and hold criteria, because the flip-flop may be
connected to a real-time signal that could change at any time, outside the control of the designer. In this case,
the best the designer can do is to reduce the probability of error to a certain level, depending on the required
reliability of the circuit. One technique for suppressing metastability is to connect two or more flip-flops in a
chain, so that the output of each one feeds the data input of the next, and all devices share a common clock.
With this method, the probability of a metastable event can be reduced to a negligible value, but never to zero.
The probability of metastability gets closer and closer to zero as the number of flip-flops connected in series is
increased. The number of flip-flops being cascaded is referred to as the "ranking"; "dual-ranked" flip flops (two
flip-flops in series) is a common situation.
So-called metastable-hardened flip-flops are available, which work by reducing the setup and hold times as
much as possible, but even these cannot eliminate the problem entirely. This is because metastability is more
than simply a matter of circuit design. When the transitions in the clock and the data are close together in time,
the flip-flop is forced to decide which event happened first. However fast we make the device, there is always
the possibility that the input events will be so close together that it cannot detect which one happened first. It is
therefore logically impossible to build a perfectly metastable-proof flip-flop. Flip-flops are sometimes
characterized for a maximum settling time (the maximum time they will remain metastable under specified
conditions). In this case, dual-ranked flip-flops that are clocked slower than the maximum allowed metastability
time will provide proper conditioning for asynchronous (e.g., external) signals.

Propagation delay [ edit ]

Another important timing value for a flip-flop is the clock-to-output delay (common symbol in data sheets: tCO) or
propagation delay (tP), which is the time a flip-flop takes to change its output after the clock edge. The time for a
high-to-low transition (tPHL) is sometimes different from the time for a low-to-high transition (tPLH).
When cascading flip-flops which share the same clock (as in a shift register), it is important to ensure that the
tCO of a preceding flip-flop is longer than the hold time (th) of the following flip-flop, so data present at the input
of the succeeding flip-flop is properly "shifted in" following the active edge of the clock. This relationship
between tCO and th is normally guaranteed if the flip-flops are physically identical. Furthermore, for correct
operation, it is easy to verify that the clock period has to be greater than the sum tsu + th.

Generalizations [ edit ]
Flip-flops can be generalized in at least two ways: by making them 1-of-N instead of 1-of-2, and by adapting
them to logic with more than two states. In the special cases of 1-of-3 encoding, or multi-valued ternary logic,
these elements may be referred to as flip-flap-flops.[29]
In a conventional flip-flop, exactly one of the two complementary outputs is high. This can be generalized to a
memory element with N outputs, exactly one of which is high (alternatively, where exactly one of N is low). The
output is therefore always a one-hot (respectively one-cold) representation. The construction is similar to a
conventional cross-coupled flip-flop; each output, when high, inhibits all the other outputs.[30] Alternatively, more
or less conventional flip-flops can be used, one per output, with additional circuitry to make sure only one at a
time can be true.[31]
Another generalization of the conventional flip-flop is a memory element for multi-valued logic. In this case the
memory element retains exactly one of the logic states until the control inputs induce a change.[32] In addition, a
multiple-valued clock can also be used, leading to new possible clock transitions.[33]

See also [ edit ]

Wikimedia Commons has
Latching relay media related to Flip-flops.
Positive feedback
Pulse transition detector

References [ edit ]
1. ^a bPedroni, Volnei A. (2008). Digital electronics and design with VHDL . Morgan Kaufmann. p. 329. ISBN 978-
2. ^ a b Latches and Flip Flops (EE 42/100 Lecture 24 from Berkeley) "...Sometimes the terms flip-flop and latch
are used interchangeably..."
3. ^ William Henry Eccles and Frank Wilfred Jordan, "Improvements in ionic relays " British patent number: GB
148582 (filed: 21 June 1918; published: 5 August 1920).
4. ^ See:
W. H. Eccles and F. W. Jordan (19 September 1919) "A trigger relay utilizing three-electrode thermionic
vacuum tubes," The Electrician, 83 : 298.
Reprinted in: Radio Review, 1 (3) : 143146 (December 1919).
Reprinted in: Radio Review, 1 (3) : 143146 (December 1919).
Summary in: W. H. Eccles and F. W. Jordan (1919) "A trigger relay utilising three electrode thermionic vacuum
tubes," Report of the Eighty-seventh Meeting of the British Association for the Advancement of Science:
Bournemouth: 1919, September 913, pp. 271272.
5. ^ Pugh, Emerson W.; Johnson, Lyle R.; Palmer, John H. (1991). IBM's 360 and early 370 systems . MIT Press.
p. 10. ISBN 978-0-262-16123-7.
6. ^ Flowers, Thomas H. (1983), "The Design of Colossus" , Annals of the History of Computing, 5 (3): 249,
7. ^ Gates, Earl D. (2000-12-01). Introduction to electronics (4th ed.). Delmar Thomson (Cengage) Learning.
p. 299. ISBN 978-0-7668-1698-5.
8. ^ Fogiel, Max; Gu, You-Liang (1998). The Electronics problem solver, Volume 1 (revised ed.). Research &
Education Assoc. p. 1223. ISBN 978-0-87891-543-9.
9. ^ P. L. Lindley, Aug. 1968, EDN (magazine), (letter dated June 13, 1968).
10. ^ Phister, Montgomery (1958). Logical Design of Digital Computers. Wiley. p. 128.
11. ^ US 2850566 , Eldred C. Nelson, "High-Speed Printing System", published Sept. 8, 1953, issued Sept. 2, 1958;
page 15
12. ^ Shiva, Sajjan G. (2000). Computer design and architecture (3rd ed.). CRC Press. p. 81. ISBN 978-0-8247-
13. ^ Roth, Charles H. Jr. "Latches and Flip-Flops." Fundamentals of Logic Design. Boston: PWS, 1995. Print.
14. ^ Langholz, Gideon; Kandel, Abraham; Mott, Joe L. (1998). Foundations of Digital Logic Design . Singapore:
World Scientific Publishing Co. Ptc. Ltd. p. 344. ISBN 978-981-02-3110-1.
15. ^ Hinrichsen, Diederich; Pritchard, Anthony J. (2006). Mathematical Systems Theory I: Modelling, State Space
Analysis, Stability and Robustness . Springer. pp. 6364. ISBN 9783540264101.
16. ^ Farhat, Hassan A. (2004). Digital design and computer organization . 1. CRC Press. p. 274. ISBN 978-0-8493-
17. ^ a b Kogge, Peter M. (1981). The Architecture of Pipelined Computers. McGraw-Hill. pp. 2527. ISBN 0-07-
18. ^ Cotten, L. W. (1965). "Circuit Implementation of High-Speed Pipeline Systems". AFIPS Proc. Fall Joint
Computer Conference: 489504. doi:10.1145/1463891.1463945 .
19. ^ Earle, J. (March 1965). "Latched Carry-Save Adder". IBM Technical Disclosure Bulletin. 7 (10): 909910.
20. ^ a b Omondi, Amos R. (1999-04-30). The Microarchitecture of Pipelined and Superscalar Computers . Springer.
pp. 4042. ISBN 978-0-7923-8463-2.
21. ^ a b Kunkel, Steven R.; Smith, James E. (May 1986). "Optimal Pipelining in Supercomputers". ACM SIGARCH
Computer Architecture News. ACM. 14 (2): 404411 [406]. doi:10.1145/17356.17403 . ISSN 0163-5964 .
CiteSeerX: .
22. ^ The D Flip-Flop
23. ^ Edge-Triggered Flip-flops
24. ^ A Survey of Digital Computer Memory Systems
25. ^ SN7474 TI datasheet
26. ^ a b Mano, M. Morris; Kime, Charles R. (2004). Logic and Computer Design Fundamentals, 3rd Edition. Upper
Saddle River, NJ, USA: Pearson Education International. pp. pg283. ISBN 0-13-191165-1.
27. ^ a b Harris, S; Harris, D (2016). Digital Design and Computer Architecture - ARM Edition,. Morgan Kaufmann,
Waltham, MA. ISBN 978-0-12-800056-4.
28. ^ Chaney, Thomas J.; Molnar, Charles E. (April 1973). "Anomalous Behavior of Synchronizer and Arbiter
Circuits" . IEEE Transactions on Computers. C22 (4): 421422. doi:10.1109/T-C.1973.223730 . ISSN 0018-
9340 .
29. ^ Often attributed to Don Knuth (1969) (see Midhat J. Gazal (2000). Number: from Ahmes to Cantor . Princeton
University Press. p. 57. ISBN 978-0-691-00515-7.), the term flip-flap-flop actually appeared much earlier in the
computing literature, for example, Bowdon, Edward K. (1960). The design and application of a "flip-flap-flop" using
tunnel diodes (Master's thesis) . University of North Dakota., and in Alexander, W. (Feb 1964). "The ternary
computer" . Electronics and Power. IET. 10 (2): 3639. doi:10.1049/ep.1964.0037 .
30. ^ "Ternary "flip-flap-flop" " .
31. ^ US 6975152
32. ^ Irving, Thurman A.; Shiva, Sajjan G.; Nagle, H. Troy (March 1976). "Flip-Flops for Multiple-Valued Logic".
Computers, IEEE Transactions on. C25 (3): 237246. doi:10.1109/TC.1976.5009250 .
33. ^ Wu, Haomin; Zhuang Nan (1991). "Research into ternary edge-triggered JKL flip-flop". Journal of Electronics
(China). 8 (Volume 8, Number 3 / July, 1991): 268275. doi:10.1007/BF02778378 .
External links [ edit ]
FlipFlop Hierarchy , shows interactive flipflop circuits. Wikibooks has a book on
The J-K Flip-Flop the topic of: Digital

Authority control GND: 4135907-0

Categories: Digital electronics Electronic engineering Digital systems Logic gates Computer memory

This page was last modified on 4 October 2016, at 06:14.

Text is available under the Creative Commons Attribution-ShareAlike License; additional terms may apply. By using this site, you agree to the Terms
of Use and Privacy Policy. Wikipedia is a registered trademark of the Wikimedia Foundation, Inc., a non-profit organization.

Privacy policy About Wikipedia Disclaimers Contact Wikipedia Developers Cookie statement Mobile view
Search on Network

Home Jobs Enewsletter Events Buyers Guide Magazine Subscription Advertiser Press room Contact Us


Most consulted news

Options for Improving the Efficiency of Heat Recovery T oday This Week This Month
Steam Generators
by V. Ganapathy, ABCO Industries, Abilene, Texas

In any heat transfer equipment such as a boiler or Heat Recovery Steam Generator (HRSG),
the exit gas temperature determines the amount of energy recovered from the flue gas stream,
which is indicative of efficiency. Hence efforts are often made to lower this temperature as
much as possible taking into consideration cost effectiveness and low temperature corrosion
concerns. In a conventional steam generator such as a package boiler, the exit gas
temperature is independent of steam pressure. With say a 230 F feed water temperature, an
exit gas temperature of about 300 F can be easily achieved using an economizer as the heat
recovery equipment. However in a gas turbine HRSG, due to thermodynamic reasons, the exit
gas temperature is a function of inlet gas temperature, feed-water temperature and steam
pressure. The low exhaust gas temperature from gas turbines, typically ranging from 900 to
1050F, generates less steam on unit gas mass basis in the HRSG evaporator compared to a
package boiler. On the other hand, in a steam generator or package boiler, the flue gas stream
is cooled from adiabatic combustion temperature of 3300 F and hence generates a large
amount of steam on unit gas mass basis. Table 1 shows the gas/steam ratio of HRSGs and
steam generators. The small ratio of steam to gas flow in a HRSG is not adequate to cool the
exhaust gases in the economizer, resulting in a high exit gas temperature. Also it can be shown
that higher the steam pressure, higher the exit gas temperature and vice versa. However
various options are available for lowering the exit gas temperature, which improves the HRSG
efficiency and these are examined in this article.

Table 1: Gas inlet temperature vs Steam generation in HRSGs and steam generatorsType of
HRSG gas inlet temp Gas/steam
Unfired 850-1000 7 to 5.5
Supplemenatry fired 1000-1700 5.5 to 2.5
Furnace fired HRSG 1700-3200 2.5 to 1.2
Steam generator* 3300-3400 1.2 to 1.3
[* typical oil or gas fired steam generator]

HRSG temperature profiles

Fig 1 shows a simple gas turbine HRSG consisting of a superheater, evaporator and
economizer. The exhaust gas from the gas turbine enters the HRSG at a temperature of Tg1.
Steam is generated at a temperature of ts2 using feed water at tw1. Two important variables
determine the temperature profiles and steam generation, namely Pinch point and Approach

Pinch point is the difference between the gas temperature leaving the evaporator and
saturation temperature=Tg3-ts

Fig 1: HRSG temperature profiles

Approach point is the difference between saturation temperature and feed water temperature
entering the evaporator= ts -tw2.

Pinch and approach points cannot be arbitrarily selected. In an unfired HRSG, minimum pinch
and approach points range from 10 to 20 F depending on economic considerations. A low
pinch or approach point naturally increases the surface area required for the evaporator and
economizer and thus the HRSG cost. A large value for these variables decreases the amount
of energy recovered and hence a balance has to be struck.

The energy recovered from the superheater and evaporator=Q12=WgCp(Tg1-Tg3)xhl=Ws


The energy recovered from the complete HRSG=Q13=WgCp(Tg1-Tg4)=Ws(hs2-hw1)

In the above equations, blow down was neglected.

Wg, Ws=gas flow and steam generation, lb/h
Cp=gas specific heat, Btu/lbF
hs2=enthalpy of steam, Btu/lb
hw1,hw2=enthalpy of feed water entering and leaving economizer, F
Tg1,Tg2,Tg3,Tg4=gas temperatures at various surfaces as shown in Fig 1, F
hl=heat loss factor, typically 0.99 to 0.995

Neglecting variations in gas specific heats we have from the above equations:
where X is a function of steam parameters. For steam generation to occur, two conditions must
be satisfied: Tg3>ts and Tg4>tw1

If the pinch point is arbitrarily selected, then it is likely that Tg4 can be lower than tw1; if the
approach point is arbitrarily selected, then it is likely that Tg3 can be lower than ts. These
situations are referred to as temperature cross conditions from thermodynamic view point.

Thus one cannot assume an exit gas temperature and determine the steam generation. A
temperature profile analysis must be done in the unfired mode as shown below.

Evaluating Steam Generation and Temperature profiles in a HRSG

Example: A HRSG generates 600 psig, 750 F steam using feed water at 230 F. Exhaust gas
flow is 160,000 lb/h at 950 F.% volume CO2=3, H2O=7, N2=75, O2=15. Calculate the unfired
steam using 25 degree pinch and 20 degree approach points. Use a heat loss factor of 0.98.

Solution: Assume 10 psi pressure drop in the superheater. The drum pressure is 610 psig and
the saturation temperature is 492 F. The gas temperature leaving the evaporator=492+25=517
F. The feed water temperature entering evaporator or leaving economizer is 492-20=472 F.

The energy absorbed by superheater and evaporator= 160,000 x 0.27 x 0.98 x (950-517)
=18.33 MM Btu/h. In this expression, 0.98 refers to the 2 % heat loss in the HRSG system and
0.27 the specific heat of the gas at the average temperature of 734 F.

The enthalpy absorbed by steam=(1378.9-455.4) Btu/lb, where 1378.9 and 455.4 refer to
enthalpies of steam at 600 psig, 750 F and at water at 472 F. Neglecting blow down, we have
the steam production as: 18.33x106/(1378.9-455.4)=19,850 lb/h

The energy absorbed in the superheater= (1378.9-1202.8) x 19,850=3,495,600 Btu/h

The gas temperature drop across the superheater=3.495x106/(160,000x0.98x0.28)=79 F

Thus gas temperature leaving the superheater= 950-79=871 F

The energy absorbed by economizer=19850 x (455.4-199.7) = 5.076x106 Btu/h, where 199.7

is the enthalpy of the feed water at 230 F.

The gas temperature drop across economizer=5.076x106/(160,000x0.98x0.26)=125 F. Thus

HRSG exit gas temperature=517-125=392 F

The total energy absorbed by steam=23.4 MM Btu/h

This calculation is referred to as the design mode.

It may be seen that the exit gas temperature is rather high. With lower pinch and approach
points, we could bring it down a little to around 370 F but not to 300 F range. Thus unfired
single pressure HRSGs are not very efficient particularly at high steam pressures. The exit gas
temperature will be higher at higher steam pressures. Table 1 shows the results of calculations
for various steam pressures.

Table 1: Exit gas temperature from unfired HRSG

Pressure Steam tem,F Sat tem, F X Exit gas,F
100 Sat 338 0.904 300
150 Sat 366 0.8754 313
250 Sat 406 0.8337 332
400 Sat 448 0.7895 353
400 600 450 0.8063 367
600 Sat 490 0.74 373
600 750 492 0.7728 398

(based on 15 F approach point,20 F pinch point and 900 F gas inlet temperature and no blow
down. Feed water temperature=230 F)

It can be easily seen that higher the steam pressure, higher the exit gas temperature.
This is due to the fact that higher the steam pressure, higher the saturation temperature
of steam and higher the gas temperature leaving the evaporator. Hence less energy is
available between the gas inlet temperature and gas temperature leaving the evaporator
and the resulting flow through the economizer is not adequate to cool the exit gas
temperature to a low level.
Higher the steam temperature, higher the exit gas temperature. This is again due to the
fact that less steam is generated if it is superheated (due to the higher enthalpy
absorbed by steam) and the resulting low flow through the economizer is not adequate
to cool the exhaust gases to a low exit gas temperature.
Higher the gas inlet temperature, lower will be exit gas temperature. For example, if the
inlet temperature is 1000 F instead of 900 F, the exit gas temperature for the case of 600
psig, 750 F steam is: 1000-(1000-512)/.7728=369 F versus 398 F. This is due to the
simple fact that more energy is available between the gas temperatures entering the
HRSG and leaving the evaporator, which generates more steam, which in turn results in
more water flow through the economizer; the larger heat sink at the economizer can cool
the gases further. It may be shown similarly that lower the gas inlet temperature, higher
the exit gas temperature from the HRSG. This is one of the reasons that part load
operation of gas turbines is not generally a good idea.
Lower the feed water temperature, lower will be exit gas temperature. However one can
to consider condensation of water vapor on economizer surfaces if the inlet temperature
is below the water dew point.

We mentioned earlier that the exit gas temperature and pinch and approach points cannot be
arbitrarily selected and an analysis similar to that above should be done to establish
temperature profiles else there will be temperature crossings. To illustrate this point, a few
examples are given.

Example: Can we obtain a stack temperature of 300 F with 900 F gas inlet temperature and
with steam parameters of 600 psig,750 F and 230 F feed water?

We note from Table 1 that 398 F is the exit gas temperature. With minor improvements in pinch
and approach points, the exit gas temperature can be lowered slightly but not to 300 F level.
Let us see what happens if we did so.

X=0.7728=(900-Tg3)/(900-300) or Tg3=437 F! The gas temperature leaving the evaporator

cannot be lower than the saturation temperature of 492 F; this indicates a temperature cross
situation. Hence it is a thermodynamic issue and no amount of surface area at the evaporator
or economizer can lower the exit gas temperature below the level of 398 - 380 F.

Example: Can we have a pinch point of 20 F when the gas inlet temperature is say 1500 F?

Tg3=512 F at 600 psig. (1500-512)/(1500-Tg4)=0.7728 or Tg4=221 F, which falls below the

feed water temperature. Hence a large pinch point and a large approach point is associated
with high inlet gas temperatures.

Predicting off-design performanceIn order to evaluate the temperature profiles in the fired
mode or other off-design cases, a HRSG simulation analysis should be done[1]. This analysis
estimates the (UA) value of each surface and corrects it for the off-design or fired conditions for
the effects of gas flow, gas analysis and temperature.[U=overall heat transfer coefficient and
A=surface area].Then using the NTU (Number of Transfer Units)method, one arrives at the
performance. In the off-design mode the pinch and approach points fall in place. There is only
one design mode analysis but there can be numerous off-design cases.A software is required
to perform this complex analysis, particularly if the HRSG has multiple pressure levels and has
a complex arrangement of heating surfaces. Note that simulation analysis does not require the
physical design of the HRSG as UA is taken as a single entity, which can be obtained from the
equation Q=UADT, where Q=energy transferred to the surface and DT is the log-mean
temperature difference.

Once we have the HRSG performance in various modes of operation such as unfired, fired,
part load etc, the next question is: How can we improve the efficiency of a HRSG or lower the
exit gas temperature?

Options to improve HRSG efficiency

There are a few options to improve the efficiency of a HRSG. These could be combined or
used in isolation. The ideal option varies from case to case based on plant operating period,
cost of fuel and electricity and initial investment cost.

Multiple pressure steam generation

Optimizing arrangement of heating surfaces
Auxilliary firing
Use of secondary surfaces such as condensate heater, de-aerator or heat exchanger
Using low pinch and approach points for the HRSG evaporator

Multiple pressure steam generation

As seen earlier, in an unfired HRSG the exit gas temperature is rather high and the situation
worsens if the steam pressure is increased. Hence in order to lower the exit gas temperature
from the HRSG, additional steam may be generated at a lower pressure as shown in Fig 2. In
this design, the high pressure stage is followed by the low pressure system. Using the HRSG
simulation program [1].the design temperature profiles were obtained. The figure shows a
HRSG generating 39,500 lb/h of high-pressure steam at 800 psig/750 F and 6270 lb/h low
pressure steam at 100 psig. The exit gas temperature is 340 F.

Rearranging heat transfer surfaces

Though the option discussed above is better than a single pressure system, one can improve
the energy recovery through rearrangement of heating surfaces. The heat sink or the
economizer, in Fig 2 is not a large one, basically handling the water flow of the low-pressure
evaporator. If the water flow through this can be increased somehow, we can cool the exhaust
gases further. The simplest way is to use the common economizer concept as shown in Fig 3.
Here the feed-water through the economizer feeds both the high and low-pressure
evaporators, thus handling much larger amount of flow. This larger heat sink cools the exhaust
gas to 281 F versus 340 F in the earlier case. We are able to generate more low-pressure
Fig 2: HRSG temperature profiles using separate modules

Fig 3: HRSG temperature profiles using common economizer concept

Auxilliary firing
Auxilliary firing of turbine exhaust gases is the simplest way to improve the efficiency of a
HRSG. In a gas turbine, unlike a steam generator, the exhaust gas flow remains constant and
adding fuel alone without adding air increases the exhaust gas temperature. The exhaust gas
typically has 14 % volume of oxygen and hence is capable of being fired to about 3000 F
without additional air. The relation between oxygen consumption and fuel input to a HRSG is
given by the simple relation [1]: Q=58.4WO

Where Q=heat input in MM Btu/h on LHV basis

W=gas flow, lb/h and O is the oxygen consumption in % volume.

Let the exhaust gas flow=100,000 lb/h at 900 F with the following analysis:
CO2=3,H2O=7,N2=75 and O2=15 by volume. If the gas inlet temperature is 900 F and is
raised to 3000 F, the fuel required can be shown to be 74 MM Btu/h. This lowers the oxygen
content by about 12.3 % and hence 2.7 % oxygen still remains in the exhaust gases. Thus a lot
of energy can be added to the exhaust gases, which in turn generates steam in the HRSG. The
exit gas temperature is also lowered due to the larger heat sink in the form of economizer. In
fact, it can be shown that the efficiency of fuel input is nearly 100 % or all of the fuel goes into
generating steam. In a conventional boiler, it is a well known fact that increasing the excess air
decreases the boiler efficiency. In a HRSG,the excess air is decreased by addition of fuel,
which increases the efficiency. Also, we have a lower exit gas temperature, which also
contributes to the efficiency improvement.

Fig 4: Furnace fired HRSG in a cogeneration plant

Fig 4 shows the arrangement of a furnace fired HRSG capable of being fired to adiabatic
combustion temperature. It has water cooled membrane walls, a furnace section, followed by a
screen section, a two-stage superheater and an evaporator with an economizer. Fig 5a, 5b
show gas/steam temperature profiles of a HRSG in unfired and fired modes. The HRSG was
designed in the unfired mode and its performance simulated in the fired mode. The printouts
from the simulation program also show the HRSG efficiency using ASME PTC 4.4 method.
Note the change in the pinch point, approach point and the exit gas temperature in the fired
mode. The additional fuel input of 27.83 MM Btu/h adds 28.5 MM Btu/h to the steam, which is
indicative of the 100 % plus efficiency of fuel utilization in the fired mode. In fact it can be
shown that in a cogeneration plant, it makes more sense to generate additional steam in the
HRSG rather than in the package boiler, as the efficiency of steam generation is only about 92
to 93 % (LHV) in a boiler versus 100 % in a HRSG.
Fig 5a: HRSG temperature profiles in the design,unfired mode

Fig 5b: HRSG temperature profiles in off-design, fired mode

Fig 6: Secondary surfaces to improve HRSG efficiency

Secondary surfaces to improve efficiency

Fig 6 shows the arrangement of various secondary surfaces to improve the energy recovery
process. The de-aerator coil supplies steam for de-aeration and also cools the exhaust gases.
The condensate heater preheats the make up water before entering the de-aerator and thus
reduces the steam for de-aeration. The heat exchanger option increases the energy recovered
from the exhaust gases and also reduces the de-aeration steam.

Using low pinch and approach points

If secondary surfaces or low pressure steam is not required, one may use low pinch and
approach points to maximize steam generation. However this increases the HRSG evaporator
and economizer surfaces and hence the cost. An economic evaluation may be done to arrive at
the optimum pinch and approach points.

Efficiency of an unfired single pressure HRSG is low and can be improved using several
methods as discussed above. Though the cost of the HRSG increases, the payback is quick
and well worth consideration, particularly when the fuel cost is on the rise. HRSG simulation is
a valuable tool that may be used to evaluate the performance of HRSGs in various modes of
operation to determine if the HRSG design can be optimized. It also helps to arrive at the
gas/steam temperature profiles in a HRSG, which is basic to understanding and improving the
HRSG performance.

1.V.Ganapathy, Waste Heat Boiler Deskbook, Fairmont Press
2.V.Ganapathy, HRSGs-Understanding the basics, Chemical Engineering Progress, Aug
3.V.Ganapathy, Efficiently generate steam from cogeneration plants, Chemical Engineering,
May 1997

Author Information
V.Ganapathy is a Heat Transfer Specialist with ABCO industries, Abilene, Texas, where he is
responsible for process engineering of package boilers and heat recovery boilers. He holds a
Bachelors and Masters degree in Mechanical Engineering. Ganapathy is the author of over
200 articles and papers on boilers, heat recovery and steam generation and has authored four
books. He has also contributed several chapters to the Encyclopedia of Chemical Processing
and Design. He can be reached at

Article published part of the November/December 2001 Issue


Contact us Press Subscription

Send us a press release Create your user account and receive enewsletter
RSS Receive JOBS Enewsletter
All news
General News
Renewable Energy General
Jaguar Expo Inc
Energy Efficiency Automation and IT
834 Monte Masson
Terrebonne (Quebec) J6W 2C6 T&D
Mergers & Acquisition
Appointments etc... Renewable Energy
Tel.: 450-471-0796 Generation
Toll free: 888-332-3749
Oil & Gas Mergers & Acquisitions
Fax: 450-471-5443 . 888-243-4562
Appointments etc... Jobs Financial Oil & Gas
Post or modify a job
View jobs Magazine

Events Current Issue

View calendar
Post an event

2016, Jaguar Media inc. All rights reserved. 1996-2016


Home / Sequential Logic / Sequential Logic Circuits

Sequential Logic Circuits

Unlike Combinational Logic circuits that change state depending upon the actual signals being applied
to their inputs at that time, Sequential Logic circuits have some form of inherent Memory built in.

This means that sequential logic circuits are able to take into account their previous input state as well
as those actually present, a sort of before and after effect is involved with sequential circuits.
In other words, the output state of a sequential logic circuit is a function of the following three
states, the present input, the past input and/or the past output. Sequential Logic circuits
remember these conditions and stay fixed in their current state until the next clock signal changes
one of the states, giving sequential logic circuits Memory.
Sequential logic circuits are generally termed as two state or Bistable devices which can have their
output or outputs set in one of two basic states, a logic level 1 or a logic level 0 and will remain
latched (hence the name latch) indefinitely in this current state or condition until some other input
trigger pulse or signal is applied which will cause the bistable to change its state once again.
Sequential Logic Representation

Looking for the latest from TI?

The word Sequential means that things happen in a sequence, one after another and in
Sequential Logic circuits, the actual clock signal determines when things will happen next. Simple
sequential logic circuits can be constructed from standard Bistable circuits such as: Flip-flops, Latches
and Counters and which themselves can be made by simply connecting together universal NAND
Gates and/or NOR Gates in a particular combinational way to produce the required sequential circuit.
Related Products: Direct Digital Synthesizer
Classification of Sequential Logic
As standard logic gates are the building blocks of combinational circuits, bistable latches and flip-
flops are the basic building blocks of sequential logic circuits. Sequential logic circuits can be
constructed to produce either simple edge-triggered flip-flops or more complex sequential circuits
such as storage registers, shift registers, memory devices or counters. Either way sequential logic
circuits can be divided into the following three main categories:
1. Event Driven asynchronous circuits that change state immediately when enabled.
2. Clock Driven synchronous circuits that are synchronised to a specific clock signal.
3. Pulse Driven which is a combination of the two that responds to triggering pulses.

As well as the two logic states mentioned above logic level 1 and logic level 0, a third element is
introduced that separates sequential logic circuits from their combinational logic counterparts,
namely TIME. Sequential logic circuits return back to their original steady state once reset and
sequential circuits with loops or feedback paths are said to be cyclic in nature.
We now know that in sequential circuits changes occur only on the application of a clock signal making
it synchronous, otherwise the circuit is asynchronous and depends upon an external input. To retain
their current state, sequential circuits rely on feedback and this occurs when a fraction of the output is
fed back to the input and this is demonstrated as:
Sequential Feedback Loop

The two inverters or NOT gates are connected in series with the output at Q fed back to the input.
Unfortunately, this configuration never changes state because the output will always be the same,
either a 1 or a 0, it is permanently set. However, we can see how feedback works by examining the
most basic sequential logic components, called the SR flip-flop.
SR Flip-Flop
The SR flip-flop, also known as a SR Latch, can be considered as one of the most basic sequential logic
circuit possible. This simple flip-flop is basically a one-bit memory bistable device that has two
inputs, one which will SET the device (meaning the output = 1), and is labelled S and another
which will RESET the device (meaning the output = 0), labelled R.
Then the SR description stands for Set-Reset. The reset input resets the flip-flop back to its
original state with an output Q that will be either at a logic level 1 or logic 0 depending upon this
set/reset condition.
A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back to its opposing
inputs and is commonly used in memory circuits to store a single data bit. Then the SR flip-flop
actually has three inputs, Set, Reset and its current output Q relating to its current state or history.
The term Flip-flop relates to the actual operation of the device, as it can be flipped into one logic
Set state or flopped back into the opposing logic Reset state.
The NAND Gate SR Flip-Flop
The simplest way to make any basic single bit set-reset SR flip-flop is to connect together a pair of
cross-coupled 2-input NAND gates as shown, to form a Set-Reset Bistable also known as an active
LOW SR NAND Gate Latch, so that there is feedback from each output to one of the other NAND gate
inputs. This device consists of two inputs, one called the Set, S and the other called the Reset, R with
two corresponding outputs Q and its inverse or complement Q (not-Q) as shown below.
The Basic SR Flip-flop

The Set State

Consider the circuit shown above. If the input R is at logic level 0 (R = 0) and input S is at logic level
1 (S = 1), the NAND gate Y has at least one of its inputs at logic 0 therefore, its output Q must be
at a logic level 1 (NAND Gate principles). Output Q is also fed back to input A and so both inputs to
NAND gate X are at logic level 1, and therefore its output Q must be at logic level 0.
Again NAND gate principals. If the reset input R changes state, and goes HIGH to logic 1 with S
remaining HIGH also at logic level 1, NAND gate Y inputs are now R = 1 and B = 0. Since one of
its inputs is still at logic level 0 the output at Q still remains HIGH at logic level 1 and there is no
change of state. Therefore, the flip-flop circuit is said to be Latched or Set with Q = 1 and Q =
Reset State
In this second stable state, Q is at logic level 0, (not Q = 0) its inverse output at Q is at logic level
1, (Q = 1), and is given by R = 1 and S = 0. As gate X has one of its inputs at logic 0 its output
Q must equal logic level 1 (again NAND gate principles). Output Q is fed back to input B, so both
inputs to NAND gate Y are at logic 1, therefore, Q = 0.
If the set input, S now changes state to logic 1 with input R remaining at logic 1, output Q still
remains LOW at logic level 0 and there is no change of state. Therefore, the flip-flop circuits
Reset state has also been latched and we can define this set/reset action in the following truth
Truth Table for this Set-Reset Function
State S R Q Q Description
1 0 0 1 Set Q 1
1 1 0 1 no change
0 1 1 0 Reset Q 0
1 1 1 0 no change
Invalid 0 0 1 1 Invalid Condition

It can be seen that when both inputs S = 1 and R = 1 the outputs Q and Q can be at either logic level
1 or 0, depending upon the state of the inputs S or R BEFORE this input condition existed.
Therefore the condition of S = R = 1 does not change the state of the outputs Q and Q.
However, the input state of S = 0 and R = 0 is an undesirable or invalid condition and must be
avoided. The condition of S = R = 0 causes both outputs Q and Q to be HIGH together at logic level
1 when we would normally want Q to be the inverse of Q. The result is that the flip-flop looses
control of Q and Q, and if the two inputs are now switched HIGH again after this condition to logic
1, the flip-flop becomes unstable and switches to an unknown data state based upon the unbalance
as shown in the following switching diagram.
S-R Flip-flop Switching Diagram

This unbalance can cause one of the outputs to switch faster than the other resulting in the flip-flop
switching to one state or the other which may not be the required state and data corruption will exist.
This unstable condition is generally known as its Meta-stable state.
Then, a simple NAND gate SR flip-flop or NAND gate SR latch can be set by applying a logic 0, (LOW)
condition to its Set input and reset again by then applying a logic 0 to its Reset input. The SR flip-
flop is said to be in an invalid condition (Meta-stable) if both the set and reset inputs are activated
As we have seen above, the basic NAND gate SR flip-flop requires logic 0 inputs to flip or change
state from Q to Q and vice versa. We can however, change this basic flip-flop circuit to one that
changes state by the application of positive going input signals with the addition of two extra NAND
gates connected as inverters to the S and R inputs as shown.
Positive NAND Gate SR Flip-flop

As well as using NAND gates, it is also possible to construct simple one-bit SR Flip-flops using two
cross-coupled NOR gates connected in the same configuration. The circuit will work in a similar way to
the NAND gate circuit above, except that the inputs are active HIGH and the invalid condition exists
when both its inputs are at logic level 1, and this is shown below.
The NOR Gate SR Flip-flop

Switch Debounce Circuits

Edge-triggered flip-flops require a nice clean signal transition, and one practical use of this type of
set-reset circuit is as a latch used to help eliminate mechanical switch bounce. As its name implies,
switch bounce occurs when the contacts of any mechanically operated switch, push-button or keypad
are operated and the internal switch contacts do not fully close cleanly, but bounce together first
before closing (or opening) when the switch is pressed.
This gives rise to a series of individual pulses which can be as long as tens of milliseconds that an
electronic system or circuit such as a digital counter may see as a series of logic pulses instead of one
long single pulse and behave incorrectly. For example, during this bounce period the output voltage
can fluctuate wildly and may register multiple input counts instead of one single count. Then set-reset
SR Flip-flops or Bistable Latch circuits can be used to eliminate this kind of problem and this is
demonstrated below.
SR Flip Flop Switch Debounce Circuit
Depending upon the current state of the output, if the set or reset buttons are depressed the output
will change over in the manner described above and any additional unwanted inputs (bounces) from
the mechanical action of the switch will have no effect on the output at Q.
When the other button is pressed, the very first contact will cause the latch to change state, but any
additional mechanical switch bounces will also have no effect. The SR flip-flop can then be RESET
automatically after a short period of time, for example 0.5 seconds, so as to register any additional and
intentional repeat inputs from the same switch contacts, such as multiple inputs from a keyboards
Commonly available ICs specifically made to overcome the problem of switch bounce are the
MAX6816, single input, MAX6817, dual input and the MAX6818 octal input switch debouncer ICs.
These chips contain the necessary flip-flop circuitry to provide clean interfacing of mechanical
switches to digital systems.
Set-Reset bistable latches can also be used as Monostable (one-shot) pulse generators to generate a
single output pulse, either high or low, of some specified width or time period for timing or control
purposes. The 74LS279 is a Quad SR Bistable Latch IC, which contains four individual NAND type
bistables within a single chip enabling switch debounce or monostable/astable clock circuits to be
easily constructed.
Quad SR Bistable Latch 74LS279

Gated or Clocked SR Flip-Flop

It is sometimes desirable in sequential logic circuits to have a bistable SR flip-flop that only changes
state when certain conditions are met regardless of the condition of either the Set or the Reset inputs.
By connecting a 2-input AND gate in series with each input terminal of the SR Flip-flop a Gated SR
Flip-flop can be created. This extra conditional input is called an Enable input and is given the
prefix of EN. The addition of this input means that the output at Q only changes state when it is
HIGH and can therefore be used as a clock (CLK) input making it level-sensitive as shown below.
Gated SR Flip-flop

When the Enable input EN is at logic level 0, the outputs of the two AND gates are also at logic
level 0, (AND Gate principles) regardless of the condition of the two inputs S and R, latching the two
outputs Q and Q into their last known state. When the enable input EN changes to logic level 1 the
circuit responds as a normal SR bistable flip-flop with the two AND gates becoming transparent to the
Set and Reset signals.
This additional enable input can also be connected to a clock timing signal (CLK) adding clock
synchronisation to the flip-flop creating what is sometimes called a Clocked SR Flip-flop. So a
Gated Bistable SR Flip-flop operates as a standard bistable latch but the outputs are only activated
when a logic 1 is applied to its EN input and deactivated by a logic 0.
In the next tutorial about Sequential Logic Circuits, we will look at another type of simple edge-
triggered flip-flop which is very similar to the RS flip-flop called a JK Flip-flop named after its
inventor, Jack Kilby. The JK flip-flop is the most widely used of all the flip-flop designs as it is
considered to be a universal device.

Resistor Tutorial

The JK Flip Flop


Join the conversation!

Your Name

Email Address

Write your comment here

What's the Answer * SUBMIT

six = six

M Md Robiul Islam Prince (MBSTU)

Really very helpfull.
Posted on October 04th 2016 | 1:29 pm

s suvradip das
great tutorial.. really helpful
Posted on October 04th 2016 | 10:52 am

G Gowthaman
This tutorial is very mush use full for me .
This shows clear ideas & good content.
Posted on September 24th 2016 | 10:19 am

g girihelp
nice material
Posted on September 03rd 2016 | 8:18 am

K Kenny
For the basic SR flip flop, why are there bars over the S and R symbols at the input of the basic SR flip flop?
Posted on June 24th 2016 | 5:42 am

Wayne Storr
The overbar represents an inverted (NOT function) or complementary operator. So if A = 1 then NOT A = 0.
When used this way it shows that a low voltage level 0 is required at the input.
Posted on June 24th 2016 | 9:29 am

K Kenny
Thanks Wayne. I understand now. The meaning of the bar is defined by the designer of the
circuit, right? The meaning here seems to be if we make the S_bar input low, and make the
R_bar input high, then the result is the Q output will become high.
When you meant required at the input, this means required at the input in order to have the
output Q go high.
Posted on June 28th 2016 | 5:01 am

K Kenny
For the sequential feedback loop diagram, why is there a summer (adder) at the input? Or is it a multiplier? What
exactly is the circle with a X sign inside the circle, with + symbols in each input terminal.
Posted on June 24th 2016 | 5:07 am


s sajid Rafique
There is a mistake in the NOR gate flip flop terminology even though the truth table is correct . Set usually is used
to set Q true .
Posted on June 07th 2016 | 8:01 pm
T Talha Malik
Nice Topic and i understand this topic easily thank you
Posted on June 06th 2016 | 6:32 pm

j joe
very clear , i was confused on the situation when s = 1 and Qnot= 1, in other texts it is the inverse of that , it is like
when it is on set state Q must be at high state and Qnot at low, nice though
Posted on May 31st 2016 | 9:22 am

s saurabh
nice & worth while
Posted on May 31st 2016 | 4:44 am

View More

Other Tutorials in Sequential Logic

The Shift Register
The D-type Flip Flop
The JK Flip Flop
Sequential Logic Circuits
Featured Design

Small Footprint Isolated Analog DC/DC

Converter Reference Design
The design measures Total Harmonic
Distortion (THD), monitors voltage sags and
swells, and measures phase-to-phase angles
to help determine phase sequence and
prevent accidental phase swapping.

View More Designs

Related Tutorials

Conversion of Flip-flops
Jan 15th, 2016
We have seen throughout this Electronics Tutorial section on Sequential Logic that a flip-flop will remain in [...]
Johnson Ring Counter
Jan 15th, 2016
In the previous Shift Register tutorial we saw that if we apply a serial data [...]


Contact Us
Privacy Policy
Terms of Use


Contact Sales


Electronics Tutorials
Electronic Products
Embedded Developer
ICC Media
Engineers Garage

Facebook Google+

All contents are Copyright 2016 by AspenCore, Inc. All Rights Reserved.
Learnabout electronics
Digital Electronics

Select Language Google Search

Powered by Translate
The Web This site

1. Number Systems 2. Digital Logic 3. Logic Families 4. Combinational Logic 5. Sequential Logic
5.0 Introduction 5.1 Clock Circuits 5.2 SR Flip Flops 5.3 D Type Flip Flops 5.4 JK Flip-flops 5.5 CMOS Flip-flops
5.6 Counters 5.7 Registers 5.8 A Simple ALU 5.9 Quiz 5.10 EXTRA Logic Circuit Simulation

Module 5.2
SR Flip-flops
What youll learn in Module 5.2
After studying this section, you should be able to:

Describe SR flip-flop circuits and can:

Describe typical applications for SR flip-flops.

Recognize standard circuit symbols for SR flip-flops.

Recognize SR flip-flop integrated circuits.

Compile truth tables for SR flip-flops.

Construct timing diagrams to explain the operation of SR flip-flops.

Recognise alternative forms of SR flip-flops.

The Clocked SR flip-flop.

The RS Latch.

Use software to simulate SR flip-flops.

Typical applications for SR Flip-flops.

The basic building bock that makes computer memories possible, and is also used in many sequential logic circuits is the flip-flop or
bi-stable circuit. Just two inter-connected logic gates make up the basic form of this circuit whose output has two stable output states.
When the circuit is triggered into either one of these states by a suitable input pulse, it will remember that state until it is changed by a
further input pulse, or until power is removed. For this reason the circuit may also be called a Bi-stable Latch.

The SR flip-flop can be considered as a 1-bit memory, since it stores the input pulse even after it has passed. Flip-flops (or bi-stables)
of different types can be made from logic gates and, as with other combinations of logic gates, the NAND and NOR gates are the most
versatile, the NAND being most widely used. This is because, as well as being universal, i.e. it can be made to mimic any of the other
standard logic functions, it is also cheaper to construct. Other, more widely used types of flip-flop are the JK, the D type and T type,
which are developments of the SR flip-flop and will be studied in Modules 5.3 and 5.4.
The SR Flip-flop.
The SR (Set-Reset) flip-flop is one of the simplest sequential circuits and
consists of two gates connected as shown in Fig. 5.2.1. Notice that the
output of each gate is connected to one of the inputs of the other gate,
giving a form of positive feedback or cross-coupling.

The circuit has two active low inputs marked S and R, NOT being indicated
by the bar above the letter, as well as two outputs, Q and Q. Table 5.2.1
shows what happens to the Q and Q outputs when a logic 0 is applied to
either the S or R inputs. Fig. 5.2.1 Fig 5.2.1 SR Flip-flop (low activated)

The SR Flip-flop Truth Table (Table 5.2.1)

1. Q output is set to logic 1 by applying logic 0 to the S input.
2. Returning the S input to logic 1 has no effect. The 0 pulse (high-
low-high) has been remembered by the Q.
3. Q is reset to 0 by logic 0 applied to the R input.
4. As R returns to logic 1 the 0 on Q is remembered by Q.

Problems with the SR Flip-flop

There are however, some problems with the operation of this most basic of flip-flop circuits. For conditions 1 to 4 in Table 5.2.1, Q is
the inverse of Q. However, in row 5 both inputs are 0, which makes both Q and Q = 1, and as they are no longer opposite logic states,
although this state is possible, in practical circuits it is not allowed.

In row 6 both inputs are at logic 1 and the outputs are shown as indeterminate, this means that although Q and Q will be at opposite
logic states it is not certain whether Q will be 1 or 0, Notice however that in the absence of any input pulses, both inputs are normally at
logic 1. This is normally OK, as the outputs will be at the state remembered from the last input pulse. The indeterminate or uncertain
logic state only occurs if the inputs change from 0,0 to 1,1 together. This should be avoided in normal operation, but is likely to happen
when power is first applied. This could lead to uncertain results, but the flip-flop will work normally once an input pulse is applied to
either input.

The SR Flip-flop is therefore, a simple 1-bit memory. If the S input is taken to logic 0 then back to logic 1, any further logic 0 pulses atS
will have no effect on the output.

Fig. 5.2.2 Switch Bounce

Switch De-Bouncing
The fact that repeated pulses at the S (or the R) inputs are ignored after the initial pulse has set or reset the Q output, makes the SR
Flip-flop useful for switch de-bouncing.

When any moving object collides with a stationary object it tends to bounce; the contacts in switches are no exception to this rule.
Although the contacts may be tiny and the movement small, as the contacts close they will tend to bounce rather than close and stay

This causes a number of very fast on and off states for a short time, until the
contacts stop bouncing in the closed position. The length of time of the bouncing
may be very short, as shown in Fig. 5.2.3 where a number of fast pulses occur for
about 2ms after the switch is initially closed (red arrow). For many applications this
switch bounce may be ignored, but in digital circuits the repeated ones and zeros
occurring after a switch is closed, will be recognised as additional switching

Fig. 5.2.3 Typical Switch Bounce Spikes

Switch De-Bounce Circuit

The SR flip-flop is very effective in removing the effects of switch
bounce and Fig 5.2.4 illustrates how a SR flip-flop can be used to
produce clean pulses using SWI, which is a break before make
changeover switch. When SW1 connects the upper contact to 0V, the
S input changes from logic 1 to logic 0 and R is pulled up to logic 1 by

As soon as S is at logic 0, (at time a in Fig. 5.2.4) output Q will be at

logic 1 and any further pulses due to switch bounce will be ignored.

When SW1 is switched to the lower contact, there will be a short time
(between times b and c in Fig. 5.2.4) when neither S or R is
connected to 0V. During this time S returns to logic 1, therefore both
inputs will be at logic 1 until time c, when SW1 connects R to 0V and
Fig. 5.2.4 SR Flip-flop Switch De-Bouncing Circuit
Q is reset to logic 0 completing the output pulse. The use of a break
before make rather than a make before break switch is important, as
it ensures that during the changeover period (time b to time c in Fig. 5.2.4) both inputs are at logic 1 rather than the non-allowed state
where both inputs would be logic 0. This ensures that outputs Q and Q are never at the same logic state.

Although, during the change over of SW1 both inputs are at logic 1, this does not produce the indeterminate state described in Table
5.2.1, as one or other of the inputs is always at logic 0 before both inputs become logic 1.

The RS Latch
Flip-flops can also be considered as latch circuits due to them remembering or
latching a change at their inputs. A common form of RS latch is shown in Fig.
5.2.5. In this circuit the S and R inputs have now become S and R inputs,
meaning that they will now be active high.

They have also changed places, the R input is now on the gate having the Q
output and the S input is on the Q gate. These changes occur because the circuit
is using NOR gates instead of NAND. Fig. 5.2.5 High Activated RS Latch
RS Latch Truth Table (Table 5.2.2)
1. Q is set to 1 when the S input goes to logic 1.
2. This is remembered on Q after the S input returns to logic 0.
3. Q is reset set to 0 when the R input goes to logic 1.
4. This is remembered on Q after the R input returns to logic 0.
5. If both inputs are at logic 1, Q is the same as Q (the
non-allowed state).
6. The state of the outputs cannot be guaranteed if the
inputs change from 1,1 to 0, 0 at the same time.

Timing Diagrams

Truth tables are not always the best method for describing the action of
a sequential circuit such as the SR flip-flop. Timing diagrams, which
show how the logic states at various points in a circuit vary with time,
are often preferred.

Fig. 5.2.6 RS Latch Timing Diagram

Fig. 5.2.6 shows a timing diagram describing the action of the basic RS Latch for logic changes at R and S. At time (a) S goes high
and sets Q, which remains high until time (b) when S is low and R goes high, resetting Q. During period (c) both S and R are high
causing the non-allowed state where both outputs are high. After period (c) Q remains high until time (d) when R goes high, resetting
Q. Period (e) is another non-allowed period, at the end of which both inputs go low causing an indeterminate output condition in period

The Clocked SR Flip-flop

Fig. 5.2.7 shows a useful variation on the basic SR flip-flop, the clocked SR flip-flop. By adding two extra NAND gates, the timing of the
output changeover after a change of logic states at S and R can be controlled by applying a logic 1 pulse to the clock (CK) input. Note
that the inputs are now labelled S and R indicating that the inputs are now high activated. This is because the two extra NAND gates
are disabled while the CK input is low, therefore the outputs are completely isolated from the inputs and so retain any previous logic
state, but when the CK input is high (during a clock pulse) the input NAND gates act as inverters. Then for example, a logic 1 applied to
S becomes a logic 0 applied to the S input of the active low SR flip-flop second stage circuit.

The main advantage of the CK input is that the output of this flip-flop can now
be synchronised with many other circuits or devices that share the same
clock. This arrangement could be used for a basic memory location by, for
example, applying different logic states to a range of 8 flip-flops, and then
applying a clock pulse to CK to cause the circuit to store a byte of data.

The basic form of the clocked SR flip-flop shown in Fig. 5.2.7 is an example
of a level triggered flip-flop. This means that outputs can only change to a
new state during the time that the clock pulse is at its high level (logic 1). The
ability to change the input whilst CK is high can be a problem with this
circuit, as any input changes occurring during the high CK period, will also
Fig. 5.2.7 High Activated Clocked SR Flip-flop
change the outputs. A better method of triggering, which will only allow the
outputs to change at one precise instant is provided by edge triggered devices available in D Type and JK flip-flops.

SR Flip-flop ICs
Comprising just two gates, low activated SR flip-flops are simple to implement using standard NAND gates but active low SR flip-flops
(called SR flip-flops) are available as Quad packages in the LS TTL family as 74LS279 from Texas Instruments.

Circuit Symbols for Flip-flops

Rather than drawing the schematic circuit for individual gate versions
of flip-flops it is common to draw them in block form. Some commonly
used block versions of SR and RS flip-flops are shown in Fig. 5.2.8.

Fig. 5.2.8 SR Flip-flop Circuit Symbols

Top of Page
2007 2016 Eric Coates MA BSc. (Hons) All rights reserved. (Revision 8.00 31 March 2016)