JTAG Principles and

Interface
 JTAG
JTAG is the name used for the IEEE 1149.1
standard entitled Standard Test Access Port
and BoundaryScan Architecture for test access
ports (TAP) used for testing printed circuit
boards (PCB) using boundary scan.
JTAG is the acronym for Joint Test Action
Group, the name of the group of people that
developed the IEEE 1149.1 standard.
 Functionality
Debug Access is used by debugger tools to
access the internals of a chip making its
resources and functionality available and
modifiable, e.g. registers, memories and the
system state.
Boundary Scan is used by hardware test tools
to test the physical connection of a device, e.g.
on a PCB.
Storing firmware is used to transfer data into
internal non-volatile device memory.
 Versions
Daisy-chained JTAG (IEEE 1149.1)
The connector pins are
TDI (Test Data In)
TDO (Test Data Out)
TCK (Test Clock)
TMS (Test Mode Select)
TRST (Test Reset) optional.
 Versions
Reduced pin count JTAG (IEEE 1149.7)
Reduced pressure on the number of pins
Devices can be connected in a star topology.
The connector pins are
TMSC (Test Serial Data)
TCK (Test Clock)
 JTAG System Test

TAP TAP
Control Control
TAP

TDI
TCK
TMS
TRST
TDO
 Extra JTAG Logic

Boundary-Scan
Cell Test Registers
and Decoder

TAP
Controller

TAP
Control

Package Pin Test Access Port

(TAP)
Test Access Port
(TAP)
 TAP Pin Descriptions I

Test Clock Input (TCK)

Independent of the system clock.
Rising edge used to load signals applied at the TAP
input pins (TDI,TMS).
Falling edge used to clock data out of the TAP data
output (TDO).

Test Mode Select (TMS)

Test logic operation determined by input sequence on
this pin.
In undriven state, TMS should be a logic 1.

Test Data Input (TDI)

Serial test data applied at this input.
Again, should be pulled up to logic 1 when undriven.
 TAP Pin Descriptions II

Test Data Output (TDO)

Serial data out.
When there is no shift activity, TDO is set to a high-
impedence state.

Test Reset (TRST)

TAP controller can be initialised via TCK and TMS.
Optional TRST pin allows reset independently of TCK
and TMS.
Pulling TRST to 0 asynchronously forces the test logic
into its reset state.
Additional signals for debugging

VTREF
It indicates if the target power is applied, it is
used to create the logic-level reference
(VTREF/2) for the debugger input comparators
and it auto adjusts the voltage levels of the
debugger output driver.

VSUPPLY
Voltage Supply is used by some debug tools to
draw it's supply current.

RTCK
Return Test Clock can be used to synchronize
the JTAG signals to internal clocks.
 Additional signals for debugging
SRST:
System Reset (low active) is used to reset the target
system.
DBGRQ:
Debug Request (high active) is an output of the debugger
to cause the processor to enter debug mode (to halt the
processor).
DBGACK:
Debug Acknowledge (high active) is an input of the
debugger to sense the processors halt status.
 AC characteristics
Data on TDI and TMS will be sampled with the
rising edge of TCK.
TDO will change on the falling edge of TCK.
 Frequency
The maximum operating frequency of TCK varies depending on all
chips in the chain (the lowest speed must be used), but it is
typically 10-100 MHz.
Also TCK frequencies depend on board layout and JTAG adapter
capabilities and state. One chip might have a 40 MHz JTAG clock,
but only if it is using a 200 MHz clock for non-JTAG operations;
and it might need to use a much slower clock when it is in a low
power mode. Accordingly, some JTAG adapters have adaptive
clocking using an RTCK (Return TCK) signal.
Faster TCK frequencies are most useful when JTAG is used to
transfer lots of data, such as when storing a program executable
into flash memory.
TAP Architecture
TAP Control State Machine
 Controller States I

TEST-LOGIC-RESET
Test logic disabled; allows for normal chip operation.

RUN-TEST-IDLE
Controller state between scan operations.

SELECT-DR/IR-SCAN
Temporary controller states in which all test data
registers selected by the current instruction retain their
current state.
Initiates register scan sequence.

CAPTURE-DR
The selected test data register captures its data inputs
on the rising edge of TCK.
 Controller States II

CAPTURE-IR
The instruction register loads a fixed bit pattern on
rising TCK.

SHIFT-DR/IR
In these states the test data register (DR) or the
instruction register (IR), shifts its data by one stage on
each rising edge of TCK.

EXIT1-DR/IR
These are temporary controller states. If TMS = 1,
then on the next rising TCK, the state machine will
enter the Update-DR/IR states.

UPDATE-DR
Some test data registers have latched parallel outputs.
These outputs are latched on falling TCK
 Controller States III

UPDATE-IR
On TCK falling the instruction shifted in during SHIFT-
IR is latched into the instruction register.

PAUSE-DR/IR
These states allow for the instruction/data shift
operations to be halted temporarily.

EXIT2-DR/IR
Temporary controller states allowing either resumption
of or termination of the current scan instruction.
 TAP Instructions I

SCAN_N (0010)
Connects the Scan Path Select Register between TDI
and TDO.
Selects scan chain for subsequent test operations.

EXTEST (0000)
Allows for testing of external logic.
During SHIFT-DR scanned-in data is applied
immediately to the system.

INTEST (1100)
Allows for testing of internal logic.
 TAP Instructions II

IDCODE (1110)
Connects device identification register between TDI
and TDO.

BYPASS (1111)
Connects a single stage shift register between TDI
and TDO.
Allows testing of individual devices to take place.

CLAMP (0101)
Connects a single stage shift register between TDI
and TDO.
Output signals are defined by values previously
loaded into the currently selected scan chain.
 TAP Instructions III

HIGHZ (0111)
Connects a single stage shift register between TDI
and TDO.
All outputs are forced to high impedance state.

CLAMPZ (1001)
Connects a single stage shift register between TDI
and TDO.
All tri-state outputs are inactive, but data supplied to
outputs is derived from the scan cells.

SAMPLE/PRELOAD (0011)
Selects the boundary scan register as DR, and
samples or preloads the chip I/Os.
Identifying JTAG connector using
headers
10 Pin Header
12 Pin Header
14 Pin Header
16 Pin Header
 References
http://www2.lauterbach.com/pdf/training_jtag.pd
f
http://www2.lauterbach.com/pdf/arm_app_jtag.p
df
http://en.wikipedia.org/wiki/Joint_Test_Action_
Group