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514 Aufrufe4 SeitenReal Time Implementation on FPGA of an OFDM based Wireless LAN modem [http://bbwizard.com]

Jul 05, 2010

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Real Time Implementation on FPGA of an OFDM based Wireless LAN modem [http://bbwizard.com]

Attribution Non-Commercial (BY-NC)

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514 Aufrufe

Real Time Implementation on FPGA of an OFDM based Wireless LAN modem [http://bbwizard.com]

Attribution Non-Commercial (BY-NC)

Als PDF, TXT **herunterladen** oder online auf Scribd lesen

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- 15074150-DESIGN-AND-IMPLEMENTATION-OF-OFDM-TRANSMITTER-AND-RECEIVER-ON-FPGA-HARDWARE.pdf
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extended with Adaptive Loading

Steven Thoen

Imec vzw, DESICS, Kapeldreef 75,B-3001 Heverlee,Belgium

Maryse.Wouters@imec.be

One means to increase the capacity of wireless LAN is

Future wireless applications target multimedia and applying adaptive loading on top of the OFDM

high-speed internet access, all requiring techniques to modulation. Simulations [2] show that a gain of 6 dB is

improve the link capacity and robustness. For wireless achieved at BER of 10-2 and even better improvement is

Local Area Network (LAN) the standards have chosen achieved at higher Eb/N0. In the study done in [2] the

orthogonal frequency division multiplex (OFDM) as Fischer et al [3] algorithm is selected because of its low

modulation scheme. An extension beyond the standards computational complexity and its similar performance

to improve the link capacity is adaptive loading. This compared to other algorithms. This paper presents the

paper presents the implementation aspects of an OFDM implementation aspects of the adaptive loading algorithm

based wireless LAN modem together with adaptive and its integration with the OFDM baseband modem.

loading on field programmable gate array (FPGA). The The OFDM modem is modeled in high level fixed

FPGA implementation of the wireless LAN modem point C++ dataflow and in VHDL register transfer. A

enhances rapid prototyping and allows flexible simulation environment is set up with automatic

integration of extensions to improve the quality of comparison checks.

service. Implementation results are given and a A generic demonstration platform is proposed on

comparison is made with an ASIC implementation of the which the OFDM based wireless LAN modem is

modem. The wireless LAN system will be demonstrated evaluated.

on a generic platform that is developed for prototyping The next sections describe details of the modem

and demonstration of high speed communication architecture, the FPGA specific design aspects, the design

systems. flow and the implementation complexity comparison

between ASIC and FPGA implementation. In the last

1. Introduction section an overview of the demonstration platform is

given.

The standards IEEE.802.11a and Hiperlan-2 have

chosen for the upcoming broadband wireless LAN 2. Principles of OFDM and Adaptive

systems OFDM as modulation scheme because of its Loading

good performance for frequency selective channels in the

5 GHz band. The maximum data rate of 72 Mbit/sec in a The indoor propagation channel for wireless LAN

20 MHz bandwidth requires spectrally efficient coding applications is frequency selective due to multi-path

schemes up to QAM-64. IMEC was one of the first to fading. The link between transmitter and receiver is often

implement a broadband OFDM baseband modem [1] on a non-line of sight link. OFDM exploits the frequency

an Application Specific Integrated Circuit (ASIC). This diversity by partitioning the bandwidth in narrow sub-

modem contains all functionality that is needed for bands each seeing a flat fading channel. Each sub-band is

OFDM burst transmission and for robust OFDM PSK or QAM modulated.

reception in a multi-path environment. The architecture Given the dips in the channel (see Figure 2) and

of the ASIC is optimized for low power. The ASIC is OFDM as modulation scheme adaptive bit loading on the

highly programmable to adapt for different services and sub-carriers results in an improvement of the capacity

environments. In this paper we present the design aspects usage of the channel. By measurement of the channel and

to map the OFDM modem on a FPGA. by identification of the dips and peaks, an optimal bit

The implementation on flexible hardware allows the loading over the sub-carriers can be calculated for

addition of new functionality to the OFDM modem in transmission. The Fischer et al algorithm distributes the

531

Authorized licensed use limited to: UNIVERSITY OF WESTERN ONTARIO. Downloaded on April 3, 2009 at 11:23 from IEEE Xplore. Restrictions apply.

bits (Rt) over the different sub-carriers (D) in order to guard. A simple equalisation can be implemented in

minimise the bit error rate (BER) at a constant total bit frequency domain by a one tap equalizer per subcarrier.

rate and transmit power. The bit assignment is given by: The equalizer performance is improved by adaptive

D

remaining frequency offset. The channel estimation is

Ri = + log 2 ( l =1 D )

D D Ni done on a known symbol.

with N the equivalent channel power. The bit assignment Resource sharing between the transmitter and receiver

has to be done recursively since R can become negative chain is exploited for the (I)FFT and the data reordening

and those carriers have to be excluded. tasks. A clock strategy for power optimisation is

implemented by disabling the clocks of non active

processes. This gives a significant average power saving

for the receiver when it is listening to an incoming signal.

3. Transceiver Architecture

3.2 Adaptive Loading Unit

The transceiver architecture (Figure 1) contains three

main functional blocks: The adaptive loading unit at the receiver takes the

1. OFDM (de)modulator channel estimate of the equalizer as input to calculate the

2. adaptive loading unit equivalent channel power on the sub-carriers and to

3. debug and data analysis unit recursively calculate the bit loading until the target bit

acquisition sequence

rate is obtained. Figure 2 shows the channel profile, the

TX_data mapper symbol DAC

estimated channel profile by the adaptive equalizer and

(I)FFT

TX_mod spectral shaping re-ordering the optimal bit loading calculated by the adaptive loading

guard insertion unit.

0.6 estimated channel after adaptive interpolation

memory for Adaptive Equalizer guard removal, true channel

Debug_data 0.5

data analysis coarse channel clock offset tracking

channel power

estimator 0.4

Adaptive Loading

tracking adaptive channel estim./comp.

interpolator 0.2

sub-carrier power

estimation symbol timing, ADC 0.1

divider gain estimator

0

0 5 10 15 20 25 30 35 40 45 50

recursive carrier index

bit assignment

demapper, MPI

soft/hard 4

3

Bit_loading Channel_estimate RX_data µproc_interface

bit loading

0 5 10 15 20 25

carrier index

30 35 40 45 50

derived from the architecture of its ASIC Figure 2 Indoor frequency channel response

implementation. It is built of processes that operate and corresponding bit loading

stand-alone and that are activated by data tokens.

In the transmitter the data bits are mapped on Nc The execution time of the algorithm should be

parallel signals with a programmable bit loading for each minimised and should be at least less than two OFDM

individual signal (0,1,2,4,6). It is then modulated on Nc

symbols (8 µs). The inputs for the algorithm are

parallel orthogonal carriers by means of an IFFT and a

generated serially at a clock rate of 20 MHz. Therefore,

guard is added to create a OFDM symbol. For

the first part of the algorithm, calculating the channel

synchronisation purposes a preamble is inserted at the

power and the logarithm, is also done serially at 20 MHz.

start of a burst.

The remainder of the algorithm, i.e. the recursive bit

The receiver performs basically the inverse of the

loading, is implemented fully parallel. The maximum

transmitter and does synchronisation in time and

execution time of the adaptive loading implementation is

frequency domain. The timing and the coarse frequency

determined by simulating the bit loading for 10000

acquisition are done in a feed forward way before the

Hiperlan-2 channels. This results in a maximum

FFT. The start of a burst is detected by power

execution time of 4.25 µs for the recursive bit loading

measurements and repeated correlation peak detection.

implementation clocked at 40 MHz and in a maximum

The frequency offset is determined by correlation of two

known sequences. The frequency offset compensation execution time of 5.75 µs for the recursive bit loading

before the FFT reduces the inter-carrier interference. implementation clocked at 20 MHz.

Clock offset tracking is performed by correlation on the The fixed point implementation gives an extra signal

to noise loss in the BER performance curve. The BER

532

Authorized licensed use limited to: UNIVERSITY OF WESTERN ONTARIO. Downloaded on April 3, 2009 at 11:23 from IEEE Xplore. Restrictions apply.

performance curve, done on 10000 Hiperlan-2 channels, as the buffered AND gate. In this way a power optimised

is shown in Figure 3 for the register transfer VHDL implementation is realised of the OFDM modem on the

implementation. The signal to noise implementation loss FPGA.

is 0.09 dB at the bit error rate of 10-5 compared with the The mapping on the FPGA did give timing violations

floating point Fischer algorithm. for some functional units. This was the case in the

equalizer where additional pipeline registers are added in

0

10 floating point

fixed point

the divider and in the datapath of the channel estimator

qpsk

10

−1

and interpolator.

−2

10

10

−3

5. Design Flow

−4

10

The OFDM (de)modulator is described as a high level

BER

−5

10

dataflow model in C++ using the OCAPI [5] hardware

−6

10

libraries. Algorithmic exploration, performance

10

−7

simulations and fixed point refinement are done on this

10

−8

model. The C++ dataflow model is further refined to a

10

−9 C++ description of combined finite state machine and

datapath (FSMD). From this description the VHDL code

0 5 10 15 20

EsNo (dB)

25 30 35 40

is automatically generated. The channel is modelled in

C++ dataflow with programmable frequency offset,

Figure 3: BER comparison for the fixed point timing offset, noise insertion, multi-path channel and up-

register transfer and the floating point Fischer and down-sampling filter.

algorithm The VHDL register transfer model of the adaptive

loading unit is manually written. The interface between

3.3 Debug and Data Analysis Unit

the OFDM (de)modulator and the adaptive loading unit

Memory is allocated to store debug data and channel is written in VHDL.

measurements. This data can be processed and analysed A simulation environment is defined to test the OFDM

off line. The following data can be stored in memory: modem whereby an automatic comparison check is done

• a OFDM burst of 2 ms at 20 MHz sampling rate on the internal signals and on the output signals between

at the transmitter output (DAC) and receiver input the fixed point C++ dataflow model and the VHDL

(ADC) netlist.

• channel estimations for channel profiling

• internal signals of the OFDM modem for debug 6. Implementation Results

purposes

The XilinX Virtex2 family is selected as target FPGA

4. Adaptations for FPGA implementation for the mapping of the OFDM modem extended with

adaptive loading. The design did not fit into the

The register transfer VHDL netlist of the OFDM XC2V3000 FPGA because the number of available

modem, that is optimised for low power consumption and multipliers is lower than the required number and this

ASIC implementation, is used as basic netlist for leads to an inefficient implementation of the remaining

mapping on a XilinX Virtex-2 FPGA [4]. The multipliers on the slices. The implementation figures for

adaptations required for FPGA implementation are FPGA are summarised in Table 1 and for ASIC

related to the clock distribution network and the timing implementation in Table 2. The FPGA implementation

constraint of 50 ns. has as extra functionality the adaptive loading unit and

The FPGA Digital Clock Manager (DCM) with PLL is the memory (1.25 Mbit) for off line data analysis.

used to derive the main internal clock at 20 MHz out of Remark that the equalizer takes besides 36.2 % of the

the external input clock at 40 MHz. The DCM installs a slices also 79% of the multipliers.

zero phase delay between the internal and external clock

and this allows to use a FIFO interface operating on the

clock edges to transfer transmit data (TX_data) and

received data (RX_data). The ASIC implementation is

optimised for power consumption by disabling the main

internal clock when a functional unit is not operational.

This derived clock is the output signal of a buffered AND

gate with the main internal clock and the control enable

signal as input signals. In inactive mode the derived clock

is low. On FPGA the derived clocks are implemented

with a BUFGCE clock buffer that has the same behaviour

533

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Table 1. FPGA key figures of OFDM modem

with adaptive loading

FPGA XC2V6000

Internal main clock 20 MHz

Slices 16167 = 47,8 % usage

- active in reception 15309 = 94.7 %

- active in transmission 2650 = 16.4 %

- of which equalizer 5862 = 36,2 %

Figure 4: Demonstration Platform for high speed

- of which fft 1963 = 12,1%

telecommunication systems, e.g wireless LAN

- of which ad. loading 4103 = 25,4%

system

Multipliers 124 = 86% usage

- of which in equalizer 98 = 79%

- of which in fft 8 = 6.4% 8. Conclusions

Block RAM 81 = 56.2 % In this paper, the implementation on FPGA of a

- of which functional 8 = 9.8% broadband OFDM modem, which achieves data rates up

- of which data analysis 73 = 90 % to 72 Mbit/sec, is presented. It contains all functionality

for (de)modulation, e.g. synchronisation and frequency

Table 2: ASIC key figures of OFDM modem domain equalisation, and also contains adaptive loading

to improve the capacity usage. Imec has developped an

Technology CMOS 0.18 µm OFDM (de)modulator ASIC. The register transfer netlist

1.8 V core, 3.3 V I/O of the ASIC, which is optimised for power consumption,

clock 20 MHz is used as basic netlist for FPGA mapping. Modifications

Equ. Gate count (core) 431000 = 100.0 % needed to be done on the clock distribution network to

- active in reception 416000 = 96.7 % disable clocks of non active processes for power

- active in transmission 79000 = 18.4 % optimisation. Extra pipeline registers are added in the

- of which equalizer 270000 = 62.6 % FPGA implementation to meet the timing constraints.

- of which fft 42000 = 9.7% The implementation takes 48% of the slices and 86% of

- of which RAMs 78000 = 18.1% the multipliers in a XC2V6000 FPGA. The adaptive

Die Size 20.8 mm2 loading takes 25% of the slices of the OFDM modem and

gives a performance improvement of 6 dB at BER of 10-2

A generic platform for high speed systems is proposed

on which the wireless LAN system will be demonstrated.

7. Demonstration Platform

We have defined generic platform concepts [6] to 8. References

enable reuse of modular hardware and of Linux driver

development software. The hardware concepts feature [1] W. Eberle et al, “A Digital 80 Mb/s OFDM

dedicated high-speed inter-board data links, flexible transceiver IC for Wireless LAN in the 5 GHz Band”,

configurable hardware, integration of Intellectual IEEE International Solid_State Circuits Conference,

Property (IP) cores and built-in debug facilities. The San Francisco, California, February 2000

boards are Compact PCI compliant and can be plugged in [2] L. Van der Perre, S. Thoen, P. Vandenameele,

a standard shelf to build a system. The wireless LAN “Adaptive loading strategy for a high speed OFDM-

system will be demonstrated on this platform (see Figure based WLAN”, IEEE Globecom ‘98, Sydney, Australia,

4) for which two boards are developed. One board is a November 1998, pp 1936-1940

general purpose board with two XilinX Virtex2 family [3] R.F.H. Fischer, and J.B. Huber, “A New Loading

FPGAs for implementation of the application specific Algorithm for Discrete Multitone Transmission”, IEEE

cores. The OFDM modem with adaptive loading is Proc. GLOBECOM ’96, London, England, November

mapped on a XC2V6000 FPGA. The second board 1996, pp. 724-728

contains one XilinX Virtex2 family FPGA and a socket [4] http://www.xilinx.com/

to mount a front-end daughter board. The automatic gain [5] P. Schaumont, S. Vernalde, L. Rijnders, “A design

control (AGC) and intermediate frequency up- and down environment for the design of complex high-speed

conversion is implemented on the FPGA. For the real ASICs”, Proc. 35th Design Automation Conf., June 1998,

time demonstration of the wireless LAN system, the pp. 609-618

communication of payload data between the boards is [6] M. Wouters, T. Huybrechts, R. Huys, S. De Rore,

managed via high speed data links with a capacity of 1.4 S. Sanders, E. Umans, ”PICARD: Platform Concepts for

Gbit/sec per link. Prototyping and Demonstration of High Speed

Communication Systems”, Rapid System Prototyping

’02, Darmstadt, Germany, July 2002

534

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