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VLSI (B.Tech.)
S.N
O Projects Titles Type
Front End(Verilog HDL/VHDL)
1 An Optimized Design of Area efficient FAM for Real time Arithmetic operations IEEE

Video Objects Motion Estimation Architecture using Adaptive Rood Pattern

2 IEEE
Search(ARPS) Algorithm
3 A Nano-Transmitter design for Ultra-Wide Band Communications IEEE

4 A Low-power Variable-length FFT Processor Base on Radix-24 Algorithm IEEE

5 Smart Games applicable Parallel Radix-Sort-based VLSI architecture IEEE

6 Design and implementation of efficient Quaternary Signed Digit Multiplier IEEE

7 3D Pilot Pattern based MIMO-OFDM System for Telecommunications IEEE

8 Area-Delay Efficient Binary Adders in QCA IEEE

Low power VLSI architecture for adaptive filter and its application to noise
9 IEEE
cancellation
10 Differential Scan-Path: A Novel Solution for Secure Design-for Testability IEEE

11 FIR Filter Design Based on Faithfully Rounded Truncated MCM IEEE

12 Implementation of JPEG2000 using DWT IEEE

13 FPGA implementation of multi operand redundant adders IEEE

14 Multi bit Flip-Flop design for Area efficiency IEEE

15 MDC FFT/IFFT Processor With Variable Length IEEE

16 Built in generation of functional broadside tests using a fixed hardware structure IEEE

17 Constant and high speed adder design using QSD number system IEEE

18 Digital-Serial FIR Filter Algorithms, Architecture and a CAD Tool IEEE

19 A Common Boolean Logic(CBL) implementation for modified CSLA IEEE

20 High speed Vedic multiplier using barrel shifter IEEE

Ph.no:9985827707 E-mail:vstechnosolutions7@gmail.com
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Bar Code Reader(RFID Gun) with Reliable and Higher Throughput Anti-Collision
21 IEEE
Technique
A new approach to design fault coverage circuit with efficient hardware utilization
22 IEEE
for testing applications
23 Design of Parallel Carry-Save Pipelined RSFQ Multiplier IEEE

24 Single phase clock distribution using VLSI technology for low power IEEE
A VLSI architecture for video object motion estimation using a 2D hierarchical
25 IEEE
mesh model
26 High Speed FPGA implementation of FIR Filters for DSP Applications IEEE
Design and implementation of Floating Point Multiplier based on Vedic
27 IEEE
Multiplication Technique
28 A Novel Approach for parallel CRC generation FOR High Speed Application. IEEE

29 High speed Modified Booth Encoder multiplier for signed and unsigned numbers. IEEE

Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA
30 IEEE
Implementation.
Efficient VLSI Implementation of DES and Triple DES Algorithm with Cipher
31 IEEE
Block Chaining concept using Verilog and FPGA
32 Implementation of an Efficient Multiplier based on Urdhva Tiryakbhyam Sutra IEEE

33 A Floating point Fused Dot Product Unit IEEE

34 Implementation of Power Efficient Vedic Multiplier using DBNS IEEE

35 LUT Optimization for Memory-Based Computation IEEE

Area Efficient parallel FIR Digital Filter Structures for Symmetric Convolution
36 IEEE
based on Fast FIR Algorithm
37 Measurement and evaluation of power analysis attacks on Asynchronous S-Box. IEEE

38 High Speed Booth Encoded Multiplier to Minimize the Computation time IEEE

39 Design Of Area Optimized AES 128 Algorithm Using Mix column Transformation. IEEE

40 VLSI design Of a Digital Clock Using GALS Technique IEEE

41 Efficient Weighted Pattern Generation Technique with Low Hardware Overhead IEEE

42 SCA-FF and SCAh-FF design for single cycle access test IEEE

43 Design and implementation of a high performance multiplier using HDL IEEE

A VLSI Implementation of Modulo Multiplier By Using Radix-8 Modified Booth
44 IEEE
Algorithm
45 Platform-Independent Customizable UART Soft-Core IEEE
A Parallel Multiplier Accumulator Based On Radix 4 Modified Booth Algorithms
46 IEEE
by Using Spurious Power Suppression Technique

Ph.no:9985827707 E-mail:vstechnosolutions7@gmail.com
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47 Using Self-Immunity Technique 64-bit Register File Immunity Improvement IEEE

48 A Novel Nanometric Parity Preserving Reversible Vedic Multiplier IEEE

High Speed 3D DWT VLSI Architecture for Image Processing Using Lifting Based
49 IEEE
wavelet Transform
50 Pulse Triggered Flip-Flop Design for low power IEEE

Back End(Schematics & Layouts)

Design of Secure Differential Logic Gates for DPA Resistant Circuits for High-
51 IEEE
Secure Applications
52 Pulse Triggered Flip-Flop Design for low power IEEE
Comparative analysis and optimization of active power and delay of 1-bit full adder
53 IEEE
at 45nm technology
54 Statistical Analysis of MUX-Based Physical Unclonable Functions IEEE

55 Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator IEEE

56 Realization of Basic Gates Using MUX in CMOS Design IEEE

57 Digitally Controlled Pulse Width Modulator for On-Chip Power Management IEEE

A Multiobjective Optimization Based Fast and Robust Design Methodology for Low
58 IEEE
Power and Low Phase Noise Current Starved VCO
59 Area Efficient ROM-Embedded SRAM Cache IEEE
A Low Power MICS Band Phase - Locked Loop for High Resolution Retinal
60 IEEE
Prosthesis

Ph.no:9985827707 E-mail:vstechnosolutions7@gmail.com
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VLSI (B.Tech.) 2014-2015

S.N
O Projects Titles
1 High Speed FPGA implementation of FIR Filters for DSP Applications

Design and implementation of Floating Point Multiplier based on Vedic

2
Multiplication Technique

A Noval Approach for parallel CRC generation FOR High Speed

3
Application.

High speed Modified Booth Encoder multiplier for signed and unsigned
4
numbers.

Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA
5
Implementation.

Efficient VLSI Implementation of DES and Triple DES Algorithm with

6
Cipher Block Chaining concept using Verilog and FPGA

7 Implementation of an Efficient Multiplier based on Vedic Mathematics

8 A Floating point Fused Dot Product Unit

9 Implementation of Power Efficient Vedic Multiplier

10 LUT Optimization for Memory-Based Computation

Area Efficient parallel FIR Digital Filter Structures for Symmetric

11
Convolution based on Fast FIR Algorithm

Measurement and evaluation of power analysis attacks on Asynchronous S-

12
Box.

High Speed Booth Encoded Multiplier By Minimizing The Computation

13
Time

Design Of Area Optimized AES 128 Algorithm Using Mix column

14
Transformation.

15 A Secure, Low Power and Low Hardware Digital Watermarking System.

Ph.no:9985827707 E-mail:vstechnosolutions7@gmail.com
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Efficient Weighted Pattern Generation Technique with Low Hardware

16
Overhead

Low Power Design Techniques Applied to Pipelined Parallel and Iterative

17
CORDIC Design

18 Design and implementation of a high performance multiplier using HDL

A VLSI Implementation of Modulo Multiplier By Using Radix-8 Modified

19
Booth Algorithm

20 Platform-Independent Customizable UART Soft-Core

A Parallel Multiplier Accumulator Based On Radix 4 Modified Booth

21
Algorithms by Using Spurious Power Suppression Technique

22 Using Self-Immunity Technique 64-bit Register File Immunity Improvement

FPGA Implementation of Low power Digital QPSK Modulator

23

High Speed 3D DWT VlSI Architecture for Image Processing Using Lifting
24
Based wavelet Transform

25 Implementation of AMBA compliant Memory Controller on a FPGA

26 Faster and Low Power Twin Precision Multiplier

27 Design and Analysis of Low Power Parallel Prefix VLSI Adder

28 FPGA Implementation of Booths and Baugh- Wooley Multiplier

29 Implementation of Area Efficient 16bit Adder in SPARTAN-3 FPGA

Reliable and Higher Throughput Anti-Collision Technique for RFID UHF

30
Tag

31 Implementation of Bus Bridge between AHB and OCP

32 An Implementation of Open Core Protocol for the On-Chip Bus

33 Implementation of OFDM System using IFFT and FFT

Ph.no:9985827707 E-mail:vstechnosolutions7@gmail.com
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An Efficient FPGA implementation of Double Precision floating Point

34
Multiplier

35 FPGA Based High Speed Parallel Cyclic Redundancy Check

High speed carry save multiplier based linear convolution using Vedic
36
mathematics

FPGA Implementation of 2-D DCT Architecture for JPEG Image

37
Compression

38 Performance Evaluation of Complex Multiplier Using Advance Algorithm

Design of High Speed Vedic Square by using Vedic Multiplication

39
Techniques

40 An FSM Based VGA Controller with 640480 Resolution.

41 A Verilog Model of Universal Scalable Binary Sequence Detector

Hardware modeling of binary coded decimal adder in field programmable

42
gate array

43 Low powers add and shift multiplier design BZFAD architecture

44 A High Throughput Fixed point Complex divider for FPGAs

Design and Implementation of Two Variable Multiplier Using KCM and

45
Vedic Mathematics.

Ph.no:9985827707 E-mail:vstechnosolutions7@gmail.com