Superscalar processor

While a superscalar CPU is typically also pipelined,

pipelining and superscalar execution are considered dif-
ferent performance enhancement techniques. The former
executes multiple instructions in the same execution unit
in parallel by dividing the execution unit into dierent
phases, whereas the latter executes multiple instructions
in parallel by using multiple execution units.
The superscalar technique is traditionally associated with
several identifying characteristics (within a given CPU):

Instructions are issued from a sequential instruction

Simple superscalar pipeline. By fetching and dispatching two in-
structions at a time, a maximum of two instructions per cycle can
be completed. (IF = Instruction Fetch, ID = Instruction Decode,
EX = Execute, MEM = Memory access, WB = Register write
back, i = Instruction number, t = Clock cycle [i.e., time])
stream
The CPU dynamically checks for data dependen-
cies between instructions at run time (versus soft-
ware checking at compile time)
The CPU can execute multiple instructions per clock
cycle

1 History
Seymour Cray's CDC 6600 from 1966 is often mentioned
as the rst superscalar design. The Motorola MC88100
(1988), the Intel i960CA (1989) and the AMD 29000-
series 29050 (1990) microprocessors were the rst com-
Processor board of a CRAY T3e supercomputer with four super-
mercial single-chip superscalar microprocessors. RISC
scalar Alpha 21164 processors microprocessors like these were the rst to have super-
scalar execution, because RISC architectures frees tran-
A superscalar processor is a CPU that implements a sistors and die area which could be used to include mul-
tiple execution units (this was why RISC designs were
form of parallelism called instruction-level parallelism
within a single processor. It therefore allows for more faster than CISC designs through the 1980s and into the
1990s).
throughput (the number of instructions that can be exe-
cuted in a unit of time) than would otherwise be possible Except for CPUs used in low-power applications,
at a given clock rate. A superscalar processor can exe- embedded systems, and battery-powered devices, essen-
cute more than one instruction during a clock cycle by tially all general-purpose CPUs developed since about
simultaneously dispatching multiple instructions to dif- 1998 are superscalar.
ferent execution units on the processor. Each execution The P5 Pentium was the rst superscalar x86 proces-
unit is not a separate processor (or a core if the proces- sor; the Nx586, P6 Pentium Pro and AMD K5 were
sor is a multi-core processor), but an execution resource among the rst designs which decode x86-instructions
within a single CPU such as an arithmetic logic unit. asynchronously into dynamic microcode-like micro-op
In Flynns taxonomy, a single-core superscalar proces- sequences prior to actual execution on a superscalar
sor is classied as an SISD processor (Single Instruction microarchitecture; this opened up for dynamic scheduling
stream, Single Data stream), though many superscalar of buered partial instructions and enabled more paral-
processors support short vector operations and so could lelism to be extracted compared to the more rigid meth-
be classied as SIMD (Single Instruction stream, Mul- ods used in the simpler P5 Pentium; it also simplied
tiple Data streams). A multi-core superscalar processor speculative execution and allowed higher clock frequen-
is classied as an MIMD processor (Multiple Instruction cies compared to designs such as the advanced Cyrix
streams, Multiple Data streams). 6x86.

1
2 4 ALTERNATIVES
2 Scalar to superscalar
The simplest processors are scalar processors. Each in-
struction executed by a scalar processor typically manip-
ulates one or two data items at a time. By contrast, each
instruction executed by a vector processor operates simul-
taneously on many data items. An analogy is the dif-
ference between scalar and vector arithmetic. A super-
scalar processor is a mixture of the two. Each instruction
processes one data item, but there are multiple execution
units within each CPU thus multiple instructions can be
processing separate data items concurrently.
Superscalar CPU design emphasizes improving the in-
struction dispatcher accuracy, and allowing it to keep the
multiple execution units in use at all times. This has be-
come increasingly important as the number of units has
increased. While early superscalar CPUs would have two
ALUs and a single FPU, a modern design such as the
PowerPC 970 includes four ALUs, two FPUs, and two
SIMD units. If the dispatcher is ineective at keeping
all of these units fed with instructions, the performance
of the system will be no better than that of a simpler,
cheaper design.
A superscalar processor usually sustains an execution rate
in excess of one instruction per machine cycle. But
merely processing multiple instructions concurrently does
not make an architecture superscalar, since pipelined,
multiprocessor or multi-core architectures also achieve
that, but with dierent methods.
In a superscalar CPU the dispatcher reads instructions
from memory and decides which ones can be run in par-
allel, dispatching each to one of the several execution
units contained inside a single CPU. Therefore, a super-
scalar processor can be envisioned having multiple par-
allel pipelines, each of which is processing instructions
simultaneously from a single instruction thread.
3 Limitations
Available performance improvement from superscalar
techniques is limited by three key areas:
1. The degree of intrinsic parallelism in the instruc-
tion stream (instructions requiring the same compu-
tational resources from the CPU).
2. The complexity and time cost of dependency check- core computing.
ing logic and register renaming circuitry
3. The branch instruction processing.
Existing binary executable programs have varying de-
grees of intrinsic parallelism. In some cases instructions instructions.
are not dependent on each other and can be executed si- Simultaneous multithreading, often abbreviated as SMT,
multaneously. In other cases they are inter-dependent: is a technique for improving the overall eciency of su-
one instruction impacts either resources or results of the perscalar processors. SMT permits multiple independent
other. The instructions a = b + c; d = e + f can be run
in parallel because none of the results depend on other
calculations. However, the instructions a = b + c; b = e
+ f might not be runnable in parallel, depending on the
order in which the instructions complete while they move
through the units.
When the number of simultaneously issued instructions
increases, the cost of dependency checking increases ex-
tremely rapidly. This is exacerbated by the need to check
dependencies at run time and at the CPUs clock rate.
This cost includes additional logic gates required to im-
plement the checks, and time delays through those gates.
Research shows the gate cost in some cases may be nk
gates, and the delay cost k 2 log n , where n is the number
of instructions in the processors instruction set, and k is
the number of simultaneously dispatched instructions.
Even though the instruction stream may contain no
inter-instruction dependencies, a superscalar CPU must
nonetheless check for that possibility, since there is no
assurance otherwise and failure to detect a dependency
would produce incorrect results.
No matter how advanced the semiconductor process or
how fast the switching speed, this places a practical limit
on how many instructions can be simultaneously dis-
patched. While process advances will allow ever greater
numbers of execution units (e.g., ALUs), the burden of
checking instruction dependencies grows rapidly, as does
the complexity of register renaming circuitry to mitigate
some dependencies. Collectively the power consump-
tion, complexity and gate delay costs limit the achievable
superscalar speedup to roughly eight simultaneously dis-
patched instructions.
However even given innitely fast dependency checking
logic on an otherwise conventional superscalar CPU, if
the instruction stream itself has many dependencies, this
would also limit the possible speedup. Thus the degree
of intrinsic parallelism in the code stream forms a second
limitation.
4 Alternatives
Collectively, these limits drive investigation into alterna-
tive architectural changes such as very long instruction
word (VLIW), explicitly parallel instruction computing
(EPIC), simultaneous multithreading (SMT), and multi-
With VLIW, the burdensome task of dependency check-
ing by hardware logic at run time is removed and dele-
gated to the compiler. Explicitly parallel instruction com-
puting (EPIC) is like VLIW, with extra cache prefetching
 3

threads of execution to better utilize the resources pro- 7 External links

vided by modern processor architectures.
Superscalar processors dier from multi-core processors Eager Execution / Dual Path / Multiple Path, By
in that the several execution units are not entire proces- Mark Smotherman
sors. A single processor is composed of ner-grained ex-
ecution units such as the ALU, integer multiplier, inte-
ger shifter, FPU, etc. There may be multiple versions of
each execution unit to enable execution of many instruc-
tions in parallel. This diers from a multi-core proces-
sor that concurrently processes instructions from multiple
threads, one thread per processing unit (called core). It
also diers from a pipelined processor, where the multi-
ple instructions can concurrently be in various stages of
execution, assembly-line fashion.
The various alternative techniques are not mutually
exclusivethey can be (and frequently are) combined in a
single processor. Thus a multicore CPU is possible where
each core is an independent processor containing multiple
parallel pipelines, each pipeline being superscalar. Some
processors also include vector capability.

5 See also

Out-of-order execution

Super-threading

Simultaneous multithreading (SMT)

Speculative execution / Eager execution

Software lockout, a multiprocessor issue similar to

logic dependencies on superscalars

Shelving buer

6 References

Mike Johnson, Superscalar Microprocessor Design,

Prentice-Hall, 1991, ISBN 0-13-875634-1

Sorin Cotofana, Stamatis Vassiliadis, On the De-

sign Complexity of the Issue Logic of Superscalar
Machines, EUROMICRO 1998: 10277-10284

Steven McGeady, The i960CA SuperScalar Imple-

mentation of the 80960 Architecture, IEEE 1990,
pp. 232240

Steven McGeady, et al., Performance Enhance-

ments in the Superscalar i960MM Embedded Mi-
croprocessor, ACM Proceedings of the 1991 Con-
ference on Computer Architecture (Compcon), 1991,
pp. 47
4 8 TEXT AND IMAGE SOURCES, CONTRIBUTORS, AND LICENSES

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