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Chapter 6 Selected

Design Topics

Part 1 The Design Space

2008 Pearson Education, Inc.

(Hyperlinks are active in View Show mode)

Overview

Integrated Circuits

Levels of Integration

CMOS Circuit Technology

CMOS Transistor Models

Circuits of Switches

Fully Complementary CMOS Circuits

Technology Parameters

Part 2 Propagation Delay and Timing

Part 3 - Programmable Implementation

Technologies

Chapter 6 - Part 1 2

Integrated Circuits

Integrated circuit (informally, a chip) is a

semiconductor crystal (most often silicon)

containing the electronic components for the digital

gates and storage elements which are

interconnected on the chip.

Terminology - Levels of chip integration

SSI (small-scale integrated) - fewer than 10 gates

MSI (medium-scale integrated) - 10 to 100 gates

LSI (large-scale integrated) - 100 to thousands of gates

VLSI (very large-scale integrated) - thousands to 100s of

millions of gates

Chapter 6 - Part 1 3

MOS Transistor

0 Volts

0 Volts G (Gate) VDD Volts

S (Source) D (D rain)

Channel

length Location of

conducting

layer

Substrate

Chapter 6 - Part 1 4

MOS Transistor

V D D Volts

0 Volts G (Gate) V D D Volts

S (Source) D (D rain)

Channel

length Location of

conducting

layer

Substrate

Chapter 6 - Part 1 5

Switch Models for MOS Transistors

D

G

X

X: X:X

S

Symbol Switch M odel: Simplifed

Switch M odel

p-Channel Normally Closed (NC) Switch Contact

S

G

X X:X

X:

D

Simplified

Symbol Switch M odel

Switch M odel

Chapter 6 - Part 1 6

Circuits of Switch Models

Series

X: X

X A ND Y

Y: Y

Series

Parallel

X: X Y: Y X OR Y

Parallel

Chapter 6 - Part 1 7

Fully-Complementary CMOS Circuit

CMOS gate logic 1 +V

F using

p-type

transistors

(NC switches)

X1

X2 F using

n-type

transistors

Xn (NO switches)

logic 0

General Structure

Chapter 6 - Part 1 8

CMOS Circuit Design Example

Find a CMOS gate with the following

function: F = X Z + Y Z = (X + Y )Z

Beginning with F0, and using F

F0 Circuit: F = X Y + Z

The switch model circuit in terms of NO

switches:

X: X

Z: Z

Y: Y

Chapter 6 - Part 1 9

CMOS Circuit Design Example

The switch model circuit for F1 in terms of NC

contacts is the dual of the switch model circuit

for F0:

X : X Y: Y

Z: Z

F1 Circuit: F = (X + Y ) Z

which is the correct F.

Chapter 6 - Part 1 10

CMOS Circuit Design Example

+V

Replacing the From F 1

switch models

with CMOS

transistors;

note input

Z must be F

used. X

Z

Y

From F0

Chapter 6 - Part 1 11

Technology Parameters

Specific gate implementation technologies are

characterized by the following parameters:

Fan-in the number of inputs available on a gate

Fan-out the number of standard loads driven by a gate output

Logic Levels the signal value ranges for 1 and 0 on the inputs and

1 and 0 on the outputs (see Figure 1-1)

Noise Margin the maximum external noise voltage superimposed

on a normal input value that will not cause an undesirable change

in the circuit output

Cost for a gate - a measure of the contribution by the gate to the

cost of the integrated circuit

Propagation Delay The time required for a change in the value of

a signal to propagate from an input to an output

Power Dissipation the amount of power drawn from the power

supply and consumed by the gate

Chapter 6 - Part 1 12

Fan-out

Fan-out can be defined in terms of a

standard load

Example: 1 standard load equals the load

contributed by the input of 1 inverter.

Transition time -the time required for the

gate output to change from H to L, tHL, or

from L to H, tLH

The maximum fan-out that can be driven by

a gate is the number of standard loads the

gate can drive without exceeding its specified

maximum transition time

Chapter 6 - Part 1 13

Cost

In an integrated circuit:

The cost of a gate is proportional to the chip area

occupied by the gate

The gate area is roughly proportional to the number

and size of the transistors and the amount of wiring

connecting them

Ignoring the wiring area, the gate area is roughly

proportional to the gate input count

So gate input count is a rough measure of gate cost

If the actual chip layout area occupied by the

gate is known, it is a far more accurate

measure

Chapter 6 - Part 1 14

Overview

Part 1 The Design Space

Part 2 Propagation Delay and Timing

Propagation Delay

Delay Models

Cost/Performance Tradeoffs

Flip-Flop Timing

Circuit & System Level Timing

Part 3 - Programmable Implementation

Technologies

Chapter 6 - Part 1 15

Propagation Delay

Propagation delay is the time for a change on an input

of a gate to propagate to the output.

Delay is usually measured at the 50% point with

respect to the H and L output voltage levels.

High-to-low (tPHL) and low-to-high (tPLH) output signal

changes may have different propagation delays.

High-to-low (HL) and low-to-high (LH) transitions are

defined with respect to the output, not the input.

An HL input transition causes:

an LH output transition if the gate inverts and

an HL output transition if the gate does not invert.

Chapter 6 - Part 1 16

Propagation Delay (continued)

IN

Propagation delays measured at the midpoint

between the L and H values

What is the expression for the tPHL delay for:

a string of n identical buffers?

a string of n identical inverters?

Chapter 6 - Part 1 17

Propagation Delay Example

Find tPHL, tPLH and tpd for the signals given

IN (volts)

OUT (volts)

t (ns)

1.0 ns per division Chapter 6 - Part 1 18

Delay Models

Transport delay - a change in the output in

response to a change on the inputs occurs after

a fixed specified delay

Inertial delay - similar to transport delay,

except that if the input changes such that the

output is to change twice in a time interval less

than the rejection time, the output changes do

not occur. Models typical electronic circuit

behavior, namely, rejects narrow pulses on

the outputs

Chapter 6 - Part 1 19

Delay Model Example

A

B

A B:

No Delay

(ND) a b c d e

Transport

Delay (TD)

Inertial

Delay (ID)

0 2 4 6 8 10 12 14 16 Time (ns)

Propagation Delay = 2.0 ns Rejection Time = 1 .0 ns

Chapter 6 - Part 1 20

Circuit Delay

Suppose gates with delay n ns are

represented for n = 0.2 ns, n = 0.4 ns,

n = 0.5 ns, respectively:

Chapter 6 - Part 1 21

Circuit Delay

Consider a simple A

2-input multiplexer: 0.4

With function: 0.2

Y

Y = A for S = 1 0.5

Y = B for S = 0 S

B 0.4

A

B

S

S

Y

Glitch is due to delay of inverter

Chapter 6 - Part 1 22

Fan-out and Delay

The fan-out loading a gates output affects the

gates propagation delay

Example:

One realistic equation for tpd for a NAND gate with

4 inputs is:

tpd = 0.07 + 0.021 SL ns

SL is the number of standard loads the gate is

driving, i. e., its fan-out in standard loads

For SL = 4.5, tpd = 0.165 ns

If this effect is considered, the delay of a gate

in a circuit takes on different values depending

on the circuit load on its output.

Chapter 6 - Part 1 23

Flip-Flop Timing Parameters

ts - setup time twH $ twH,min

twL$ twL,min

th - hold time C

ts th

tw - clock S/R

pulse width tp-,min

t p-,max

tpx - propa-

Q

gation delay (a) Pulse-triggered (positive pulse)

tPHL - High-to-

twH $ t wH,min

Low

twL $ twL,min

tPLH - Low-to-C

High ts th

tpd - max (tPHLD,

tPLH) t p-,min

t p-,max

Q

(b) Edge-triggered (negative edge)

Chapter 6 - Part 1 24

Flip-Flop Timing Parameters

ts - setup time

Master-slave - Equal to the width of the triggering

pulse

Edge-triggered - Equal to a time interval that is

generally much less than the width of the the

triggering pulse

th - hold time - Often equal to zero

tpx - propagation delay

Same parameters as for gates except

Measured from clock edge that triggers the output

change to the output change

Chapter 6 - Part 1 25

Circuit and System Level Timing

Consider a system

comprised of ranks

D Q D Q

C Q' C Q'

of flip-flops D Q D Q

C Q'

D Q

C Q'

C Q'

D Q

C Q'

circuit to flip-flop

CLOCK CLOCK

time interval begins

Chapter 6 - Part 1 26

Circuit and System Level Timing

New Timing Components

tp - clock period - The interval between occurrences

of a specific clock edge in a periodic clock

tpd,COMB - total delay of combinational logic along

the path from flip-flop output to flip-flop input

tslack - extra time in the clock period in addition to

the sum of the delays and setup time on a path

Can be either positive or negative

Must be greater than or equal to zero on all paths for

correct operation

Chapter 6 - Part 1 27

Circuit and System Level Timing

Timing components along a path from flip-flop

to flip-flop

tp

C

tpd,FF tpd,COMB ts tslack

(a) Edge-triggered (positive edge)

tp

C

tpd,FF tpd,COMB tslack ts

(b) Pulse-triggered (negative pulse)

Chapter 6 - Part 1 28

Circuit and System Level Timing

Timing Equations

tp = tslack + (tpd,FF + tpd,COMB + ts)

For tslack greater than or equal to zero,

tp max (tpd,FF + tpd,COMB + ts)

for all paths from flip-flop output to flip-flop input

Can be calculated more precisely by using tPHL

and tPLH values instead of tpd values, but

requires consideration of inversions on paths

Chapter 6 - Part 1 29

Calculation of Allowable tpd,COMB

Compare the allowable combinational delay for a

specific circuit:

a) Using edge-triggered flip-flops

b) Using master-slave flip-flops

Parameters

tpd,FF(max) = 1.0 ns

ts(max) = 0.3 ns for edge-triggered flip-flops

ts = twH = 1.0 ns for master-slave flip-flops

Clock frequency = 250 MHz

Chapter 6 - Part 1 30

Calculation of Allowable tpd,COMB

Calculations: tp = 1/clock frequency = 4.0 ns

Edge-triggered: 4.0 1.0 + tpd,COMB + 0.3, tpd,COMB 2.7 ns

Master-slave: 4.0 1.0 + tpd,COMB + 1.0, tpd,COMB 2.0 ns

Comparison: Suppose that for a gate, average tpd =

0.3 ns

Edge-triggered: Approximately 9 gates allowed on a path

Master-slave: Approximately 6 to 7 gates allowed on a path

Chapter 6 - Part 1 31

Overview

Part 1 The Design Space

Part 2 Propagation Delay and Timing

Part 3 - Programmable Implementation

Technologies

Why Programmable Logic?

Programming Technologies

Read-Only Memories (ROMs)

Programmable Logic Arrays (PLAs)

Programmable Array Logic (PALs)

Chapter 6 - Part 1 32

Why Programmable Logic?

Facts:

It is most economical to produce an IC in large

volumes

Many designs required only small volumes of ICs

Need an IC that can be:

Produced in large volumes

Handle many designs required in small volumes

A programmable logic part can be:

made in large volumes

programmed to implement large numbers of

different low-volume designs

Chapter 6 - Part 1 33

Programmable Logic - More Advantages

programmable, i. e., can be programmed outside of the

manufacturing environment

Most programmable logic devices are erasable and

reprogrammable.

Allows updating a device or correction of errors

Allows reuse the device for a different design - the ultimate in

re-usability!

Ideal for course laboratories

Programmable logic devices can be used to prototype

design that will be implemented for sale in regular ICs.

Complete Intel Pentium designs were actually prototyped with

specialized systems based on large numbers of VLSI

programmable devices!

Chapter 6 - Part 1 34

Programming Technologies

Programming technologies are used to:

Control connections

Build lookup tables

Control transistor switching

The technologies

Control connections

Mask programming

Fuse

Antifuse

Single-bit storage element

Chapter 6 - Part 1 35

Programming Technologies

The technologies (continued)

Build lookup tables

Storage elements (as in a memory)

Transistor Switching Control

Stored charge on a floating transistor gate

Erasable

Electrically erasable

Flash (as in Flash Memory)

Storage elements (as in a memory)

Chapter 6 - Part 1 36

Technology Characteristics

Permanent - Cannot be erased and reprogrammed

Mask programming

Fuse

Antifuse

Reprogrammable

Volatile - Programming lost if chip power lost

Single-bit storage element

Non-Volatile

Erasable

Electrically erasable

Flash (as in Flash Memory)

Chapter 6 - Part 1 37

Programmable Configurations

Read Only Memory (ROM) - a fixed array of AND

gates and a programmable array of OR gates

Programmable Array Logic (PAL) - a

programmable array of AND gates feeding a

fixed array of OR gates.

Programmable Logic Array (PLA) - a

programmable array of AND gates feeding a

programmable array of OR gates.

Complex Programmable Logic Device (CPLD)

/Field- Programmable Gate Array (FPGA) -

complex enough to be called architectures - See

VLSI Programmable Logic Devices reading supplement

PAL is a registered trademark of Lattice Semiconductor Corp. Chapter 6 - Part 1 38

ROM, PAL and PLA Configurations

Fixed Programmable Programmable

Inputs AND array OR array Outputs

(decoder) Connections

Inputs Outputs

Connections AND array OR array

Inputs Outputs

Connections AND array Connections OR array

Chapter 6 - Part 1 39

Read Only Memory

Read Only Memories (ROM) or Programmable

Read Only Memories (PROM) have:

N input lines,

M output lines, and

2N decoded minterms.

Fixed AND array with 2N outputs implementing

all N-literal minterms.

Programmable OR Array with M outputs lines to

form up to M sum of minterm expressions.

Chapter 6 - Part 1 40

Read Only Memory

A program for a ROM or PROM is simply a

multiple-output truth table

If a 1 entry, a connection is made to the

corresponding minterm for the corresponding

output

If a 0, no connection is made

Can be viewed as a memory with the inputs as

addresses of data (output values), hence ROM or

PROM names!

Chapter 6 - Part 1 41

Read Only Memory Example

Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output

lines)

The fixed "AND" array is a D7 X X X

decoder with 3 inputs and 8 D6

X X

D5

outputs implementing minterms. D4 X

D3

The programmable "OR A A2

D2 X

X X

array uses a single line to B A1 D1

X

C A0 D0

represent all inputs to an

OR gate. An X in the

array corresponds to attaching the

minterm to the OR

F3 F2 F1 F0

Read Example: For input (A2,A1,A0)

= 011, output is (F3,F2,F1,F0 ) = 0011.

What are functions F3, F2 , F1 and F0 in terms of (A2,6 A

Chapter 1, A

- Part 1 0)?42

Programmable Array Logic (PAL)

The PAL is the opposite of the ROM, having a

programmable set of ANDs combined with fixed ORs.

Disadvantage

ROM guaranteed to implement any M functions of N

inputs. PAL may have too few inputs to the OR gates.

Advantages

For given internal complexity, a PAL can have larger N and M

Some PALs have outputs that can be complemented, adding

POS functions

No multilevel circuit implementations in ROM (without

external connections from output to input). PAL has

outputs from OR terms as internal inputs to all AND

terms, making implementation of multi-level circuits easier.

Chapter 6 - Part 1 43

Programmable Array Logic Example

AND gates inputs

0 1 2 3 4 5 6 7 8 9

X

2

X X

F1

terms 3

X X X

4

X X

5 F2

F1 = A B + C X X

6

F2 = A B C + AC + AB I2 5 B

F3 = 7

X X

F4 = 8

X X

F3

X

9

I3 5 C

X X

10

X X

11 F4

X

12

I4

0 1 2 3 4 5 6 7 8 9

Chapter 6 - Part 1 44

Programmable Logic Array (PLA)

Compared to a ROM and a PAL, a PLA is the

most flexible having a programmable set of

ANDs combined with a programmable set of

ORs.

Advantages

A PLA can have large N and M permitting

implementation of equations that are impractical

for a ROM (because of the number of inputs, N,

required

A PLA has all of its product terms connectable to

all outputs, overcoming the problem of the limited

inputs to the PAL Ors

Some PLAs have outputs that can be complemented,

adding POS functions

Chapter 6 - Part 1 45

Programmable Logic Array (PLA)

Disadvantages

Often, the product term count limits the application

of a PLA.

Two-level multiple-output optimization is required

to reduce the number of product terms in an

implementation, helping to fit it into a PLA.

Multi-level circuit capability available in PAL not

available in PLA. PLA requires external

connections to do multi-level circuits.

Chapter 6 - Part 1 46

Programmable Logic Array Example

A

What are the equations for F1 and F2?

B Could the PLA implement the

functions without the XOR gates?

C

X X 1 X X AB

X X 2 X BC X Fuse intact

Fuse blown

X X 3 X AC

X X 4 X AB

C C B B AA X 0

X 1

3-input, 3-output PLA F1

with 4 product terms

F2

Chapter 6 - Part 1 47

Terms of Use

All (or portions) of this material 2008 by Pearson

Education, Inc.

Permission is given to incorporate this material or

adaptations thereof into classroom presentations and

handouts to instructors in courses adopting the latest

edition of Logic and Computer Design Fundamentals

as the course textbook.

These materials or adaptations thereof are not to be

sold or otherwise offered for consideration.

This Terms of Use slide or page is to be included within

the original materials or any adaptations thereof.

Chapter 6 - Part 1 48

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