EECE 6082C VLSI Design for Test/Power

Project 1 to be completed by Feb 27, 2017

Each team can have up to 2 members

The purpose of this project is to use Synopsys Design Compiler, DFT (design for
testability) Compiler and BSD (boundary scan design) Compiler to synthesize a GCD
machine which is able to compute the greatest common divisor of two numbers. The
following function gives the basic idea how this is done with A>=B.

GCD (A, B):

(a) If the remainder of A/B is 0, then B is the GCD.

(b) If it is not 0, then find the remainder of A/B and assign B to A and the remainder
to B.

(c) Return to step (a) and repeat the process.

For example, the greatest common divisor between 12 and 8 is 4. You can get this by
12%8, and the remainder is 4. Then, you divide 8 by 4 and the remainder is 0. So, you
have GCD(12,8)=4.

VHDL code of the machine will be given and you have to synthesize it using a 90-nm
technology cell library that contains scan cells. Please make sure that the registers
will be synthesized as flip-flops, not latches because we will use MUX-FF as scan
cells. You have to fix the VHDL code if necessary. The circuit will be synthesized as
shown in Fig. 1, next page. The reason to use a small machine for this project is to see
how the scan design is implemented, e.g., how the scan chain is organized.

There are totally three phases in this project: (1) register-transfer (RT) level code
simulation by writing a testbench, (2) circuit synthesis and test bench simulation, (3)
scan chain design and automatic test pattern generation. They are discussed below.
 Fig. 1: GCD Machine.

Phase 1: RT level simulation

Write a testbench to simulate the RT level code for ensuring the correctness of the
code. If the VHDL code provided uses latches to design the sequential circuit, you
have to change all latches to flip-flops such that MUX-type scan cells can be used
from the cell library. Make sure that the RTL code is working after replacing all latch
design to flip-flop design.

Phase 2: Circuit synthesis and test bench simulation

Use Design Compiler to synthesize your RTL GCD into gate-level using a 90-nm cell
library called saed90nm_typ_ht.lib, saed90nm.sdb and
saed90nm_typ_ht.db (announced in BB). Use the test bench developed in
phase 1 to simulate the synthesized circuit, especially checking the regular conditions
and corner conditions (e.g., GCD(10, 0)).

Phase 3: Scan chain construction and test pattern generation

Use Design Compilers DFT Compiler to construct a scan chain for the GCD
machine synthesized in Phase 1. Then, use TetraMax to generate test patterns for the
GCD machine with scan chain. In this phase, you need to use a directory called
saed90nm_typ_ht_verilog which contains Verilog files for gates.

All necessary cell libraries, tool user guides and tutorials have been announced in
BB.

For each task, the report must contain (1) the objective of this task, (2) the way to
solve the problem, (3) how the tool helps you solve the problem (mainly the script
must be included in the report), (4) the results reported by the tool , and (5) important
observations..

For example, in Task 2, you should explain: (1) The objective of doing logic
synthesis for GCD, (2) how to convert VHDL code from latch-based design to FF-
based design, (3) how to simulate the logic-level circuits after synthesis, (4)
summarize the reports from Synopsis, e.g., important results like gate counts, timing
information, (5) Give your observations for this task.

You are more than welcome to report whatever you think is important.

Please note that if a report gives many pages (e.g., netlist or test patterns), you just
need to give the first 5 pages to save paper. Submit a hard copy to Dr. Jone in the
class. If TA Sangeetha Shenoi requires e-submission to BB, we will let you know.

Repeat phases 1-3 above using a Fibonacci number generator (FNG). Just include 4,
and 5 of the report contents mentioned above. The Verilog code of FNG is given in a
separate file. The circuit function can be analyzed by the sim file.