PRACTICE 1: LOGIC GATES.

Daniel Rodriguez Jos de Jess Montero Omar Lopez David Escamila

Electronic engineering Electronic engineering Electronic engineering Electronic engineering
ITM ITM ITM ITM

I. INTRODUCTION space board, then write the code that describes the behavior of
In this practice, the objective consist in study of a logic gates, each logic gate, as shown in the following sequence:
principally a tip: AND, OR, NOT, XOR, NAND, NOR.
Vhdl code for the main logic gates
The study of a logic gates is most important in the electronic
word, because is using in divers camps and it use is different
Entity PRACTICA1 is
according a logic gate. In the practice use a program Ise Design
Suite for implementation the vhdl code at the target: digilent Port ( A1 : in STD_LOGIC;
Spartan 3. A2 : in STD_LOGIC;
F1 : out STD_LOGIC;
II. DEVELOPMENT F2 : out STD_LOGIC;
F3 : out STD_LOGIC;
A. Theoretical development
F4 : out STD_LOGIC;
In this section, develop the logic gates theory, because it use is
F5 : out STD_LOGIC;
different according a logic gate. This different, its expressing in
the table 1 and this depends a voltage in in the terminals of the F6 : out STD_LOGIC
logic gates. );
end PRACTICA1;

Table 1
architecture Behavioral of PRACTICA1 is

T1 T2 O NOT NAND NOR XOR XNOR begin

A A R F2 F3 F4 F5 F6
0 1 F1 F1 <= A1 OR A2;
F2 <= NOT A1;
0 0 0 1 1 1 0 1 F3 <= A1 NAND A2;
F4 <= A1 NOR A2;
0 1 1 0 1 0 1 0
F5 <= A1 XOR A2;
F6 <= A1 XNOR A2;
1 0 1 1 1 0 1 0
end Behavioral;
1 1 1 0 0 0 0 1

B. Vhdl code
In this section study the sequence necessary for program in Ise
Desing Suite in vhdl code. First is necessary the creation a new
Then it is very important to verify that the input values are the
same as output because on some occasions the code is correct,
but the sequence is incorrect.
 Input and output assignments to the FPGA board.

- Generation programing file: In this section the program

generates the bit file, where are saved the pins designated
on the target, for implementation in the FPGA.

D. Evaluation of the logic gates in the FPGA..

Once installed and the pin code and assign input and output of
the logic gates, it is time to evaluate the processes. To verify that
the logic states shown in Table 1. Together with Professor was
observed that the logic gates, meet their logical states of signal
selection. After introducing the truth table in FPGA terminals, the
LEDs which depended on the output signals, remained off, when
the signal was 0 and is activated, when the signal was 1

Picture 1
E. Questions

C. Implementation the vhdl code a the equivalents logic gate

in the FPGA.. What is the number of LUTs used in the synthesis?
The implementation in the FPGA., consist in tree steps: R=5
- Synthetise: In this section verifies the vhdl code to the
desired specifications. What is the amount of FlipFlops s used in the synthesis?
R=0
- Implement desing : In this proccess first selection place
and rute, because this section is the responsible of the
traslation a vhdl code at logics gates in the models of What is the number of IOBs used in the synthesis?
target FPGA.. After the transfer, the program assigns R= Total is 8, 2 input and 6 output.
certain input and output pins, which can be modified a
your preference, for this copy the old asignation, then What is the total percentage used in the logic gates
select the file vhd, right click and select give new suerce, R= Logic gates use: 3 that 1920 equals a 1% the
where select Implementation constraint files, all this to total.
generate the file, where the pins were modified and was
modificaded enruted again. following the above
procedure, we obtained the following assignments:
F. Conclusion

NET "F1" LOC = L14;

In this practice learned the basic characteristics of logic gates and
NET "F2" LOC = L13; its implementation in vhdl code and FPGA targets especially
NET "F3" LOC = M14; nexys Espartan 3. We see the truth table reflected in the outputs
of the FPGA (LEDs), was concluded that the FPGA is a
NET "F4" LOC = L12; mechanism to translate a logical sequence in vhdl code for logic
NET "F5" LOC = N14; gates, with the program Ise Design Suite.

NET "F6" LOC = M13; REFERENCES

[1] http://www.profesormolina.com.ar/electronica/componentes/int/comp_log.h
NET "A1" LOC = N15; tm

NET "A2" LOC = J16;