IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 26, NO.
6, AUGUST 2008
A Real-Time 4-Stream MIMO-OFDM Transceiver:
System Design, FPGA Implementation, and
Characterization
Simon Haene, Member, IEEE, David Perels, Member, IEEE, and Andreas Burg, Member, IEEE
AbstractWhen designing complex communication systems,
such as MIMO-OFDM transceivers, prototypes have become an
important tool for understanding the implementation trade-offs
and the system behavior. This paper presents a real-time FPGA
prototype for a 4-stream MIMO-OFDM transceiver capable
of transmitting 216 Mbit/s in 20 MHz bandwidth. The paper
covers all parts of the system from RF to channel decoding
and considers both algorithm and implementation aspects. In
particular, we discuss the initial parameter estimation, channel
estimation, MIMO detection, parameter tracking, and channel
decoding. FPGA implementation results are reported along
with measurements that demonstrate the throughput of spatial
multiplexing with four spatial streams.
Index TermsMIMO, OFDM, prototype, FPGA implementa-
tion, measurements, 802.11n, VLSI.
I. I NTRODUCTION
M ULTIPLE-INPUT multiple-output (MIMO) technology
combined with orthogonal frequency-division multi-
plexing (OFDM) and channel coding, for example based
on bit interleaved coded modulation (BICM), has recently
attracted significant attention. MIMO offers high spectral
efficiency through spatial multiplexing, OFDM provides re-
silience against interference caused by multipath propagation,
and BICM combines the ability to exploit the diversity in a
frequency-selective wideband MIMO channel with a straight-
forward approach to rate adaptation. Due to these signifi-
cant advantages, the combination of these three technologies
constitutes the basis for many next generation wireless com-
munication systems. The list of emerging standards already
employing these technologies [11] includes IEEE 802.11n
for wireless local area networks (WLAN), IEEE 802.16e
for metropolitan area networks, and the evolution of third
generation cellular systems (3GPP LTE).
Unfortunately, leveraging the tremendous gains achievable
with sophisticated signaling schemes also incurs the need
to employ elaborate transceiver architectures which build on
highly complex digital signal processing algorithms. Due to
their computational complexity, the economic implementation
of such systems remains challenging [12]: On one hand,
Manuscript received July 15, 2007; revised December 12, 2007. This paper
summarizes and extends our results, published in parts in [1][10], and puts
them into the context of a real-time 4 4 MIMO-OFDM prototype system.
The authors are with the Integrated Systems Laboratory and the Commu-
nication Technology Laboratory of the Swiss Federal Institute of Technol-
ogy (ETH) Zurich, 8092 Zurich, Switzerland (e-mail: haene@iis.ee.ethz.ch;
perels@iis.ee.ethz.ch; apburg@iis.ee.ethz.ch).
Digital Object Identifier 10.1109/JSAC.2008.080805.
0733-8716/08/$25.00 2008 IEEE
877
the hardware-efficient implementation of the transceiver algo-
rithms is an important task. On the other hand, understanding
the interaction of various algorithms and system components
and assessing the performance of the overall system under
real-world conditions is a crucial step in the development and
verification process.
Prototype implementations of MIMO systems are an ex-
cellent vehicle to study these system-level and performance
aspects. The real-time prototyping approach also offers oppor-
tunities to identify and work around complexity-bottlenecks, to
consider complexity/performance trade-offs, and to assess the
impact of hardware implementation on system performance.
Hence, the engineering of fully functional systems based on
programmable devices has frequently been adopted in the past
to support the development of MIMO wireless systems [13]:
The first prototype in this area has been a DSP-based, non real-
time, narrow-band system built by Bell-Labs to demonstrate
the gains available from using MIMO technology [14]. Later
prototypes, focusing on the application of MIMO to wideband
systems, include the real-time MIMO-CDMA demonstrator
described in [15], the first MIMO-OFDM system developed
at IOSpan [16], and a variety of other real-time and non
real-time prototypes, developed at universities and research
labs [17][21]. However, most of the existing MIMO testbed
implementations focus on algorithm and performance aspects
and the complexity and efficient implementation has often not
been the main research focus. Hence, corresponding publica-
tions provide little insight into the hardware architecture and
implementation aspects.
Contributions: This work is primarily concerned with the
implementation aspects of a real-time 4 4 MIMO-OFDM
transceiver with a view towards hardware-efficient (i.e., low-
complexity) algorithms. To this end, the present article covers
the complete physical layer, discusses the system architec-
ture, presents the algorithm choices for the transceiver im-
plementation, and outlines corresponding efficient hardware
architectures. Our implementation results provide reference
for the hardware complexity of the complete physical layer
transceiver and the referenced companion papers provide an
in-depth, comprehensive view of its individual components.
Reproducible measurement results are obtained from a well
defined measurement setup including an RF channel emulator.
Outline: The remainder of this paper is structured as
follows: An overview of the MIMO-OFDM system under con-
sideration is presented in Section II. Corresponding receiver
878 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 26, NO. 6, AUGUST 2008

scrambler conv. encoder puncturer mapper OFDM modulator

algorithms are discussed in Section III. Section IV describes

interleaver
scrambler conv. encoder puncturer mapper OFDM modulator

parser
the hardware platform used for the field programmable gate
scrambler conv. encoder puncturer mapper OFDM modulator
array (FPGA) implementation. A detailed view on the archi-
scrambler conv. encoder puncturer mapper s[t]
OFDM modulator
tecture of the real-time 4 4 MIMO-OFDM physical layer
b[l] s[k, t]
is provided in Section V. Implementation and measurement
results are reported in Sections VI and VII and conclusions (a) Transmitter
are drawn in Section VIII. OFDM demod. MIMO processing depunc. Viterbi descr.

synchronization

deinterleaver
pilot-tracker

deparser
Notation: Matrices are denoted by bold uppercase letters, OFDM demod. spatial depunc. Viterbi descr.

AGC &
soft-
MIMO
the rth row of A by Ar . Lowercase bold letters represent OFDM demod. separa-
metric
extraction
depunc. Viterbi descr.
r[t] tion
column vectors. The rth entry of vector a is written as ar . OFDM demod. depunc. Viterbi descr.

L(b | r[k, t], H[k]) b[l]

AH and A1 denote the Hermitian transpose and the inverse
of A, respectively. The operator (.) extracts the angle of its
complex-valued argument and exp[a] denotes the exponential
function ea . Upper case caligraphic letters denote sets of
integer numbers and |B| corresponds to the cardinality of the
set B. The operator \ denotes the set-theoretic difference.
II. S YSTEM D ESIGN
The MIMO-OFDM system presented in the following is
based on the OFDM modulation parameters defined in the
IEEE 802.11a single-antenna WLAN standard [22]. These
parameters define a bandwidth of 20 MHz, N = 64 subcar-
riers, and a cyclic-prefix length of 16 samples. For tracking
purposes, 4 subcarriers are reserved for the transmission of
known BPSK training sequences. In order to spectrally shape
the transmitted signal, 12 tones are turned off. The frequency-
domain indices of all non-zero tones are subsumed in the set
P = {26, . . . , 1, 1, . . . , 26} and the frequency indices of
the pilot tones are given by K = {7, 21}. Modulation
schemes for the data tones range from BPSK to 64-QAM and
channel coding is based on BICM and a rate-1/2 convolutional
code with constraint length 7. Coding rates of 2/3 and 3/4 are
achieved through puncturing. Compared to the IEEE 802.11a
standard specifications, the system under consideration was
extended to support spatial multiplexing with antenna config-
urations up to 4 4, thus achieving a four-fold increase in the
peak data rate from 54 Mbit/s to 216 Mbit/s.
A. System Model
The transmitter follows the data flow shown in Fig. 1(a) for
the case of MT = 4 transmit antennas. During data transmis-
sion, a high-rate data stream b[l] (where l indexes the payload
bits to be transmitted) is parsed into MT lower-rate data
streams. Each of these lower-rate streams is scrambled, binary
convolutionally encoded, and punctured independently. The
punctured data is interleaved bitwise across OFDM tones and
across transmit antennas to leverage both frequency and spa-
tial diversity. The resulting bit-streams (each associated with
one of the transmit antennas) are then mapped to 2Q -QAM
constellations by translating groups of Q = 1, 2, 4, or 6 bits
to scalar constellation points, depending on the selected mod-
ulation scheme. The corresponding scalar constellation points
of the individual streams are grouped into vectors s[k, t] of
dimension MT , where k (P \ K) and t indicate the OFDM
tone index and the OFDM-symbol time index, respectively.
The QMT bits b , with = 1, 2, . . . , QMT , corresponding
to s[k, t] are referred to as the label of s[k, t]. After OFDM
r[k, t] r[k, t]
(b) Receiver
Fig. 1. Transmitter and receiver architecture for a 4 4 MIMO-OFDM
system employing spatial multiplexing and BICM.
modulation, the resulting signal is transmitted over the wire-
less channel.
The corresponding digital baseband receiver is shown in
Fig. 1(b). The power of the received signal is first adjusted
by an automatic gain control (AGC) and frames detected by
the synchronizer are OFDM demodulated independently for
each of the MR receive antennas to yield the vectors r[k, t]. A
pilot-tracking unit, operating on
r[k, t], is responsible for fine-
grained synchronization tasks and produces vectors r[k, t].
Assuming perfect timing and frequency synchronization after
the pilot tracking operation and a propagation channel with
a delay-spread smaller than the cyclic prefix inserted during
OFDM modulation, the OFDM demodulated and pilot-tracked
signal can be expressed as
r[k, t] = H[k]s[k, t] + n[k, t],
where H[k] is an MR MT -dimensional matrix describing
the channel experienced by the kth tone and where n[k, t]
is a complex vector representing the additive thermal noise.
The time index t is omitted for the channel matrices since
they are assumed to remain constant during an entire OFDM
frame (block-fading assumption). A MIMO processing unit is
in charge of extracting soft-information for Viterbi decoding.
This operation corresponds to computing log-likelihood ratios
(LLRs) L(b | r[k, t], H[k]) for the QMT bits associated with
each of the vector symbols s[k, t]. After deinterleaving and
depuncturing, the LLRs are fed into separate Viterbi decoders
for channel decoding. The estimate b[l] of the original high-
rate data stream b[l] is finally reconstructed by recombining
the decoded and descrambled lower-rate streams.
B. Frame Structure
The WLAN system under consideration is a packet-based
communication system. Hence, the receiver must synchronize
to each OFDM frame anew. For this reason, each burst
starts with dedicated preamble and training symbols as shown
in Fig. 2. At the receiver, the preamble is used for AGC
convergence and for timing and frequency synchronization.
The preamble OFDM symbols are constructed based on the
short preamble defined in IEEE 802.11a [22], but are radi-
ated employing all transmit antennas. To avoid unintended
HAENE et al.: A REAL-TIME 4-STREAM MIMO-OFDM TRANSCEIVER: SYSTEM DESIGN, FPGA IMPLEMENTATION, AND CHARACTERIZATION
Timing and
frequency synch. Block-type
AGC setting channel training Header Payload data
antennas
Transmit
ng
bl
m
ni
ea
ai
Tr
Pr
0 8 12 16 20 24 28 32
Fig. 2. Structure of a MIMO-OFDM frame.
beamforming, each of the OFDM tones excited by the legacy
preamble is assigned to one transmit antenna exclusively [6].
To enable coherent detection of the transmitted data symbols
the complex-valued channel matrices H[k] must be estimated
at the receiver. To this end, the preamble is followed by MT
OFDM training symbols which are based on the BPSK
training sequence (long preamble) used in IEEE 802.11a [22].
To support MIMO channel estimation, a frequency-orthogonal
training sequence is constructed. The basic idea behind this
sequence is to distribute the tones that comprise a training
symbol equally across the transmit antennas to stimulate each
tone by only one transmit antenna at a time. To sound all
entries of H[k], the assignment of tones to transmit antennas is
altered for each training symbol. After MT training symbols,
all tones in all spatial channels have been stimulated, one at
a time.
The first OFDM data symbol, immediately following the
channel training, is reserved as a physical layer header that
contains information on the length and transmission mode of
the subsequent payload data. This field is always transmitted
in the most robust modulation and coding scheme.
III. T RANSCEIVER A LGORITHMS
The focus of this section is on the discussion of the
individual algorithms employed for the most critical receiver
components. To this end, the synchronization, the channel
estimation, the separation of the spatially multiplexed data
streams, the tracking, and the extraction of LLRs shall be
discussed.
A. Synchronization
The first stage of the physical layer signal processing is
an AGC that estimates the signal-power level to be expected
during the training and data portion of the frame based on the
first few samples of the preamble [23]. Different gain stages
at the input of the receiver are set according to this estimate in
order to optimally exploit the dynamic range of the hardware.
The AGC is followed by the frame-start detection for which
three main classes of algorithms can be identified:
1) With matched-filter-based algorithms, the received sig-
nal is correlated with the known preamble sequence.
This approach works well for specially designed syn-
chronization signals as they are common in CDMA
systems [24]. The IEEE 802.11a preamble, instead,
is less suitable for matched-filter approaches due to
the signals periodicity and the considerable hardware
complexity required for a corresponding matched-filter
implementation.
879
2) Autocorrelation-based approaches rely on the detection
of repeating portions of a received signal. The basic
idea was first described in [25] and was further re-
fined to allow frame-timing extraction in the case of
initial signal-power fluctuations incurred by an AGC
time [us] in [26]. The hardware complexity of these approaches
is significantly lower compared to matched-filtering.
Unfortunately, multi-path channels lead to inaccurate
frame-timing recovery.
3) Power-based frame-start detection [9] compares the
instantaneous received signal power to a long-term
received-signal power estimate. A frame start is detected
if the ratio between the two power measurements ex-
ceeds a threshold. In the MIMO case, the aggregate
received power across all antennas can be considered,
which leads to surprisingly precise detection. Among
the three classes of synchronization algorithms, this ap-
proach is the most hardware-efficient solution. However,
it suffers from a high false-alarm rate in the presence of
strong interference.
In order to combine the advantages of the last two ap-
proaches (lower false-alarm rate and detection precision), the
system under consideration performs initial synchronization
using a power-based approach and improves the detection
reliability by additionally taking into account an autocorre-
lation metric that confirms the characteristic periodicity of an
IEEE 802.11a-based preamble. The corresponding metric is
obtained as a side product of the frequency-offset estimation.
Upon detection of a new frame, a potential carrier frequency
offset between transmitter and receiver must be estimated and
compensated to preserve the orthogonality between different
tones. Because this estimate must be obtained both fast and
accurately, only training assisted methods are considered since
blind approaches [27], [28] do not provide reliable results
on time. In our system, the initial carrier frequency offset
estimation is carried out on the preamble using the auto-
correlation algorithm presented in [25]. Compared to the
single-input single-output (SISO) case, a lower estimation
variance is achieved by combining the correlations obtained
on different antennas1 .
B. Channel Estimation
With the frequency-orthogonal training described in Sec-
tion II-B, tone-by-tone channel estimation can be easily per-
formed for each H[k], one column at a time. To this end,
the receiver simply divides the received vectors r[k, t] by
the scalar (BPSK) training symbol transmitted on tone k at
time t from the jth transmit antenna2 to obtain the jth column
of the estimated channel matrices H[k]. We shall refer to
this estimate as the frequency-domain maximum likelihood
(FDML) estimate.
The number of degrees of freedom in the estimated
frequency-domain channel coefficients depends on the length
of the time-domain channel impulse response. Assuming the
channel being shorter than the cyclic prefix and a number of
1 It is reasonable to assume that the frequency offset is the same across all
antennas since the local oscillators are usually shared.
2 With k P and t = 0, 1, . . . , 3, j = (k t) modulo M
T
880 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 26, NO. 6, AUGUST 2008
Q Q
P (trained subcarriers) P (trained subcarriers)
DC
S distance = 4 X S X S
DC
Fig. 3. Graphical representation of the sets P, Q, X and S required for
the refinement of the FDML channel estimate with the tone allocation of
IEEE 802.11a.
subcarriers that is larger than the cyclic prefix length, the es-
timated frequency-domain channel coefficients are correlated.
Since the simple FDML estimation algorithm does not exploit
this correlation to improve the estimation accuracy, low-pass
filtering of channel coefficients (for all the MT MR spatial
subchannels independently) has been recognized as a simple
technique to improve the quality of an initial FDML chan-
nel estimate. Unfortunately, the presence of untrained zero
tones, that spectrally shape the transmitted signal, introduces
an irregularity in the initial FDML channel estimate which
increases the complexity of straightforward low-complexity
channel-estimation refinement algorithms [29]. The technique
employed in the system under consideration follows the ap-
proach initially introduced in [5] and also summarized in [8].
The basic idea of this algorithm is illustrated in Fig. 3 and
outlined as follows: The procedure starts with the straightfor-
ward FDML estimation for all trained tones, whose indices
are subsumed in the set P. In a second step, an equidistant
set of tones X with distance four3 is chosen and an initial
estimate is computed for all untrained zero tones in X (the
set of zero tones in X is denoted as Q, as shown in Fig. 3).
In a third step, an estimate for all remaining untrained zero
tones, subsumed in S, is obtained based on the tones in the
equidistant set X . In a last step, the initial estimate (now
available for all N tones in the union of the sets P, Q, and S)
is refined though low-pass filtering of the frequency-domain
channel estimate. The analytical mean-squared error (MSE) of
this estimation scheme has been derived and shown to be close
to the MSE of the optimum maximum-likelihood estimator
in [5]. A more detailed discussion and analysis of this topic
is provided in [30].
C. MIMO Detection
Once the channel coefficients are known, a wide range
of algorithms is available for the separation of the spatially
multiplexed data streams. This separation can be performed on
each OFDM tone independently. Almost all MIMO detection
algorithms can be partitioned into a preprocessing and a detec-
tion phase. The preprocessing comprises all those operations
which must be carried out only when the channel estimate
changes. The detection comprises the remaining operations
which must be performed for each received vector r[k, t].
3 With a distance of four, the channel impulse response is assumed to
be limited to N/4 sample-spaced taps. If this condition is not fulfilled
(e.g., because real-world channels are not sample-spaced and the unavoidable
resampling operation will produce longer channels) the performance of the
estimation algorithm will degrade gradually, depending on the amount of
energy leaking beyond the first N/4 taps.
1) Choice of MIMO Detection Algorithm: Optimum er-
ror rate performance is achieved with soft-output maximum
likelihood detection which can be implemented economically
on ASICs using the sphere decoding or other tree-search
algorithms [31][34]. Unfortunately, on FPGAs (which are
significantly slower compared to ASICs), real-time hard-
decision or soft-output sphere decoding for the system under
consideration would require a prohibitive amount of FPGA
resources for parallel processing.
Linear and successive interference cancellation (SIC) algo-
rithms are viable alternative solutions since the complexity
of their detection stage is lower than the complexity of
sphere decoding, especially for high rates (e.g., MT = 4,
64-QAM). While in uncoded systems SIC yields better error
rate performance than linear detection, the error-propagation
associated with SIC hinders the generation of high-quality
soft-information [35]. This drawback of SIC leads to a per-
formance loss compared to linear detectors in systems with
BICM [35]. Hence, for the prototype under consideration,
a linear detector is employed. The corresponding algorithm
performs the preprocessing for all OFDM tones independently
according to
H H[k] H
G[k] = (H[k] + MT 2 I)1 H[k] (1)
where 2 is either an estimate of the noise variance (MMSE
detection) or a regularization parameter that facilitates the
fixed-point hardware implementation by limiting the dynamic
range of the entries of G[k].
The subsequent detection at the symbol-rate applies G[k]
to the received vectors r[k, t] according to
s[k, t] = G[k]r[k, t]. (2)
For hard-decision decoding the entries of s[k, t] are quantized
to the nearest constellation point. For soft-decision decoding,
LLRs are calculated as described in Section III-E.
2) Algorithm for Linear Preprocessing: The main chal-
lenge in the implementation of linear MIMO detection is the
preprocessing which requires the inversion of an unstructured,
complex-valued matrix for each data-bearing OFDM tone4 .
The three most common approaches to this problem are
triangularization using Givens rotations followed by back-
substitution [37], the square-root algorithm employed in [38]
to simplify the V-BLAST algorithm, and direct matrix inver-
sion (DMI) algorithms [37]. The main arguments for DMI
are the lower number of operations compared to the other
two methods and the natural mapping to highly efficient
arithmetic components available as macros in modern FPGAs.
The main disadvantage of DMI are the stringent fixed-point
requirements.
The preprocessing algorithm employed in the reported sys-
tem relies on DMI since the implementation target technology
are FPGAs. The specific algorithm [4], [31] is similar to
the procedure for updating the gain in Kalman filters. The
HH
basic idea is to note that H + MT 2 I can be constructed
from MR rank-one updates to MT 2 I. By using the matrix
4 Note that, in the system under consideration, interpolation-based channel-
matrix preprocessing algorithms [36] are not advantageous in terms of
complexity since the number of OFDM tones is low.
HAENE et al.: A REAL-TIME 4-STREAM MIMO-OFDM TRANSCEIVER: SYSTEM DESIGN, FPGA IMPLEMENTATION, AND CHARACTERIZATION 881

inversion lemma, the corresponding inverse can be updated on- RFO and SRO Estimation after Spatial Separation: The
the-fly. To this end, the corresponding iteration is initialized computational complexity of this algorithm is lower compared
by setting to the previous algorithm since there is no need to estimate the
1 received pilot symbols according to (4). Instead, the a-priori
P(1) = I known BPSK pilot symbols s[k, t] can be used as reference.
MT 2
Hence, the calculation of rfo is simplified to
and proceeds by computing  
  
(n+1) (n)
HH
H n
n P(n) rfo [t] = H
s[k, t] s[k, t] , (6)
P P I , (3)
1+H n P(n) H
H kK
n
and the phase offset slope induced by the SRO is obtained
where H n denotes the nth row of H. After MR iterations,
from
HH + MT 2 I)1 and G = P(MR +1) H H.
P(MR +1) = (H 

The dependence on the OFDM tone index k has been omitted k (s[k, t]H s[k, t]) rfo [t]
for brevity in this paragraph.  = kK
[t]  2 . (7)
k
kK
D. Algorithms for Pilot Tracking For the compensation of the impact of RFO and SRO
Initial carrier frequency offset estimates suffer from esti- the received
 signals on the data-bearing
 tones are multiplied
mation uncertainties which induce a residual frequency offset 
with exp j(rfo [t] + [t]k) . This compensation can be
(RFO). Additionally, the sampling rate offset (SRO) between performed before or after linear detection, independently of
transmitter and receiver introduces a tone dependent frequency the chosen estimation algorithm.
shift that cannot be estimated efficiently during the preamble An in-depth discussion of the estimation and compensation
and causes a tone-dependent phase deviation5 [39]. of analog and RF impairments in MIMO-OFDM systems can
Hence, both RFO and SRO inhibit coherent detection if not be found in [23].
compensated. To perform this compensation, the impact of
these impairments must be estimated and eliminated during
E. Generating Soft-Information
the data section of the frame using a-priori known pilot

The computation of LLRs L(b | r[k, t], H[k]) for channel
constellations transmitted on a set of pilot tones (those in K).
In the receiver architecture outlined in Fig. 1(b), pilot- decoding follows the algorithm described in [40]. The basic
tracking is performed immediately after OFDM demodulation. idea is to start from the input-output relation between the
In receivers based on linear MIMO separation, however, this transmitted vector symbol s and the output s of the spatial
task can be postponed until after the MIMO detection. Both separation in (2) which can be written as
alternatives are considered in the following. I)s + Gn,
s = s + (GH
RFO and SRO Estimation after OFDM Demodulation:
During the data section of the frame, the expected received where the time and tone indices have been omitted for brevity.
pilot constellations r[k, t] are calculated for k K based on Modeling the residual interference (GH I)s as i.i.d. Gaus-

the channel estimates H[k] and the known pilot constellations sian noise, the MIMO system is partitioned into MT parallel
s[k, t] according to SISO systems. For each of these SISO systems, the effective
signal to interference plus noise ratio (SINR) that accounts for

r[k, t] = H[k]s[k, t]. (4) the thermal noise and for the residual interference from other
Now, the phase offset due to RFO can be estimated as spatial streams is given by [41]
  1
   i =   1. (8)

rfo [t] = H
exp j(r[k, t] r[k, t]) , (5)
MT n2 (H[k] H[k] + MT n2 I)1
H
kK i,i

where the (.) and exp[.] functions are needed to normalize With this per-stream additive Gaussian noise model and by
the contributions of the individual pilot tones to rfo . The using the well known log-sum approximation, LLRs can be
slope of the phase deviation is calculated as approximated efficiently for the qth bit in the ith stream

independently of all other streams according to
k (r[k, t]H r[k, t]) rfo [t]
i (b , si )
L(b | s, H) (9)
 = kK
[t]  2 .
k
with (b , si ) = min0 | 2
si s| min1 | 2
si s| , (10)
kK s
Aq s
Aq
Note that for this algorithm to function properly, samples must
where the bit-index = (i 1)Q + q. In (10) the sets A0q and
be inserted or removed in the time-domain sample stream
A1q contain the scalar constellation points for the one and zero
if the phase slope exceeds a threshold corresponding to the
 hypothesis for the qth bit associated with si . Note that due to
offset of one sample, i.e., |[t]| > 2/N . This correction is the decoupling of the data streams, the evaluation of (9) for
necessary to avoid phase wrapping due to SRO. all bits in a vector symbol merely requires the computation
5 In the system under consideration the impact of RFO and SRO are of QMT Euclidean distances in a 1-dimensional, complex-
considered to be independent of each other. valued vector space, while the evaluation of exact LLRs would
882
MIMO-OFDM terminal FPGA
module
Converter
modules
AGC control signals
Host computer
Matlab applications
MEX function
Transceiver API
PCI Analog
Driver
bus (20 MHz IF)
Fig. 4. Hardware components of a MIMO-testbed terminal.
require the computation of 2QMT Euclidean distances in an
MT dimensional, complex-valued vector space, which would
be prohibitively complex.
Further complexity reduction can be achieved when Grey-
labeling is chosen for the mapping to QAM constellations. For
this case it has been shown in [40] that (10) is a piecewise
linear function that depends only on the real or imaginary part
of si , depending on the value of q.
IV. MIMO T ESTBED P LATFORM
The receiver algorithms presented in the previous section
were prototyped on a real-time MIMO testbed. As shown in
Fig. 4, each terminal of this testbed consists of a host PC, an
FPGA-based platform with peripheral component interconnect
(PCI) interface, and a multi-antenna RF transceiver.
A. PCI-Based FPGA Platform
The PCI platform hosts three hardware modules: a large
FPGA (Xilinx XC2V6000-6) module for baseband signal pro-
cessing and two converter modules for digital-to-analog con-
version (DAC) and analog-to-digital signal conversion (ADC).
On an FPGA (Xilinx XC2V1000-4) provided on each of the
converter modules, the baseband signals are digitally converted
to an intermediate carrier frequency (IF) of 20 MHz. Hence,
the total number of converters is reduced by a factor of two
compared to zero-IF transceivers with separate converters for
the I and Q components. Incidentally, the digital IF also
avoids any I/Q imbalance, at the cost of higher sampling
rate and resolution. Both the 14 bit DACs and the 12 bit
ADCs run at a sampling rate of 80 MS/s. Note that for our
testbed implementation the digital-IF architecture has been
preferred over the zero-IF architecture that is commonly used
in commercial products. The reasons for this choice were the
lack, at that time, of commercially available integrated zero-
IF transceivers and the fact that the advantages outlined above
were instrumental in greatly facilitating the hardware design
and maintenance of the testbed.
B. Analog RF Frontend
The RF frontend converts analog signals from the 20 MHz
IF to the RF frequency band, and vice versa. Each terminal
is equipped with four SISO super-heterodyne RF chains with
an analog IF of 475 MHz. The chains are built from discrete
RF components and support 20 MHz channel bandwidth with
center frequencies in the 2.4 GHz industrial, scientific, and
medical (ISM) band. The received signal power at the ADCs
is regulated by digitally controllable analog attenuators. These
attenuators extend the dynamic range of the receive chains by
31 dB. In conjunction with the 12 bit resolution of the ADCs,
the useful dynamic range amounts to approximately 70 dB.
IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 26, NO. 6, AUGUST 2008
C. Software Stack
Multi-antenna
Each terminal is controlled from a host PC through mul-
2.4 GHz RF tiple layers of software that allow communication with the
transceiver
hardware. This software stack includes a hardware driver for
the PCI board, a transceiver-specific application programming
interface (API) that provides several functions (for the digital
baseband configuration and the transmission or reception
of MIMO-OFDM frames), and a Matlab external interface
(MEX) function to call these API functions. Demo appli-
cations, configuration tools, and measurement sequences are
programmed as Matlab scripts.
V. R EAL -T IME FPGA I MPLEMENTATION
For the FPGA implementation, the MIMO-OFDM phys-
ical layer is partitioned into synchronization, OFDM
de/modulation, channel estimation, tracking, MIMO prepro-
cessing and detection, a first-input first-output (FIFO) buffer,
and channel de/coding. The block diagram of the complete
system is shown in Fig. 5.
Since the data flow in transmit mode is trivial, the ex-
planations of this section focus on the receive mode. The
corresponding data flow and timing are illustrated in Fig. 6 and
are summarized as follows: The synchronization unit is active
only when the channel is idle and during reception of the
preamble. After successful synchronization, OFDM demodula-
tion starts with the beginning of the training sequence. During
this training, the output of the OFDM demodulator is fed to
the channel estimation unit. The resulting estimates H[k] for
the channel matrices for all data and pilot tones are stored in
a memory. The MIMO processing unit accesses this memory
during the subsequent preprocessing phase to compute the
spatial equalizer coefficients G[k] according to (1) and the
associated per-stream SINR estimates i [k] according to (8)
for the computation of the LLRs. The matrices G[k] can be
stored without the need for additional memory by replacing
the corresponding channel estimates H[k], which are no longer
needed. A separate memory is required to store i [k]. The
detection of the data symbols in the MIMO processing unit
starts after the preprocessing is complete. Since in the system
under consideration the training is immediately followed by
data, a FIFO buffer is needed to store the received samples
until the MIMO processing unit and the bit-metric unit can
start with the data detection according to (2) and with the
generation of LLRs for the Viterbi decoder according to (9).
A. Synchronization
The synchronization block contains the AGC, the frame-
start detection, the digital down-conversion (DDC), and the
frequency offset estimation and compensation.
The AGC for each antenna is comprised of an analog atten-
uator in the RF chain and of a digital gain stage at the digital
IF. This two-step approach allows to control the signal power
in finer steps which leads to faster convergence of the power
control. Moreover, the digital gain stage allows to further
amplify weak signals to improve the utilization of the dynamic
range available for the subsequent digital signal processing.
The corresponding circuit employs two multipliers per receive
antenna, one for power estimation and one for the application
HAENE et al.: A REAL-TIME 4-STREAM MIMO-OFDM TRANSCEIVER: SYSTEM DESIGN, FPGA IMPLEMENTATION, AND CHARACTERIZATION 883

Interface Physical layer

Channel de/coding OFDM de/modulation

Symbol map.
Interleaving

4xDAC
Scrambling

Puncturing
Add
Convolu-

Demux

DUC
Tx preambles
tional
Host PCI bus

buffer and cyclic

FFT processor
encoding
MIMO processing and prefix Synchroni-
channel estimation zation

Deinterleaving
Descrambling

Bit-metric unit
Depuncturing

Frame timing
Pilot tracking

FIFO buffer

4xADC
MIMO processing Freq.

Demux

DDC

AGC
Rx Viterbi
Mux

offset est.
buffer decoding
and comp.
H/G mem H estim.

Fig. 5. Overview of the digital signal processing architecture of the MIMO-OFDM testbed transceiver.

Preamble Training Header & Payload data

Idle Idle

Synchronization Tracking
FFT FIFO buffering FFT
Channel estimation
Preprocessing
MIMO detection
Channel decoding
FFT Est. Preprocessing Receiver
latency latency latency latency

Fig. 6. Timing diagram illustrating the MIMO-OFDM receiver data flow.

of the digital AGC gain. The signal-power estimation for each provides the rotating phasor and four real-valued multipliers
antenna is obtained by the accumulation of 64 successive are used to compensate the carrier frequency offset for all four
squared samples, which proves to be more accurate than an receive antennas.
infinite-impulse-response (IIR) filter when operating on the
periodic preamble signal. Costly mathematical functions, such B. OFDM De/modulation
as square-root and division, which are necessary to obtain
an accurate power correction factor, are implemented in an In transmit mode, the OFDM de/modulation unit maps bi-
iteratively decomposed manner in order to reduce their impact nary data to complex-valued constellation points, computes the
on hardware complexity. superposition of all modulated tones with an IFFT transform,
and inserts the cyclic prefix. At the beginning of each frame,
The DDC in the receive path and the digital up-conversion
the de/modulation unit also outputs the preamble, whose time-
(DUC) in the transmit path are realized as polyphase finite-
domain representation is stored in RAMs instead of being
impulse-response filters with incorporated IQ-de/modulation
generated at run-time to reduce the transmit latency to a
and down-/up-sampling in order to minimize hardware cost,
minimum. In receive mode, the same unit demodulates the
avoiding unnecessary multiplications.
received OFDM symbols by means of FFT transforms. For the
Power-based frame-timing recovery is realized based on de/modulation of OFDM symbols, a 64-point I/FFT processor
the architecture described in [9]. Two multipliers are used with a single radix-4 processing element [8] is shared among
to obtain the power estimate for all four receive chains at the transmit and receive data paths. The different spatial
baseband. streams are processed in a time-interleaved fashion by the
Initial carrier frequency offset estimation and compensation same hardware.
is active during the preamble and realizes the operations The architecture of the I/FFT processor is shown in Fig. 7.
described in [25]. However, instead of a running mean, a low- The memory unit stores the complex-valued vector to be
pass filter in the form of an IIR filter reduces the memory processed. In order to provide sufficient memory bandwidth,
requirements considerably. A coordinate rotation digital cal- the storage is divided into four separate, dual-ported memory
culation (CORDIC) architecture [42] is used to obtain the banks, each holding up to 16 complex-valued data words. The
per-sample phase offset required for compensation of the bus barrel shifters multiplex the data words to the appropriate
frequency offset. One built-in 18 kbit random-access memory bank and are required to support an addressing scheme [43]
(RAM) per receive antenna stores the incoming complex- that avoids access conflicts during the computation of I/FFTs.
valued samples required to compute the auto-correlation. The The processing unit performs the arithmetic operations and
size of the RAM allows to correlate over a lag of either is based on a conventional decimation-in-time radix-4 but-
16, 32, or 64 samples in order to enhance the accuracy of terfly [44], consisting of three complex-valued multipliers
the frequency-offset estimate if necessary. A look-up table and eight complex-valued adders. A dedicated look-up table
884
control
input
control unit
coefficient generation
constant matrix LUT FFT Twiddle LUT
processing unit
multiply-accumulate operation
butterfly or multiplication operation
memory unit
input
bank 0
bank 1
bank 2
bank 3
SRAM
SRAM
SRAM
SRAM
data
bus
barrel
input shifter
Fig. 7. Top-level architecture of the radix-4 I/FFT processor.
(LUT) generates the twiddle coefficients for the I/FFT trans-
forms [44]. This twiddle-LUT is modest in size and is thus
realized with random logic. The computations are orchestrated
by a central control unit which accepts instructions and
generates all control signals and addresses for the RAMs and
LUTs.
C. Channel Estimation
The straightforward FDML channel estimation algorithm
has a negligible hardware complexity since it involves only
trivial multiplications with the known BPSK training se-
quence. Hence, the corresponding operations are implemented
on dedicated hardware directly in the MIMO processing
unit. The interpolation-based channel estimation refinement
algorithm described in Section III-B, instead, has a much
higher complexity. However, the interpolation algorithm can
be implemented efficiently based on I/FFT operations that
can be outsourced to the I/FFT processor in the OFDM
de/modulation unit.
The implementation of the interpolation-based channel es-
timation requires the following steps for each spatial subchan-
nel: First, the tones in P, which have been computed on-the-fly
during the demodulation of the training OFDM symbols, are
multiplied with a constant 2 52 matrix to obtain estimates
for the two untrained tones in Q. Next, the two results of
the matrix-vector multiplication, together with the remaining
14 tones that are part of X , are transformed into time-
domain by a 16-point IFFT. The result of this transformation
is element-wise multiplied with a phase correcting vector.
After (virtually) zero-padding the result to a length of 64,
it is transformed back into the frequency-domain, yielding
an estimate for the remaining untrained subcarriers (those
in S). These estimates are concatenated with the initial FDML
estimates for the trained subcarriers and with the estimates for
those in Q. At this stage, an estimate for all subcarriers is
available and the correlation between channel coefficients can
be exploited to reduce the estimation error. This requires a
64-point IFFT, a brick-wall filter that sets to zero all elements
of the result exceeding the length of the channel impulse
response, and a 64-point FFT. On the I/FFT processor, the
multiplication with the brick-wall mask is performed only
virtually and does not require any clock cycles. Additionally,
the last FFT, which operates on a vector containing many
zeros, is optimized to skip a third of the butterfly operations.
IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 26, NO. 6, AUGUST 2008
To perform the above described algorithm on the I/FFT
for channel processor, its radix-4 processing unit was extended with
estimation
additional multiplexers, two complex-valued adders, and two
accumulation registers as reported in [30] and [8] to enable
for channel
estimation the execution of plain complex-valued multiplications and
multiply-accumulate operations. Moreover, an additional LUT
was added to the I/FFT processor shown in Fig. 7. This
LUT stores the 2 52 matrix required to compute the initial
output data estimates for the subcarriers in Q. With these extensions, the
output
bus
barrel
I/FFT processor can be shared between channel estimation and
shifter OFDM de/modulation to save hardware resources.
For the MIMO case, the described sequence of operations
is repeated for all MT MR spatial subchannels sequentially,
incurring an overall latency of 42 s for channel-estimate
refinement in a 4 4 system.
D. MIMO Processing
The MIMO processing unit performs both preprocessing
and detection. The main reason for combining these two
operations is the fact that in the present architecture they are
never performed at the same time. The hardware required for
the preprocessing can thus be reused for the detection of data
symbols once preprocessing is complete. To ease hardware
reuse, the moderately parallel architecture detailed in [4] has
been chosen for the implementation of the MIMO processing
unit. The corresponding circuit is comprised of a circular array
of MT identical processing elements (PEs) and of a common
divider for the division in (3). The PEs are connected only
to their neighbors and each PE contains a complex-valued
multiplier, an adder and some local registers. The arithmetic
is pipelined with one stage which provides a reasonable
compromise between potential for higher clock speeds and
the need for additional clock cycles due to data dependencies.
This architectural choice is suitable for both preprocessing
and detection, requires almost no control overhead to switch
between these modes, and provides a balance between speed
and resource utilization.
In this configuration the proposed circuit runs at a clock
frequency of 40 MHz on the targeted Xilinx XC2V6000-6
FPGA. For the preprocessing, this clock frequency entails a
delay of 2.2 s per OFDM tone and, for the detection, 40
tones can be processed in the duration of one OFDM sym-
bol. Unfortunately, maintaining real-time performance for the
system under consideration requires a detection throughput of
52 tones per OFDM symbol6. In addition to that, a FIFO buffer
for 29 MIMO-OFDM symbols is required to store the data
symbols arriving during the preprocessing latency of 114.4 s
to avoid a loss of data. The chosen straightforward solution
to achieve real-time detection performance for the proposed
system is to instantiate two identical MIMO processing units
to process two tones in parallel. In this configuration, the
preprocessing of 52 tones incurs a latency of 57.2 s which
reduces the size of the required FIFO buffer. Moreover, the
MIMO detection can now process up to 80 instead of the
required 52 received vectors r[k, t] per OFDM-symbol interval
6 Detection is performed for all 48 data-bearing tones and for the 4 pilot
tones used for tracking as described in Section III-D.
HAENE et al.: A REAL-TIME 4-STREAM MIMO-OFDM TRANSCEIVER: SYSTEM DESIGN, FPGA IMPLEMENTATION, AND CHARACTERIZATION 885

TABLE I
so that the receiver can catch up with the incoming data stream R EQUIRED FPGA RESOURCES
after 27 OFDM symbols.
XC2V6000-6 FPGA
Block Slice %Slice Mult Ram
E. Pilot Tracking
Synchronization and 5038 17.6 17 5
The pilot tracking implements (6) and (7) to estimate tracking
the impact of RFO and SRO using the post-linear-detection FIFO memories 0 0 0 32
algorithm. To avoid the storage of an entire OFDM symbol, a OFDM de/modulation 2879 10.1 12 12
prediction of the correcting phasor based on the estimates of MIMO processing and 8847 31.0 32 10
the two last OFDM symbols is applied to the current OFDM channel estimation
symbol. A CORDIC circuit is employed to implement the Channel decoding and 9082 31.8 4 5
bit-metric unit
(.) function. For the compensation, the correcting phasor
Others 2725 9.5 0 70
is retrieved from a LUT and a complex-valued multiplier is
Total 28571 100 65 134
used to process all four streams in a time-interleaved fashion.
XC2V1000-4 FPGAs
Block Slice %Slice Mult Ram
F. Bit-Metric Unit DUC 980 19.5 20 0
The SINR-independent part (b , si ) of the bit-metric is a DDC 997 19.8 6 0
piecewise linear function that can be scaled so that the slope of AGC 940 18.7 4 0
the different segments is one of 1, 2, 3, 4. Hence, (b , si ) Others 2113 42.0 0 39
can be implemented with comparators and adders only. The Total 5030 100 30 39
product of the per-stream SINR i [k] with (b , si ) in (9) is
computed using one multiplier for each received stream. This
multiplication produces values with a dynamic range well in mapped onto the XC2V1000-4 FPGA located on the asso-
excess of the 5-bit input word width of the Viterbi decoder ciated data converter module. The required FPGA resources
used in the testbed. Fortunately, the bit error rate performance for the two FPGA designs are detailed in Table I, where
is insensitive to the quantization of the bit-metrics. Mult and Ram refer to the built-in signed 18 bit18 bit
multipliers and 18 kbit RAMs, respectively. The resources
reported under Others refer to PCI interface, debugging
G. Channel Decoding and analysis circuitry, intermodule-communication interfaces,
Per-stream convolutional coding with subsequent cross- and other functional units that are not strictly related to the
antenna interleaving, as shown in Fig. 1, allows the processing physical layer signal processing.
of the computed soft-metrics on MT parallel Viterbi decoders. In summary, the circuits for the signal processing need a
This enables the real-time decoding on Virtex-II FPGAs. The total of 64 RAMs, whereof 32 are used for the FIFO buffer
parallel decoders are implemented following the approach required to bridge the latency incurred by the MIMO prepro-
introduced in [30] and [2], where a single hardware unit cessing and channel estimation. This buffer was intentionally
processes multiple data streams in an interleaved fashion. This oversized (by at least a factor of two) to enable special debug
allows to pipeline the add-compare-select recursion which is modes that allow to access the received data directly after the
the throughput bottleneck in conventional single-steam Viterbi FFT or after the pilot tracking. Hence, a significant amount of
decoders. With this architecture, real-time performance is memory could be saved in a real-world system by eliminating
achieved with reduced FPGA resources compared to MT these debug modes.
conventional decoders. The decoders process 5-bit-wide soft- In terms of throughput, all blocks in the testbed are designed
metrics. Traceback is implemented with the register-exchange to meet the real-time requirements imposed by the 20 MHz
technique and the traceback length was selected to be 54 trellis communication bandwidth and by the 216 Mbit/s throughput
steps long. supported by the system. In terms of latency, the delay
Interleaver and deinterleaver are based on dual-ported between the start of the frame and the time when the first
RAMs that allow the concurrent storage and retrieval, accord- bits are available at the output of the receiver is dominated by
ing to the interleaving pattern, of bits (or LLRs) pertaining the 57.2 s preprocessing latency discussed in Sec. V-D. The
two different OFDM symbols. Puncturing and depuncturing use of the channel estimation refinement algorithm, described
are hardware uncritical operations that require only a corre- in Sec. III-B increases this latency by an additional 42 s. In
sponding finite state machine. Scrambling and descrambling comparison, the latency of all other blocks is insignificant.
perform a bit-wise exclusive-OR combination of the payload
data with the output of a linear feedback shift register. VII. M EASUREMENTS AND C HARACTERIZATION
A. Measurement Setup
VI. I MPLEMENTATION R ESULTS Measurements were taken with two real-time terminals
The digital signal processing blocks shown in Fig. 5 are communicating over a wideband multipath channel emulator,
integrated on a single XC2V6000-6 FPGA, with the exception as shown in Fig. 8. In place of antennas, the multi-antenna
of DUC, DDC, and digital AGC gain stages. For each antenna RF transceivers are connected directly to a MIMO channel
pair, the corresponding instances of these three blocks are emulator, which supports RF inputs and outputs. Time-varying
886
Tx MIMO-OFDM terminal Multipath MIMO Rx MIMO-OFDM terminal
(slave) channel emulator (master)
Host
RF RF
computer
Wired TCP/IP network
Fig. 8. The measurement setup includes two MIMO-OFDM terminals and
a real-time wideband multipath fading channel emulator.
MIMO channels with antenna configurations up to 4 4
and channel impulse responses with up to 12 sample-spaced
taps per SISO subchannel are supported. The measurement
operations are coordinated over a wired TCP/IP network by
the receiver terminal. The transmit terminal acts as a server
and generates MIMO-OFDM frames upon request. Channel
emulator settings, such as the wireless-channel model and
output power of the channel emulator, are also controlled over
TCP/IP. MIMO-OFDM frames at the channel emulator input,
generated by the transmitting terminal, exhibit a constant
power level. After applying the desired channel model, the
average power at the RF inputs of the receiver is controlled
by adjusting the output gain of the emulator.
B. Performance of Coded MIMO-OFDM
The performance of coded MIMO-OFDM is assessed by
enabling all physical layer receiver functions. Payload data is
transferred to the transmitter over the wired TCP/IP network,
which enables the receiver to check the decoded frames for
bit errors.
1) Performance Metrics: By averaging measurement re-
sults over Nch channel realizations, two different performance
metrics are computed as described in the following. A channel
realization labeled l is drawn according to the desired statistics
and uploaded to the emulator. Multiple OFDM frames carrying
500 bytes payload data each are transmitted over the selected
channel for each of the supported transmission modes m. An
empirical frame error rate (FER) PFER [m, l] is computed for
each transmission mode and channel realization by counting
the number of incorrectly received frames. For each trans-
mission mode, the per-mode average throughput Tm is then
computed as
1 
Nch
Tm = Tm (1 PFER [m, l]),
Nch
l=1
where Tm is the physical layer data rate of the transmission
mode m, as reported in Table II.
Assuming genie-aided adaptive modulation, for each chan-
nel realization the transmission mode providing the best
throughput is selected. Based on this assumption, the overall
average throughput T is computed as
Nch
1 
T = max Tm (1 PFER [m, l]).
Nch m simulation results in [4], the word widths of the corresponding
l=1
Optimal per-channel-realization transmission-mode selec-
tion is realistic only for scenarios with slowly varying chan-
nels, such as indoor WLAN channels, where the transmitter
IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 26, NO. 6, AUGUST 2008
TABLE II
C ONSIDERED 4 4 DATA RATES Tm IN [M BIT / S ]
Host Coding Subcarrier modulation
computer
rate Rc BPSK QPSK 16-QAM 64-QAM
1/2 24 48 96 144
2/3 - - - 192
3/4 36 72 144 216
has sufficient time to determine the highest mode supported
by the current channel conditions. In mobile scenarios, where
the wireless channel is changing faster, this assumption is
definitely optimistic.
Performance charts for coded MIMO-OFDM were obtained
by computing Tm and T for different average receive powers.
All measurements were taken with 100 kHz frequency offset
and 1.6 kHz sample-rate offset, which corresponds to a 20 ppm
frequency reference precision. The number of channel real-
izations was Nch = 500 and the empirical FER PFER [m, l]
was computed based on the transmission of 20 frames per
channel realization. Block fading is assumed and the emulated
channel is not changed during the transmission of MIMO-
OFDM frames. Unless otherwise specified, channels were
generated based on the TGn models [45], assuming an antenna
spacing of two wavelengths both at the transmitter and at the
receiver. For all measurements, only the four-stream transmis-
sion modes listed in Table II were taken into consideration.
2) Performance for Different Channel Models: The mea-
sured average throughput T under different block-fading chan-
nel scenarios is shown in Fig. 9. TGn-A is a flat-fading
channel, while TGn-B and TGn-C have a delay spread of
80 ns and 200 ns, respectively7. For comparison, a spatially un-
correlated Rayleigh fading channel with uniform power delay
profile and two taps spaced 50 ns apart was also considered.
From the chart in Fig. 9 it can be observed that the system
suffers from increasing channel lengths. However, the impact
of different channel models is not extremely significant. The
non-fluent behavior of the curves in the region around -33 dBm
average input power is due to spurious interference signals
generated by the channel emulator. The power of these spurs
was observed not to increase proportionally to the selected
channel emulator output power.
The per-mode average throughput Tm over TGn-A is shown
in Fig. 10 for the transmission modes with code rate Rc = 1/2
(see Table II). While BPSK transmission is supported over
the entire range, with increasing emulator output power also
the higher modes (QPSK, 16-QAM, and 64-QAM) become
reliable. However, the curves for 16-QAM and 64-QAM sat-
urate before reaching their corresponding Tm (96 Mbit/s and
144 Mbit/s, respectively). This observation can be attributed
to the channel emulator and to the discrete multi-antenna
RF transceivers, which limit the receive SNR. Additionally,
for high SNRs the numerical precision of the linear MIMO
detector units becomes a limiting factor. According to the
7 Channel models TGn-B and TGn-C are defined based on a tap spacing of
10 ns and hence need to be resampled. This operation potentially generates
more than the 12 taps supported by the channel emulator, so that the effective
channels are only a best-effort approximation to the TGn channel models.
HAENE et al.: A REAL-TIME 4-STREAM MIMO-OFDM TRANSCEIVER: SYSTEM DESIGN, FPGA IMPLEMENTATION, AND CHARACTERIZATION 887

160 160

140 140
Average throughput [Mbps]

Average throughput [Mbps]

120 120

100 100

80 80

60 TGn-A (0 ns)
60 Flat Rayleigh Fading
TGn-B (80 ns)
TGn-C (200 ns) TGn-A, antenna spacing 100
40 40 TGn-A, antenna spacing 2
2 tap, flat PDP (50 ns)
TGn-A, antenna spacing 1
20 20 TGn-A, antenna spacing 0.5
0 0
-63 -58 -53 -48 -43 -38 -33 -28 -63 -58 -53 -48 -43 -38 -33 -28
Average receive power [dBm] Average receive power [dBm]

Fig. 9. Average throughput T for different channel models. Fig. 11. Impact of different antenna spacings on the average throughput T
achieved over a TGn-A channel.
144 Mbps
140 160
64QAM, R=1/2
Permode average throughput [Mbps]

120 16QAM, R=1/2 140

QPSK, R=1/2

Average throughput [Mbps]

BPSK, R=1/2 96 Mbps 120
100
100
80
80
60
60
40
40
All receiver algorithms on
20 Enhanced channel estimation off
20
Soft information extraction off
0 0
-63 -58 -53 -48 -43 -38 -33 -28 -63 -58 -53 -48 -43 -38 -33 -28
Average receive power [dBm] Average receive power [dBm]

Fig. 10. Per-mode average throughput Tm over TGn-A for the transmission Fig. 12. Impact of channel estimation refinement and soft-information
modes in Table II with coding rate Rc = 1/2. extraction on the average throughput T over a TGn-B channel.

multipliers must be increased beyond 18 bit (which is the word
width of the FPGA built-in multipliers) for SNRs in excess
of 30 dB, when operating in an uncorrelated Rayleigh-fading
environment. These limitations explain why the measured
average throughputs T in Fig. 9 saturate between 120 Mbit/s
and 140 Mbit/s, even though the highest physical layer data
rate in Table II is much higher (216 Mbit/s).
3) Impact of Antenna Correlation: When reducing the
antenna spacing, the correlation between the received signals
increases and linear MIMO detection becomes less reliable.
The impact of this correlation is shown in Fig. 11 for the
particular case of TGn-A, where the antenna spacing is set
to 100, 2, 1, and 0.5 wavelengths. For comparison a flat
Rayleigh-fading channel, corresponding to the special case
of TGn-A without any spatial correlation, is considered. As
expected, the system suffers significantly when the antenna
spacing is reduced below one wavelength.
4) Impact of Channel Estimation Refinement and Soft-
Output MIMO Detection: The impact of channel estimation
refinement and soft-information extraction on the average
8 Only the overhead related to the bit-metric unit is considered. The
difference in silicon area between hard-input and soft-input Viterbi decoding
is not considered.
throughput is investigated in the following. The FPGA re-
sources required to support these algorithms are reported in
Table III, where the slice percentage refers to the total number
of used slices on the XC2V6000-6 FPGA (given in Table I).
In order to assess the impact of these algorithms on
performance, channel estimation refinement can be skipped,
and the extraction of soft-information can be replaced with
simpler hard-decision MIMO detection. The measured average
throughput T achieved over a TGn-B channel is shown in
Fig. 12. The performance with all receiver algorithms enabled
corresponds to the topmost curve. For comparison, the per-
formance was measured after disabling channel estimation
refinement and once again after additionally disabling the
extraction of LLRs. The average throughput Tm achieved with
16-QAM and Rc = 1/2 is shown in Fig. 13. From this
figure, channel estimation refinement yields an SNR gain of
about 2 dB. The impact of soft-information extraction, which
is slightly harder to determine because the curves saturate at
different levels due to the SNR limitation, amounts to about
2.5 dB to 3.7 dB.
In summary, the curves in Fig. 13 and the numbers in
Table III show that with a combination of the two receiver
algorithms, an overall SNR gain of about 4.5 dB to 5.7 dB
888 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 26, NO. 6, AUGUST 2008
TABLE III
I MPACT ON REQUIRED FPGA RESOURCES FOR CHANNEL ESTIMATION
REFINEMENT AND SOFT- INFORMATION EXTRACTION
Algorithm Slice %Slice Mult Ram
Refined channel estimation 710 2.5 - -
Soft-information extraction8 625 2.2 4 2
Total 1335 4.7 4 2
can be achieved with roughly 5% increase in FPGA-resource
utilization.
VIII. C ONCLUSION
A real-time MIMO-OFDM physical layer transmitting at
a peak data rate of 216 Mbit/s over 20 MHz bandwidth was
prototyped and characterized through measurements. Real-
time operation of the system on an FPGA was achieved by
diligent selection and optimization of the employed transceiver
algorithms for the FPGA implementation and by careful
design of the corresponding transceiver hardware architecture.
With respect to the signal processing, it is found that many
functional units are identical for all antennas. In the FPGA im-
plementation, this property can often be exploited to perform
the associated signal processing on a single entity in a time-
interleaved fashion. This architectural optimization allows to
reduce the resource utilization compared to straightforward
replication of the corresponding hardware.
One of the most critical parts in the system is the MIMO
detector. For this prototype a linear detector was chosen to en-
able a real-time FPGA implementation of soft-output MIMO
detection with reasonable resource utilization. Nevertheless,
the separation of the spatial streams accounts for 30% of the
FPGA slices and 50% of the multipliers used by the physical
layer design. Moreover, it was found that the preprocessing of
the channel matrices in the MIMO detector is one of the main
complexity bottlenecks which can incur considerable detection
latency and thus requires large FIFO buffers in the receiver.
Compared to legacy single-antenna IEEE 802.11a WLAN
systems, which transmit over the same bandwidth but are
limited to a peak data rate of 54 Mbit/s, the measured average
data rates are clearly higher. It was observed that the system
performance is affected by channels with increasing delay
spread and by high antenna correlation. As expected, the
MIMO gain is reduced when the antenna spacing is not
sufficient.
By considering the specific examples of channel estima-
tion refinement and soft information extraction, it is found
that careful algorithm and architecture optimization allows to
achieve a considerable performance improvement at the cost
of only marginal complexity increase.
ACKNOWLEDGMENT
The authors wish to thank Prof. Bolcskei for his guidance,
Prof. Fichtner for his support, and their colleagues D. Baum,
P. Luethi, and M. Borgmann for their contributions and
invaluable discussions. The ETH Zurich and the FP6 STREP
project MASCOT are acknowledged for partial funding of this
work under the project numbers TH-602-02 and IST-026905,
respectively.
100
Permode average throughput [Mbps]
80
60
3.7 dB
2 dB
40
20 2.5 dB All receiver algorithms on
Enhanced channel estimation off
Soft information extraction off
0
-63 -58 -53 -48 -43 -38 -33 -28
Average receive power [dBm]
Fig. 13. Impact of channel estimation refinement and soft-information
extraction on Tm over TGn-B with 16-QAM, Rc = 1/2.
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Simon Haene (S03M08) was born in Basel,
Switzerland, in 1978. He received the Diploma
degree in electrical engineering from ETH Zurich,
Switzerland, in 2002. He then joined the Integrated
Systems Laboratory of ETH Zurich, and graduated
with a Dr. sc. ETH degree in 2007. In the same
year, he co-founded Celestrius, an ETH-spinoff in
the field of MIMO wireless communication. In 2000,
he held a summer researcher position at British
Telecom, England.
His research interests include the design of VLSI
circuits, digital signal processing for wireless communication systems, and
FPGA-based prototyping.
David Perels (S94M97) was born on April 15th
1972 in Heidelberg, Germany. He studied electrical
engineering from 1992 to 1997 at the ETH Zurich,
Switzerland, and received his Diploma degree in
1997.
From 1997 to 2001 he worked at Swisscom
Mobile in the field of mobile communications and
mobile data services. In 2001 he joined the Inte-
grated Systems Laboratory at ETH Zurich where he
graduated with a Dr. sc. techn. degree in 2007 in the
field of VLSI design for wireless communications.
Mr. Perels is currently working at Phonak, a hearing instrument manufacturer,
in the research and development department.
Andreas Burg (S97M05) was born in Munich,
Germany, in 1975. He received his Dipl.-Ing. de-
gree in 2000 from the Swiss Federal Institute of
Technology (ETH) Zurich, Zurich, Switzerland. He
then joined the Integrated Systems Laboratory of
ETH Zurich, from where he graduated with the
Dr. sc. techn. degree in 2006.
In 1998, he worked at Siemens Semiconductors,
San Jose, CA. During his doctoral studies, he was a
visiting researcher with Bell Labs Wireless Research
for a total of one year. From 2006 to 2007, he held
positions as postdoctoral researcher at the Integrated Systems Laboratory and
at the Communication Technology Laboratory of the ETH Zurich. In 2007
he co-founded Celestrius, an ETH-spinoff in the field of MIMO wireless
communication, where he is responsible for the VLSI development. His
research interests include the design of digital VLSI circuits and systems,
signal processing for wireless communications, and deep submicron VLSI
design.
In 2000, Mr. Burg received the Willi Studer Award and the ETH Medal
for his diploma and his diploma thesis, respectively. Mr. Burg was also
awarded an ETH Medal for his Ph.D. dissertation in 2006. In 2008, Dr. Burg
was awarded a 4-years grant from the Swiss National Science Foundation
(SNF) on which he will join the ETH Zurich as an SNF Professor in 2008.