Name:

Student ID:

Eskiehir Osmangazi University

Digital Systems II(A), Homework I
Spring 2005-06, Due date: 16.03.2006

Quiz I
Chapter 6: Flip-flops (master slave, edge-triggered), analysis and design of sequential circuits.
March 16/2006

1. For the gated D latch, sketch the output Q. Assume Q=0 initially.

D
D Q

C Q' C

2. For JK master-slave flip-flop, the waveform shown below is observed on its inputs. Sketch the Q
output. Assume that Q=0 initially.

J
J Q

C K

K Q' Master
Output
(Y)

3. Sketch the output Q of the edge triggered D flip-flop. The flip-flop is initially RESET.

D
D Q
C
CLK Q'

Draw the waveforms on this page and hand in it with your homework solutions.
4. A sequential circuit has two JK flip-flops A and B, two inputs x and y, and one output z. The flip-flop
input equations and circuit output equation are

J A = Bx + By K A = Bxy
J B = Ax K B = A + xy
z =A x y+B x y

a) Draw the logic diagram of the circuit.

b) Drive the state table.
c) Drive the state diagram.
d) Starting from the 00 state in the state diagram, determine the state transitions and output sequence that
will generated when an input sequence of 11, 00, 11, 10, 01.

5. Design a sequential circuit with two D flip-flops A and B and one input X. When X= 0, the state of
the circuit remains the same. When X= 1, the circuit goes through the state transitions from 00 to 10
to 01 to 11, back to 00, and than repeats.

6. Design one input, one output serial 2s complementer. The circuit accepts a string of bits from the
input and generates the 2s complement at the output. The circuit can be reset asynchronously to start
and end the operation.

a) Find the Mealy model state diagram for the circuit.

b) Find the state table for the circuit and make a state assignment using Gray codes.
c) Find implementation of the circuit using D flip-flops and logic gates.

2complement method (read pp.212-213, Mano & Kime 3e):

Given: an n-bit binary number, beginning at the least significant bit and proceeding upward:
Copy all least significant 0s
Copy the first 1
Complement all bits thereafter

2s
01010110100100 Complementer 00111010010101
LSB LSB

http://www.ogu.edu.tr/~redizkan/DigitalSysII06_HW1.pdf