Beruflich Dokumente
Kultur Dokumente
Logic Symbols
TL071
TL072 (each amplifier)
OFFSET N1 TL074 (each amplifier)
IN+ + IN+ +
OUT OUT
IN IN
OFFSET N2
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B
SLOS080M SEPTEMBER 1978 REVISED JUNE 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 14
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 14
3 Description ............................................................. 1 9 Application and Implementation ........................ 15
4 Revision History..................................................... 2 9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
5 Pin Configuration and Functions ......................... 3
9.3 System Examples ................................................... 16
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5 10 Power Supply Recommendations ..................... 17
6.2 ESD Ratings.............................................................. 5 11 Layout................................................................... 17
6.3 Recommended Operating Conditions....................... 5 11.1 Layout Guidelines ................................................. 17
6.4 Thermal Information ................................................. 5 11.2 Layout Example .................................................... 18
6.5 Electrical Characteristics, TL07xC, TL07xAC, 12 Device and Documentation Support ................. 19
TL07xBC, TL07xI ...................................................... 6 12.1 Documentation Support ........................................ 19
6.6 Electrical Characteristics, TL07xM............................ 7 12.2 Related Links ........................................................ 19
6.7 Switching Characteristics .......................................... 7 12.3 Community Resources.......................................... 19
6.8 Typical Characteristics .............................................. 8 12.4 Trademarks ........................................................... 19
7 Parameter Measurement Information ................ 12 12.5 Electrostatic Discharge Caution ............................ 19
8 Detailed Description ............................................ 13 12.6 Glossary ................................................................ 19
8.1 Overview ................................................................. 13 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram ....................................... 13 Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature Description
section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations
section, Layout section ........................................................................................................................................................... 1
Moved Typical Characteristics into Specifications section. ................................................................................................... 8
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B
TL071, TL071A, TL071B
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www.ti.com SLOS080M SEPTEMBER 1978 REVISED JUNE 2015
1OUT 1 14 4OUT NC 1 10 NC
1IN 2 13 4IN 1OUT 2 9 VCC+
1IN+ 3 12 4IN+ 1IN 3 8 2OUT
VCC+ 4 11 VCC 1IN+ 4 7 2IN
2IN+ 5 10 3IN+ VCC 5 6 2IN+
2IN 6 9 3IN
2OUT 7 8 3OUT
TL071 FK Package
20-Pin LCCC TL072 FK Package
Top View 20-Pin LCCC
Top View
OFFSET N1
V CC+
1OUT
NC
NC
NC
NC
NC
NC
NC
3 2 1 20 19
NC 4 18 NC
3 2 1 20 19
NC 4 18 NC 1IN 5 17 2OUT
IN 5 17 VCC+ NC 6 16 NC
NC 6 16 NC 1IN+ 7 15 2IN
IN+ 7 15 OUT NC 8 14 NC
NC 8 14 NC 9 10 11 12 13
9 10 11 12 13
V CC
2IN+
NC
NC
NC
V CC
NC
NC
NC
OFFSET N2
TL074 FK Package
20-Pin LCCC
Top View
1OUT
4OUT
1IN
4IN
NC
3 2 1 20 19
1IN+ 4 18 4IN+
NC 5 17 NC
VCC+ 6 16 VCC
NC 7 15 NC
2IN+ 8 14 3IN+
9 10 11 12 13
2IN
3IN
2OUT
NC
3OUT
Pin Functions
PIN
TL071 TL072 TL074
SOIC, I/O DESCRIPTION
NAME SOIC, SOIC,
CDIP,
PDIP, LCCC CDIP, CFP LCCC LCCC
PDIP,
SO PDIP, SO
SO, CFP
1IN 2 3 5 2 3 I Inverting input
1IN+ 3 4 7 3 4 I Non-Inverting input
1OUT 1 2 2 1 2 O Output
2IN 6 7 15 6 9 I Inverting input
2IN+ 5 6 12 5 8 I Non-Inverting input
2OUT 7 8 17 7 10 O Output
3IN 9 13 I Inverting input
3IN+ 10 14 I Non-Inverting input
3OUT 8 12 O Output
4IN 13 19 I Inverting input
4IN+ 12 18 I Non-Inverting input
4OUT 14 20 O Output
IN 2 5 I Inverting input
IN+ 3 7 I Non-Inverting input
1 1
3
4
1 1
6
8
9 9
NC (1) 8 11 11 5 Do not connect
13 13 7
14 14 11
16 0 16 15
18 18
19 17
19
20
OFFSET N1 1 2 Input offset adjustment
OFFSET N2 5 12 Input offset adjustment
OUT 6 15 O Output
VCC 4 10 4 5 10 11 16 Power supply
VCC+ 7 17 8 9 20 4 6 Power supply
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B
www.ti.com SLOS080M SEPTEMBER 1978 REVISED JUNE 2015
6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC+ - VCC Supply voltage (2) 18 18 V
(3)
VID Differential input voltage 30 30 V
VI Input voltage (2) (4) 15 15 V
Duration of output short circuit (5) Unlimited
TJ Operating Virtual Junction Temperature 150 C
Case temperature for 60 seconds - FK package 260 C
Lead temperature 1.8 mm (1/16 inch) from case for 10 seconds 300 C
Tstg Storage temperature 65 150 C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC.
(3) Differential voltages are at IN+, with respect to IN.
(4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
(5) The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the
dissipation rating is not exceeded.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Supply current
ICC VO = 0, No load 25C 1.4 2.5 1.4 2.5 1.4 2.5 1.4 2.5 mA
(each amplifier)
Crosstalk
VO1 /VO2 AVD = 100 25C 120 120 120 120 dB
attenuation
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
(2) Full range is TA = 0C to 70C for TL07_C,TL07_AC, TL07_BC and is TA = 40C to 85C for TL07_I.
(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B
www.ti.com SLOS080M SEPTEMBER 1978 REVISED JUNE 2015
(1) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques must be used that will maintain the junction temperature as close to the ambient temperature as
possible.
(2) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is
TA = 55C to 125C.
100 15
VCC = 15 V VCC = 15 V RL = 10 k
VOM Maximum Peak Output Voltage V
TA = 25C
12.5 See Figure 2
IB Input Bias Current nA
10
10
VCC = 10 V
1 7.5
5 VCC = 5 V
IIIB
0.1
2.5
VOM
0.01 0
75 50 25 0 25 50 75 100 125 100 1k 10 k 100 k 1M 10 M
f Frequency Hz
TA Free-Air Temperature C
Figure 1. Input Bias Current vs Free-Air Temperature Figure 2. Maximum Peak Output Voltage vs Frequency
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B
TL071, TL071A, TL071B
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15
RL = 2 k
VOM Maximum Peak Output Voltage V TA = 25C
12.5 VCC = 15 V
See Figure 2
10
VCC = 10 V
7.5
5
VCC = 5 V
VOM
2.5
8
0
100 1k 10 k 100 k 1M 10 M
f Frequency Hz
Figure 3. Maximum Peak Output Voltage vs Frequency Figure 4. Maximum Peak Output Voltage vs Frequency
15 15
RL = 10 k
VCC = 15 V
OM Maximum Peak Output Voltage V
10 10
7.5 7.5
5 5
2.5 2.5
VOM
VOM
VCC = 15 V
8 8
V
See Figure 2
0 0
75 50 25 0 25 50 75 100 125 0.1 0.2 0.4 0.7 1 2 4 7 10
TA Free-Air Temperature C RL Load Resistance k
Figure 5. Maximum Peak Output Voltage vs Free-Air Figure 6. Maximum Peak Output Voltage vs Load
Temperature Resistance
15 1000
RL = 10 k
VOM Maximum Peak Output Voltage V
TA = 25C 400
12.5
VD Large-Signal Differential
Voltage Amplification V/mV
200
10 100
40
7.5
20
5 10
AAVD
4 VCC = 15 V
2.5
VOM
VO = 10 V
2 RL = 2 k
0 1
0 2 4 6 8 10 12 14 16 75 50 25 0 25 50 75 100 125
|VCC| Supply Voltage V TA Free-Air Temperature C
Figure 7. Maximum Peak Output Voltage vs Supply Voltage Figure 8. Large-Signal Differential Voltage Amplification vs
Free-Air Temperature
1.3 1.03
Phase Shift 1
1
0.9 0.99
VCC = 15 V
0.8 0.98
RL = 2 k
f = B1 for Phase Shift
0.7 0.97
75 50 25 0 25 50 75 100 125
TA Free-Air Temperature C
Figure 9. Large-Signal Differential Voltage Amplification and Figure 10. Normalized Unity-Gain Bandwidth and Phase
Phase Shift vs Frequency Shift vs Free-Air Temperature
89 2
VCC = 15 V
CMRR Common-Mode Rejection Ratio dB
TA = 25C
1.4
87
1.2
86 1
0.8
85
0.6
0.4
84
I CC
0.2
83 0
75 50 25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16
TA Free-Air Temperature C |VCC| Supply Voltage V
Figure 11. Common-Mode Rejection Ratio vs Free-Air Figure 12. Supply Current Per Amplifier vs Supply Voltage
Temperature
2 250
VCC = 15 V VCC =15 V
ICC Supply Current Per Amplifier mA
No Load No Load
1.6 200
1.4 175
TL074
1.2 150
1 125
0.8 100
TL072
0.6 75
0.4 50 TL071
I CC
0.2 25
0 0
75 50 25 0 25 50 75 100 125 75 50 25 0 25 50 75 100 125
TA Free-Air Temperature C TA Free-Air Temperature C
Figure 13. Supply Current Per Amplifier vs Free-Air Figure 14. Total Power Dissipation vs Free-Air Temperature
Temperature
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B
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50
nV/ Hz
VCC = 15 V
30
20
10
0
10 40 100 400 1 k 4 k 10 k 40 k 100 k
f Frequency Hz
Figure 15. Normalized Slew Rate vs Free-Air Temperature Figure 16. Equivalent Input Noise Voltage vs Frequency
1 6
VCC = 15 V VCC = 15 V
VI(RMS) = 6 V 4 CL = 100 pF
TA = 25C TA = 25C
Output
0.1 2
0.04
0
0.01 2
Input
0.004
4
0.001 6
100 400 1k 4 k 10 k 40 k 100 k 0 0.5 1 1.5 2 2.5 3 3.5
f Frequency Hz t Time s
Figure 17. Total Harmonic Distortion vs Frequency Figure 18. Voltage-Follower Large-Signal Pulse Response
OUT
VI +
CL = 100 pF RL = 2 k
10 k
1 k
VI
OUT
+
RL CL = 100 pF
TL071
IN
OUT
N2
IN+
+
N1
100 k
1.5 k
VCC
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B
www.ti.com SLOS080M SEPTEMBER 1978 REVISED JUNE 2015
8 Detailed Description
8.1 Overview
The JFET-input operational amplifiers is in the TL07xx series are similar to the TL08x series, with low input bias
and offset currents and fast slew rate. The low harmonic distortion and low noise make the TL07xx series ideally
suited for high-fidelity and audio preamplifier applications. Each amplifier features JFET inputs (for high input
impedance) coupled with bipolar output stages integrated on a single monolithic chip.
The C-suffix devices are characterized for operation from 0C to 70C. The I-suffix devices are characterized for
operation from 40C to 85C. The M-suffix devices are characterized for operation over the full military
temperature range of 55C to 125C.
VCC+
IN+
IN 64
128
OUT
64
C1
18 pF
1080 1080
VCC
OFFSET OFFSET
N1 N2
TL071 Only
All component values shown are nominal.
COMPONENT COUNT
COMPONENT
TL071 TL072 TL074
TYPE
Resistors 11 22 44
Transistors 14 28 56
JFET 2 4 6
Diodes 1 2 4
Capacitors 1 2 4
epi-FET 1 2 4
Includes bias and trim circuitry
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B
www.ti.com SLOS080M SEPTEMBER 1978 REVISED JUNE 2015
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
RI Vsup+
VOUT
+
VIN
Vsup-
0.5
Volts
-0.5
-1
-1.5
-2
0 0.5 1 1.5 2
Time (ms)
Figure 24. Input and Output Voltages of the Inverting Amplifier
R1 R2 TL071
15 V
3.3 k Output Input
+
Output
C3 VCC
TL071
+
CF = 3.3 F 1 k
R1 = R2 = 2R3 = 1.5 M
15 V R3
C1 C2 C1 = C2 = C3 = 110 pF
3.3 k 2
9.1 k fO = 1 = 1 kHz
1 2 R1 C1
f =
2 R C
F F
Figure 25. 0.5-Hz Square-Wave Oscillator Figure 26. High-Q Notch Filter
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B
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18 pF 1 k
VCC+
VCC+
0.1 F
88.4 k
TL072
88.4 k
+
TL072 6 cos t 10 k
+
VCC
1 k
18 pF
VCC
10 k 1 M
IN
15 V
1N4148 18 k (see Note A)
50 TL071 OUT
88.4 k
IN+
+
N2
N1
0.1 F 10 k
100 k
CAUTION
Supply voltages larger than 36 V for a single-supply or outside the range of 18 V for a
dual-supply can permanently damage the device (see the Absolute Maximum Ratings).
Place 0.1-F bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout.
11 Layout
RIN
VIN +
VOUT
RG
RF
Product Folder Links: TL071 TL071A TL071B TL072 TL072A TL072B TL074 TL074A TL074B
TL071, TL071A, TL071B
TL072, TL072A, TL072B, TL074, TL074A, TL074B
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12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 17-Dec-2015
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 17-Dec-2015
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 17-Dec-2015
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TL071IPE4 ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 85 TL071IP
(RoHS)
TL071MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125
TL071MJG OBSOLETE CDIP JG 8 TBD Call TI Call TI -55 to 125
TL071MJGB OBSOLETE CDIP JG 8 TBD Call TI Call TI -55 to 125
TL072ACD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 072AC
& no Sb/Br)
TL072ACDE4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 072AC
& no Sb/Br)
TL072ACDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 072AC
& no Sb/Br)
TL072ACDRE4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 072AC
& no Sb/Br)
TL072ACDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 072AC
& no Sb/Br)
TL072ACJG OBSOLETE CDIP JG 8 TBD Call TI Call TI 0 to 70
TL072ACP ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 TL072ACP
(RoHS)
TL072ACPE4 ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 TL072ACP
(RoHS)
TL072ACPSR OBSOLETE SO PS 8 TBD Call TI Call TI 0 to 70
TL072ACPSRE4 OBSOLETE SO PS 8 TBD Call TI Call TI 0 to 70
TL072ACPSRG4 OBSOLETE SO PS 8 TBD Call TI Call TI 0 to 70
TL072BCD ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 072BC
& no Sb/Br)
TL072BCDE4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 072BC
& no Sb/Br)
TL072BCDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 072BC
& no Sb/Br)
TL072BCDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 072BC
& no Sb/Br)
TL072BCDRE4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 072BC
& no Sb/Br)
TL072BCDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 072BC
& no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
Addendum-Page 4
PACKAGE OPTION ADDENDUM
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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TL072MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 8102305PA
TL072M
TL072MUB ACTIVE CFP U 10 1 TBD A42 N / A for Pkg Type -55 to 125 8102305HA
TL072M
TL074ACD ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC
& no Sb/Br)
TL074ACDE4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC
& no Sb/Br)
TL074ACDG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC
& no Sb/Br)
TL074ACDR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC
& no Sb/Br)
TL074ACDRE4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC
& no Sb/Br)
TL074ACDRG4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL074AC
& no Sb/Br)
TL074ACJ OBSOLETE CDIP J 14 TBD Call TI Call TI 0 to 70
Addendum-Page 5
PACKAGE OPTION ADDENDUM
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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
Addendum-Page 6
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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
Addendum-Page 7
PACKAGE OPTION ADDENDUM
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Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TL074MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 81023062A
TL074MFKB
TL074MJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 TL074MJ
TL074MJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8102306CA
TL074MJB
TL074MWB ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 8102306DA
TL074MWB
TL081-W ACTIVE WAFERSALE YS 0 TBD Call TI Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 8
PACKAGE OPTION ADDENDUM
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Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 9
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Mar-2016
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Mar-2016
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Mar-2016
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL074ACDR SOIC D 14 2500 333.2 345.9 28.6
TL074ACNSR SO NS 14 2000 367.0 367.0 38.0
TL074BCDR SOIC D 14 2500 333.2 345.9 28.6
TL074CDR SOIC D 14 2500 333.2 345.9 28.6
TL074CDRG4 SOIC D 14 2500 333.2 345.9 28.6
TL074CPWR TSSOP PW 14 2000 367.0 367.0 35.0
TL074IDR SOIC D 14 2500 333.2 345.9 28.6
Pack Materials-Page 3
MECHANICAL DATA
0.400 (10,16)
0.355 (9,00)
8 5
0.280 (7,11)
0.245 (6,22)
1 4
0.065 (1,65)
0.045 (1,14)
0.023 (0,58)
015
0.015 (0,38)
0.100 (2,54) 0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
C
6.6 SEATING PLANE
TYP
6.2
A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1
3.1 2X
2.9
NOTE 3 1.95
4
5
0.30
8X
0.19
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.75 0.15
0 -8 0.05
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
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EXAMPLE BOARD LAYOUT
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45) SYMM
(R0.05)
1 TYP
8
SYMM
6X (0.65)
5
4
(5.8)
4221848/A 02/2015
NOTES: (continued)
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EXAMPLE STENCIL DESIGN
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM (R0.05) TYP
8X (0.45)
1
8
SYMM
6X (0.65)
5
4
(5.8)
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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