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Version D-2010.03-SP1 for sparcOS5 -- Apr 26, 2010
Copyright (c) 1988-2010 by Synopsys, Inc.
ALL RIGHTS RESERVED
This software and the associated documentation are confidential and
proprietary to Synopsys, Inc. Your use or disclosure of this software
is subject to the terms and conditions of a written license agreement
between you, or your company, and Synopsys, Inc.
The above trademark notice does not imply that you are licensed to use
all of the listed products. You are licensed to use only those products
for which you have lawfully obtained a valid license key.
Initializing...
set link_library *
*
set target_library [list /opt/CAD/Synopsys/Current/Synthesis/libraries/syn/class
.db]
/opt/CAD/Synopsys/Current/Synthesis/libraries/syn/class.db
set synthetic_library [list /opt/CAD/Synopsys/Current/Synthesis/libraries/syn/cl
ass.sdb ]
/opt/CAD/Synopsys/Current/Synthesis/libraries/syn/class.sdb
set link_library [concat $link_library $synthetic_library $target_library]
* /opt/CAD/Synopsys/Current/Synthesis/libraries/syn/class.sdb /opt/CAD/Synopsys/
Current/Synthesis/libraries/syn/class.db
######################### ADD SCAN CHAIN SCRIPT ##############################
#
################################################################################
#
# Read in the RTL Design
################################################################################
#
analyze -format vhdl bigapple.vhd
Running PRESTO HDLC
Compiling Entity Declaration MUX
Compiling Architecture MUX_ARC of MUX
Warning: ./bigapple.vhd:20: The architecture mux_arc has already been analyzed.
It is being replaced. (VHD-4)
Compiling Entity Declaration COMPARATOR
Compiling Architecture COMPARATOR_ARC of COMPARATOR
Warning: ./bigapple.vhd:48: The architecture comparator_arc has already been an
alyzed. It is being replaced. (VHD-4)
Compiling Entity Declaration SUBTRACTOR
Compiling Architecture SUBTRACTOR_ARC of SUBTRACTOR
Warning: ./bigapple.vhd:79: The architecture subtractor_arc has already been an
alyzed. It is being replaced. (VHD-4)
Compiling Entity Declaration REGIS
Compiling Architecture REGIS_ARC of REGIS
Warning: ./bigapple.vhd:113: The architecture regis_arc has already been analyz
ed. It is being replaced. (VHD-4)
Compiling Entity Declaration FSM
Compiling Architecture FSM_ARC of FSM
Warning: ./bigapple.vhd:141: The architecture fsm_arc has already been analyzed
. It is being replaced. (VHD-4)
Compiling Entity Declaration GCD
Compiling Architecture GCD_ARC of GCD
Warning: ./bigapple.vhd:253: The architecture gcd_arc has already been analyzed
. It is being replaced. (VHD-4)
Compiling Entity Declaration GCD_BSD
Compiling Architecture GCD_BSD_ARC of GCD_BSD
Warning: ./bigapple.vhd:334: The architecture gcd_bsd_arc has already been anal
yzed. It is being replaced. (VHD-4)
Presto compilation completed successfully.
Loading db file '/opt/CAD/Synopsys/Current/Synthesis/libraries/syn/class.sdb'
Loading db file '/opt/CAD/Synopsys/Current/Synthesis/libraries/syn/class.db'
1
elaborate gcd
Loading db file '/opt/CAD/Synopsys/Current/syn/libraries/syn/gtech.db'
Loading db file '/opt/CAD/Synopsys/Current/syn/libraries/syn/standard.sldb'
Loading link library 'class'
Loading link library 'gtech'
Running PRESTO HDLC
Presto compilation completed successfully.
Elaborated 1 design.
Current design is now 'gcd'.
Information: Building the design 'fsm'. (HDL-193)
Statistics for case statements in always block at line 156 in file
'./bigapple.vhd'
===============================================
| Line | full/ parallel |
===============================================
| 158 | auto/auto |
===============================================
Inferred memory devices in process
in routine fsm line 147 in file
'./bigapple.vhd'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| cState_reg | Flip-flop | 3 | Y | N | Y | N | N | N | N |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'mux'. (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'regis'. (HDL-193)
Inferred memory devices in process
in routine regis line 115 in file
'./bigapple.vhd'.
===============================================================================
| Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
| output_reg | Flip-flop | 4 | Y | N | Y | N | N | N | N |
===============================================================================
Presto compilation completed successfully.
Information: Building the design 'comparator'. (HDL-193)
Presto compilation completed successfully.
Information: Building the design 'subtractor'. (HDL-193)
Presto compilation completed successfully.
1
check_design -multiple_designs
Warning: In design 'comparator', cell 'C38' does not drive any nets. (LINT-1)
Warning: In design 'subtractor', cell 'C73' does not drive any nets. (LINT-1)
Warning: In design 'subtractor', cell 'C76' does not drive any nets. (LINT-1)
Information: Design 'mux' is instantiated 2 times. (LINT-45)
Cell 'X_MUX' in design 'gcd'
Cell 'Y_MUX' in design 'gcd'
Information: Design 'regis' is instantiated 3 times. (LINT-45)
Cell 'X_REG' in design 'gcd'
Cell 'Y_REG' in design 'gcd'
Cell 'OUT_REG' in design 'gcd'
1
################################################################################
#
# Apply Additional Optimization Constraints
################################################################################
#
# Prevent assignment statements in the Verilog netlist.
set_fix_multiple_port_nets -all -buffer_constants
1
################################################################################
#
# Compile the Design
################################################################################
#
compile -scan
Information: Choosing a test methodology will restrict the optimization of seque
ntial cells. (UIO-12)
Information: Evaluating DesignWare library utilization. (UISN-27)
============================================================================
| DesignWare Building Block Library | Version | Available |
============================================================================
| Basic DW Building Blocks | D-2010.03-DWBB_1004 | * |
| Licensed DW Building Blocks | | |
| class.sdb | | |
============================================================================
Information: There are 3 potential problems in your design. Please run 'check_de
sign' for more information. (LINT-99)
****************************************
No user-defined segments
No multibit segments
****************************************
No cells have scan true
No cells have scan false
No tristate nets.
No bidirectionals.
========================================
AS BUILT BY insert_dft
========================================
Scan_path Len ScanDataIn ScanDataOut ScanEnable MasterClock SlaveClock
----------- ----- ----------- ----------- ----------- ----------- -----------
I chain0 15 test_si test_so test_se clk -
1
report_cell
****************************************
Report : cell
Design : gcd
Version: D-2010.03-SP1
Date : Sun May 23 18:31:39 2010
****************************************
Attributes:
b - black box (unknown)
h - hierarchical
n - noncombinational
r - removable
u - contains unmapped logic
Cell Reference Library Area Attributes
--------------------------------------------------------------------------------
OUT_REG regis_4 57.000000 h, n
TOFSM fsm_0 57.000000 h, n
U_COMP comparator_0 28.000000 h
X_MUX mux_2 15.000000 h
X_REG regis_3 57.000000 h, n
X_SUB subtractor_0 83.000000 h
Y_MUX mux_3 15.000000 h
Y_REG regis_5 57.000000 h, n
--------------------------------------------------------------------------------
Total 8 cells 369.000000
1
write_test_protocol -output ./src/gcd_scan_syn.spf
Writing test protocol file '/home/carsondk/work/test/src/gcd_scan_syn.spf' for m
ode 'Internal_scan'...
1
write -f verilog -hierarchy -output ./src/gcd_scan_syn.v
Writing verilog file '/home/carsondk/work/test/src/gcd_scan_syn.v'.
1
################################################################################
#
# Write Out Final Design and Reports (without BSD)
################################################################################
#Information: Defining new variable 'hlo_collapse_intermediate_hardware_alts'. (
CMD-041)
Information: Defining new variable 'compile_group_pull_control_logic'. (CMD-041)
Information: Defining new variable 'test_enable_dft_drc'. (CMD-041)
design_vision> Current design is 'gcd'.
Current design is 'gcd'.
design_vision> design_vision> exit
Information: Defining new variable 'tixComboBox'. (CMD-041)
Information: Defining new variable 'tixScrolledListBox'. (CMD-041)
Information: Defining new variable 'tixLabelWidget'. (CMD-041)
Information: Defining new variable 'v'. (CMD-041)
Information: Defining new variable 'tixEvent'. (CMD-041)
Information: Defining new variable 'tixControl'. (CMD-041)
Information: Defining new variable 'tixFloatEntry'. (CMD-041)
Information: Defining new variable 'tk_strictMotif'. (CMD-041)
Information: Defining new variable 'tixPrimOpt'. (CMD-041)
Information: Defining new variable 'tix'. (CMD-041)
Information: Defining new variable '_tix_event_flags'. (CMD-041)
Information: Defining new variable 'no_gui'. (CMD-041)
Information: Defining new variable 'tk_patchLevel'. (CMD-041)
Information: Defining new variable 'widget_geom'. (CMD-041)
Information: Defining new variable 'tix_library'. (CMD-041)
Information: Defining new variable 'tix_version'. (CMD-041)
Information: Defining new variable 'tix_release'. (CMD-041)
Information: Defining new variable 'tixScrolledGrid'. (CMD-041)
Information: Defining new variable 'tix_priv'. (CMD-041)
Information: Defining new variable 'tixLabelEntry'. (CMD-041)
Information: Defining new variable 'tixButtonBox'. (CMD-041)
Information: Defining new variable 'tix_patchLevel'. (CMD-041)
Information: Defining new variable 'tixAppContext'. (CMD-041)
Information: Defining new variable 'tixScrolledWidget'. (CMD-041)
Information: Defining new variable 'tkPriv'. (CMD-041)
Information: Defining new variable 'tixPrimitive'. (CMD-041)
Information: Defining new variable 'opt'. (CMD-041)
Information: Defining new variable 'tixOption'. (CMD-041)
Information: Defining new variable 'tk_library'. (CMD-041)
Information: Defining new variable 'tk_version'. (CMD-041)
Thank you...