2011 IEEE Applied Power Electronics Colloquium (IAPEC)
FPGA Based High Precision Torque and Flux
Estimator of Direct Torque Control Drives
Tole Sutikno, Nik Rumzi Nik Idris, Aiman Zakwan Jidin, Mohd Zaki Daud
Department of Energy Conversion, Faculty of Electrical Engineering, Universiti Teknologi Malaysia (UTM)
email: thsutikno@gmail.com, nikrumzi@ieee.org
Abstract- This paper presents an improved FPGA-based torque
and stator flux estimators for direct torque control (DTC)
induction motor drives, which permit very fast calculations. The
improvements are performed by 1) using twos complement
fixed-point format approach to minimize calculation errors and
the hardware resources usage in all operations, 2) calculating the
discrete integration operation of stator flux using backward
Euler approach, 3) modifying the non-restoring method to
calculate complicated square root operation of stator flux, 4)
introducing a new sector judgment method, and 5) reducing the
sampling frequency down to 5s. To avoid saturation due to DC
offset present in the sensed currents, the LP Filter is applied. The
simulation results of DTC model in MATLAB/Simulink, which
performed double-precision calculations, are used as references
to digital computations executed in FPGA implementation. The
Hardware-in-the-loop (HIL) method is used to verify the minimal
error between MATLAB/Simulink simulation and the
experimental results, and thus the well functionality of the
implemented estimators.
I. INTRODUCTION
Direct Torque control (DTC) was first introduced by
Takahashi (1986) [1] and Depenbrock (1988) [2] as an
alternative for controlling induction machines. It has simple
structure with fast torque response. Furthermore, it does not
require PWM pulse generator, coordinate transformation,
position encoder as well as current regulators [3-5].
The DTC algorithm is frequently implemented by serial
calculations based on a Microcontroller or Digital Signal
Processor (DSP) [3-4, 6]. These hardware are truly software-
based platform and is not suitable for an implementation that
require high-speed computation. As a solution, FPGA is
proposed to perform very fast executions [5, 7]. Moreover, the
high sampling frequency in FPGA allows the minimization of
torque ripple [8-10].
Unfortunately, it is not easy to implement DTC in FPGA
device, especially in performing the torque and flux estimation
Complex digital computations are involved, such as binary
multiplications, integral operation and also a square root
calculation targeted for FPGA implementation; the difficulties
of which have been addressed in several researches [11-15].
According to [1-2], sampling time is the crucial part of
torque and flux estimation in DTC. Toh [12] has implemented
all parts of the DTC in FPGA hardware except for torque and
flux estimator whereby it was estimated using the DSP; as a
result, the sampling time was reduced to 55s. On the other
hand, Monmasson [5] has developed the implementation of
978-1-4577-0008-8/11/$26.00 2011 IEEE
DTC in FPGA hardware. However since it was implemented
using a Xilinx System Generator fixed-point toolbox, the
sampling time is limited to 50s. Ferreira [13] also has
difficulty in increasing the sampling frequency, and he only
succeeded in reducing the sampling time to 25s. Other work
include [16] with a sampling time of 25s, and [14, 17] of
150 s and 100s respectively.
The main contribution of the research presented in this
paper is the new design of the torque and flux estimator for
DTC implementation in FPGA, with a sampling time reduced
to 5s. In the design, new implementation architecture,
improved digital properties, new square root algorithm and
new sector identification method is introduced. They are
implemented by using twos complement fixed-point
representation with variable words sizes. The design is
prepared for fast computation, and therefore there is no need
of using CORDIC algorithm [5, 15], soft-core CPU [16], as
well as transformation from Cartesian to polar coordinates
[18]. By using the proposed method, a simple control structure
of DTC as introduced in [1] can be retained. The
implementation technique is verified experimentally.
II. DIRECT TORQUE CONTROL DRIVES
Fig. 1 represents the scheme of a DTC drive. The
estimated flux magnitude and torque are compared with their
references values. Torque and flux comparators consisted of
three and two-level hysteresis comparators respectively. The
sector judgment is used to evaluate the position of the stator
flux vector in DQ coordinates.
The switching table produces the switching status according
to the outputs of torque and flux comparators and the sector
judgment. These switching status are connected to the
inverter, which is connected to the motor. They are also used
as the inputs to torque and flux estimator.
Fig. 1. DTC scheme
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 In order to estimate the stator flux and thee electromagnetic III. PROPOSED METHOD TO IMPROVE
M TORQUE AND FLUX
torque, several variables need to be determiined. Firstly, the ESTIMATOR
stator currents from the motor Ia and Ib, are transformed into The algorithm of torque and flux x estimation is implemented
DQ coordinates, which are used in DTC algorrithm, as follows: in an architecture consisted of six main blocks, as shown in
puts: two 21-bit currents (Ia
Fig. 2. This architecture has six inp
ID = Ia (1) and Ib), 12-bit high voltage DC C-supply (Vdc) and three
switching status Sa, Sb and Sc. Att the end, it produces three
3 outputs: the estimation values of torque (T), flux ( s ) and
IQ = ( I a + 2 Ib ) (2)
3
sector . The sampling time is seet to 5 s, which is limited
At the same time, by using the switching sttatus (Sa, Sb and by the ADC used.
Sc) produced by the switching table, the statoor voltages in DQ
components are determined:

Vdc
VD = ( 2 S a Sb S c ) (3)
3
3
VQ = Vdc ( Sb Sc ) (4)
3
Then, using the calculated Id, Iq, Vd and Vq, the estimation Fig. 2 Block Diagram of torquee and flux estimators
of the stator flux in DQ coordinates are perforrmed as follows:
A. Torque and Flux Estimator Arch
hitecture
D = D + ( VD RS I D )Ts All the equations which modelled the motor behavior are
old (5)
implemented in a two-stage-piipelined architecture, as
Q = Q + ( VQ RS I Q )Ts presented in Fig. 3. Several maathematical operations are
old (6)
performed in parallel. At the first stage, stator currents and
voltages in DQ-coordinates are calculated in parallel so that
Finally, equation (7) calculates flux magnnitude by using a
those results can be used to estimatee the stator flux in the same
square root calculation, whereas the electrom
magnetic torque is
stage. The resulted currents and flux are used to determine the
estimated in equation (8).
flux magnitude and the torque estim mation in the second stage.
A 62-bit non-restoring square root is implemented in order to
s = D2 + Q2 (7) compute the flux magnitude.
3 As a matter of fact, [13] proposedd that three-stage-pipelined
T= P( I Q D I DQ ) architecture should be implemen nted in this module, by
4 (8) separating the computation of staator currents and voltages
from the estimation of the stator flux. However, the former
can be considered as an immediate calculation and thus, those

Fig. 3. The architecture of torque and flux estimators

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calculations can be merged into one singgle stage. As a case, Ts = 0.00000476837 s (0.0 000000000000000001010)2.
consequence, the latency of the estimator is reduced from 15 However, 27-bit representation iss chose to have a better
s to 10 s. precision and thus, Ts = 0.00000499934 s
(0.000000000000000001010011111 1)2.
Fig. 4 shows the estimated torqu ue taken during the steady
B. The Digital Properties
state. From this figure, it can be seen that the torque estimation
To achieve a good implementation, several digital for 21-bit Ts is imprecise, when compared to
properties need to be considered when designing this MATLAB/Simulink double precisio on estimation, which is the
estimator. Adopted binary format, quantizatioon and sampling ideal case. In fact, the number of bits
b is increasing after each
time are among those key factors. operation in order to avoid calculaation errors or imprecision.
1). Binary format representation This will result in the rising off the hardware area used.
In this implementation, twos complem ment fixed-point Therefore, truncation process must m be performed avoid
representation is used in all operations, exceppt for the square excessive increase of the number off bits used
root calculation. In this particular case, unsiigned fixed-point
representation is applied, since its operand annd its results are
always positive. The major advantage oof using twos
complement fixed-point representation for reaal numbers is that
it adheres to the same basic arithmetic princiiples as integers.
The representation makes the system bboth simpler to
implement and capable of easily handling higher precision
arithmetic that does not require examining the signs of the
operands to determine whether to add or subtrract [14, 19].
Recent DTC implementation as in [5, 166] generally used
32-bit format where some bits might be left uunused, while 16-
bit format is not appropriate to achieeve good DTC
implementation [13, 16]. Therefore, varriable word-size Fig. 4. The torque estimation during steady state. (A) Estimated torque for
approach [13] is adopted for this implementtation and so, all Matlab double precision; (B) Estimated torque
t for Ts in 27 bits; (C)
the redundant bits can be eliminated by trunccating process to Estimated torque for Ts in 21 bits.
minimize the hardware resources usage. In aadditional, in this
implementation, extended word-size more thhan 32-bit for the
magnitude of flux and square root operation iss used.
2). Quantization
The determination of word size is one of thhe critical parts in
FPGA implementation. On one hand, insuffi ficient number of
bits used may reduce the precision or causee the calculation
error, which can unstabilize the whole systeem. On the other Fig. 5. The example of Iq calculation
hand, larger words used may increase the harrdware area used
for the implementation. In the example of Iq calculation, as
a shown in Fig. 5, when Ib
Since twos complement fixed-point formaat is used for the is multiplied by 2, the result shouldd be in 6.16 bits (6 integer
implementation, at least 2 things that needd to be verified. bits plus 16 fractional bits). Neverttheless, it is stored in 7.16
Firstly, the size of the integer must be prooperly chosen to bits to avoid overflow which may m happened during the
avoid the problem of overflow. Secondly, thhe number of the addition operation. Next, when the addition
a result is multiplied
fractional bits used must be sufficient in orderr to minimize the
calculation error. For example, due to the faact that the input
by 31 3 , which is coded in 1.18 biits, Iq should be represented
currents Ia and Ib are varied from -10A to 100A, at least 5 bits in 8.34 bits, but it is truncated to 6.1
16 bits.
are necessary for the integer bits. While 16 fraactional bits used 3). Sampling time
can result in a very good precision, since thee step change per
The sampling time Ts is limited to 5 s by the ADC used.
bit is very small (15 A). Therefore all the operations invo olved in this model were
One of the critical parts in this architecture is the stator flux performed within this sampling timee.
estimation, where the integration is performedd. This operation It should be noted that the use of high
h sampling frequency is
can easily produce errors if the sampling time Ts is not important in DTC implementatiion, for the purpose of
properly scaled; in this case, Ts = 5 s = 0.0000005 s. In fact, minimizing the torque ripple. The sampling time used for DSP
21 bits are necessary at the minimum to reprresent Ts. In this implementation is normally much larger than Ts, which is not

124
less than 50 s. Therefore, it is reduced by a factor of 10 for square root of quadrature flux maagnitude. To calculate the
this FPGA implementation and thus, lower torque ripple is stator flux ( s ), the non-restoring
g square root algorithm as
produced, as shown in Fig. 6.
proposed in [22] is modified as below (D=radicand,
q=quotient and r=remainder):

r0 = 1 ( n 2 + 2bits )
q0 = 0 ( n 2 + 1bits )
For i=0 to n-1 do:
If ri 0 then
ri + 1 = (4 ri + D( n 2 i ) 1 D( n 2 i ) 2 ) ( 4 qi + 1 )
else

Fig. 6. The effect sampling time to torque rripple ri + 1 = (4 ri + D( n 2i ) 1 D( n 2 i ) 2 ) + ( 4 qi + 3 )

(A) Estimated torque for Ts=5s; (B) Estimated torquue for Ts=50s.
If ri + 1 0
C. Backward Euler Approach qi + 1 = 2qi + 1
The discrete backward Euler formula is else
y( n ) = y( n 1 ) + k .T .u( n ) . It is simpler for qi +1 = 2qi
implementation in FPGA hardware than the foorward Euler and
Trapezoidal method that required the regisster to store the
The final result of the square root is equal to qn( n 2 -1 down to
previous value of u( n 1 ) function. The backward Euler n
0), coded in 2 bits.
integration method is also capable of maintaaining the system
stability in the large step size. Thereforre, the discrete
backward Euler integration method is chosenn to calculate the F. New Sector Identification
quadrature flux ( D and Q ). The present work has created a simpler method to judge the
sectors of voltage vector based on comparison between

D. LP Filter Q , 3 D , 3 D and 0 refer to Table 1, which is modified

In the stator flux estimator ((5) and (6)), Rs is the estimated from [23]. With the comparison, it is simpler to determine the
stator resistance, while Ts is the implemenntation sampling sector of voltage vector compared d to conventional method
time. These equations correspond to the iintegration using through arc tan of angle, three staages comparison based on
Backward Euler Method. In [20-21], it was shhown that a filter D ,Q or determination of angle using CORDIC algorithm
should be added to the integrator inn the practical
[15].
implementation to avoid integration drift prooblem due to DC
offset present in the sensed currents. Thus, equation (5) and Table 1. The proposed simpler ideentification of the sectors
(6) become:
Sector Vector
Angle
Q > 0 Q > Q > 3 D
D = ( D + ( VD RS I D )Ts )( 1 c Ts ) (9)
old 3 D
Q = ( Q + ( VQ RS I Q )Ts )( 1 c Ts )
old
(10) I (00, 600) 1 0 1
II (600, 1200) 1 1 1
III (1200, 1800) 1 1 0
Choosing an appropriate cut-off frequency for the LP Filter IV (1800, 2400) 0 1 0
is very important to optimize steady state ooperation, which V (2400, 3000) 0 0 0
depends on the operating frequency. By ssetting a cut-off VI (3000, 3600) 0 0 1
1: satisfy, 0: not satisfy
frequency closer to the operating frequency, the dc offset in
the estimated stator flux can be reduced. H However, it will The proposed method is a single staage with three comparisons
introduce phase and magnitude errors. Thee introduction of performed in parallel without calcuulation of angle; so it is a
these errors will not be discussed in this paperr. fast computation and hence incorreect voltage vector selection
can be reduced.
E. Non-restoring Square Root Algorithm II. EXPERIMEN
NT SETUP
The stator flux ( s ) in DTC drive is calcculated from the The validation of designed torquee and flux comparators was

125
performed based on Hardware-in-the-Loop (H HIL) method. The EP20K200EFC484-2x, and used 2093 logic elements for the
DTC model in MATLAB/Simulink was sim mulated and then, implementation. The tests were performed when the motor
the same data Ia, Ib, Sa, Sb, and Sc used for thee simulation were was operated in steady state condition, and the results were
copied from MATLAB workspace to VHD DL codes, as the observed on the oscilloscope. For validation purposes, the
inputs for the targeted FPGA. The VHD DL codes were results were compared with the MATLAB/Simulink
simulated in ModelSim-Altera before being synthesized and simulation results. Fig. 8 presents the
t input test, while Fig. 9
implemented in FPGA. The test design flow w is presented in and Fig. 10 shows the comparisons between
Fig. 7. MATLAB/Simulink simulations an nd the experimental results.
The results show that experimentaal results are in agreement
with the simulation in Simulink, where it is conducted in
double-precision computation.

(a)

(b)

Fig. 7. Top-down test design flow (c)

In the implementation of DTC based on F FPGA, there are

many digital properties that need to be connsidered, such as
binary format representation (data typee), quantization,
sampling time and word length (size). Inn fact, error or
(d)
inaccuracies due to these digital problems cann seriously affect
the estimation. For example, the torque ripplee can be reduced nts Ia & Ib; (b) Sa; (c) Sb; (d) Sc.
Fig. 8. The inputs test. (a) the stator curren
from 2N-m to 0.2N-m corresponding to a chaange in sampling
time from 50s to 5s, as shown Fig. 6. In this paper, these
digital properties have been considered in the implementation.
It is shown in that the calculation of torquee and flux are can
be performed with high precision and smalll sampling time.
The new architecture utilized the backward Euler approach,
LP Filter-based estimator, modified non-restooring square root
algorithm and new sector identification, which are the
essential elements of high performance DT TC motor drives.
Furthermore, the design is simple and flexible and the VHDL
source code can be easily modified. Foor example, the
truncation process can be adjusted to avoid exxcessive increase
in the hardware resource of FPGA, but its accuracy is still
sufficient. Fig. 9. The comparison between MATL LAB/Simulink simulation and
experimental result for torrque estimation.

III. RESULTS AND DISCUSSION

N
The experiments were conducted on Altera APEX

126

Fig. 10 The comparison between MATLAB/Simulink simulation and the
experimental result for flux locus.
IV. CONCLUSION
FPGA is suitable for high-performance DTC
implementation owing to its high speed processing. The
sampling time for the stator flux and torque estimation is
extremely small, which cannot be obtained using DSP or fast
microcontroller. The choice of word sizes, the binary format
and the sampling time used are very important in order to
achieve good implementation of the estimators. To get simpler
implementation and fast computation, the backward Euler
approach to calculate the discrete integration operation of
stator flux, the modified non-restoring method to calculate
complicated square root operation of stator flux and a new
sector judgment method were introduced. The design, which
was coded in synthesizable VHDL for the implementation on
Altera APEX20K200EFC484-2x device has produced very
precise estimations with minimal error and was verified with
MATLAB/Simulink double-precision simulation.
ACKNOWLEDGMENT
The authors would like to thank Universiti Teknologi
Malaysia for providing the funding for the research.
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