Design of Request Completion Handler For PCI Express

IDL - International Digital Library Of
Technology & Research

Volume 1, Issue 2, Mar 2017 Available at: www.dbpublications.org
International e-Journal For Technology And Research-2017
Design of Request Completion Handler for PCI

Express
Niranjan Mamadapur1, Shriram P Hegde2
Department of Electronics and Communication Engineering
1
SDM Institute Of Technology
2
SDM Institute Of Technology
Ujire, India
Abstract: PCI Express is the third generation high receives the requests from the master. Perform the
performance I/O bus used to interconnect peripheral completions [3] for non-posted requests and send them
devices in applications such as computing and back to the master.
communication platforms. The first generation buses
include the ISA, EISA, VESA, and Micro Channel PCI Express
buses, while the second generation buses include PCI,
AGP, and PCI-X. PCI Express is an all-encompassing PCI Express [1] is the third generation high
I/O device interconnect bus that has applications in the performance I/O bus used to interconnect peripheral
mobile, desktop, workstation, server, embedded devices in applications such as computing and
computing and communication platforms. Request communication platforms. The first generation buses
completion handler is the interface operates in include the ISA, EISA, VESA, and Micro Channel
between the PCIe master and the PCIe client. It buses, while the second generation buses include PCI,
performs the data transactions between the PCIe AGP, and PCI-X. PCI Express [4] is an all-
master and PCIe client. Requests are sent to the client encompassing I/O device interconnect bus that has
through request completion handler and completions applications in the mobile, desktop, workstation,
are sent back to the master through the request server, embedded computing and communication
completion handler. Request completion handler platforms. The PCI Express specification defines a
performs the completions for non-posted requests as layered architecture for device design as shown in
well as posted requests. The scope of this work figure. The layers [8] consist of a Transaction Layer
involves designing the request completion handler for [6], a Data Link Layer [2] and a Physical layer [9].
PCIe, develop coding for simulation and test it. The layers can be further divided vertically into two, a
Keywords: PCI Express, ISA, EISA, VESA transmit portion that processes outbound traffic [13]
and a receive portion that processes inbound traffic.
However, a device design does not have to implement
1. INTRODUCTION a layered architecture as long as the functionality
required by the speciation [12] is supported.
The PCIe slave interface [11] is the communication
interface which operates in between the PCIe master
and the slave or client. It provides the necessary
interface to perform the following operations. Sends
the requests from the master, both posted and non-
posted requests are sent to the client or slave. Performs
the completions of non-posted requests sent by the
master.
PCIe Master: PCIe master or the host is the one which

initiates the transaction. PCIe Slave: PCIe slave
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Byte Ordering At Endpoints PCIe System
The header [15] contains 3 or 4 Data Words. Important PCIe system [17] is shown in the figure below.
fields are part of the first Data Word. The Fmt field Request completion handler is the interface which
gives information about how long is the header and operates in between the PCIe master and the PCIe
whether data payload is present. The Type field client. It provides the necessary interface to perform
defines the TLP operation. R fields are the reserved the data transactions between the PCIe master [5] and
fields. The TD field gives information about whether PCIe client. Requests are sent to the client through
there is an extra CRC on the TLP data. The Length request completion handler and completions [16] are
field defines the length of the data. The Requestor ID sent back to the master through the request completion
gives information about the sender of the handler.
packet[14].The First Word BE field (1st Double-
Word Byte Enable) allows to choose which of the four
bytes in the first Data Word are valid and should be
written. The Last Word BE field must be zero when
Length is unity, since the first Data Word and the last
is the same one. Address field is the address to which
the first Data Word is written. It is shown in the Figure
below.


PCIe Controller completion handler performs the completions for the
non-posted requests. The attribute FIFO holds the
PCIe controller is located at the endpoints [10] of PCI attributes, data FIFO holds the data, header FIFO
express system. PCI hard macro implements the three holds the header information and completion FIFO
layers of the PCI Express namely transaction layer [6], holds the completion data.
data link layer and physical layer. PCI Tx
(Transmitter) Rx (Receiver) processor initiates the
transactions [11]. PCIe request handler provides the
necessary interface [7] for the transaction between the
master and the slave. PCIe request completion handler
sends the requests from the master to the client and
send the completions from the client to the master.
Requests are two types posted requests and non-posted
requests. Posted requests are the one which does not
need an acknowledgement where as non-posted
requests are the one which need an acknowledgement.
Example of the posted request is the memory write
operation. In this case the master sends the address as
well as the data along with the write request. There is
no need of acknowledgement or the completion from
the client. Example of non-posted request is the
memory read operation. In this case the master sends
read request along with the address from which it has
to be read. The client has to send an acknowledgement
or the completion which is nothing but the read data.
These request and completion operations are
performed by the PCIe request completion handler. 2. OBJECTIVES
PCIe controller is shown in the Figure below
To design the slave request handler.
To design the slave completion handler.
To design the attribute FIFO, data FIFO,
header FIFO and completion FIFO.
To design the client (slave) which in this case
is memory.
Develop the code for all the blocks using
Verilog HDL.
Integrate all the blocks.
Perform the synthesis using ISE simulator.
Simulate the design.
Test all the operations of the request
completion handler.
Request Completion Handler 3. OPERATION OF REQUEST

Request completion handler operates in between the COMPLETION HANDLER
PCIe [5] Tx-Rx processor and the client. The block
diagram of the request completion handler is shown in
the Figure below. The requests are sent to the client The operation of request completion handler is to send
through the request completion handler and both posted and non-posted requests to the client and


send back the completions or the acknowledgements - Get the data which is read from the client for non-
to the master depending upon whether the request posted requests and shift it according to the FWBE
made is posted or non-posted request. The request signal.
completion handler gets the inputs from the byte - Get the header information from the header FIFO,
ordering of the PCIe endpoint. The inputs given to the -Form the quad words. Quad word 1 which is nothing
PCIe slave are the but the header, quad word 2 holds the header plus the
1) Attributes shifted data and quad word 3 holds the data.
2) Header Information - Slave completion handler selects the quad words
3) Data according to the status of header FIFO, completion
Attribute information consists of the following. FIFO, the error signals and sends them to the slave
1) Address. completion FIFO
2) Length in bytes. - It also performs the EOD operation.
3) Base address registers being hit.
4) Whether the request being made is to the memory
space or IO.
5) Whether the request being made is a read request or 4. SIMULATION RESULTS
the write request.
Header information consists of the following.
The simulation result of the request handler is shown
1) Tag.
in the Figures below.
2) Traffic class which assigns the speed priority to the
packet to travel through the PCIe fabric.
3) Length of the transaction.
4) Byte count.
5) Requestor ID.
6) First Word Byte Enable FWBE.
7) Lower Address LWADDR.
Data information consists of the following.
1) Data to be written.
2) Byte enable.
3) Information about the end of data EOD.
4) Forwarded error.
A. Operation of Slave Request Handler

Operations of slave request handler is as following.
-To receive the attribute, header and data information
from the end point block byte ordering.
-Shift the data according to the FWBE and LWBE by
using data shifting logic so that only valid bytes are
sent to the client.
-Checks the end of data.
-Performs the error check logic.
-Sends the appropriate information to the appropriate
FIFO so as to store them for further processing.
Attributes are sent to the attribute FIFO, data is sent to
the data FIFO and header information is sent to the
header FIFO.
B. Operation of Slave Completion Handler

Operation of the slave completion handler is as
following.

The simulation result of the completion handler is

shown in the Figures below.
The simulation results of the top module is shown in

the Figures below


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[14] Xilinx, Logic Core IP End Point Block Plus v1.12
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[15] Xilinx, Logic Core IP End Point Block Plus v1.9
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International e-Journal For Technology And Research-2017