Reg. No.

136 S 74
FOUR YEAR B.TECH. DEGREE EXAMINATION * APRIL, 2016.

SIXTH SEMESTER EXAMINATION

ELECTRICAL AND ELECTRONICS ENGINEERING

INTEGRATED CIRCUITS AND APPLICATIONS (ICA)

(scHEME - 2013)

Time: 3 Hours Max. Marks :'70

Note : Question N?. is compulsory and. it must be answered first

1
in sequence at one place only.

Answer any FOUR from the remaining.

Question No. 1 carries 10 marks and remaining questions carry 15 marks each.

1. Answer the following: (1 x 10 = 10)

(a) List the methods used to provide the external frequency compensation.
(b) Define slew rate. What causes it?
(c) What are the basic requirements of a good. instrumentation amplifier?
(d) Draw the circuit of I to V converter using Op-Amp.
(e) Enlist the important features of 555 tim6r circuit.
(f) What is meant by capture range in a PLL?
G) What is the need for voltage regulation?
(h) Why d.o switching regulators have better effi.ciency than the series
regulators?
(i) What is meant by resolution of ADC?
0) Why.must CMOS devices be handled with care?

2. (a) Explain the following terms in an Op-Amp : (8)

(i) Basic current

' (iil Thermal drift
(ii, Inputoffset-voltage
(iv) Stability of Op-Amp
(b) Explain the frequency compensation techniques of Op-Amp. (7)
Iurn Over
3. (a) Explain the operation of Schmitt trigger with neat diagram. (7)

(b) Write a note on V/I and IA/ converters with diagrams. (8)

4. (a) With block diagram explain the principle of operation of IC 565 phased
Iocked loop. (7)

(b) Design and draw the waveforms of 1 kHz square wave form generator
using 555 Timer for duty cycle D = 25o/o and D = 50o/o. (8)

b. (a) Draw and explain the functional block diagram of a T}Svoltage regulator
. how its IC can be used. as high voltage regulator. (8)

(b) Expiain the rvorking of fixed voltage regulator with neat diagram. (7>

6. (a) Explain the operation of Dual-slope ADC. (5)

(b) With neat diagram, explain the working principle of

(i) R-zR ladder type DAC. (5)

(ii) Weighted resistor DAC (5)

7. (a) Expiain the operation of TTL logic family in detail' (5)

(b) Make a comparison of different logic families according to their

specifi.cations. (10)

136 S 74