A 93.

7% Peak Efficiency DC-DC Buck Converter

with All-Pass Network Based Passive Level Shifter
in 55 nm CMOS
Xiucheng Hao, Fan Yang, Mingxiao He, Yongan Zheng, Ying Guo, and Huailin Liao*
Laboratory of Microelectronic Devices and Circuits (MOE),
Institute of Microelectronics, Peking University, Beijing 100871, China
E-mail: liaohl@pku.edu.cn

AbstractThis paper proposes a DC-DC buck converter with

all-pass network based passive level shifter in 55nm standard
CMOS process, for battery powered portable applications. In
order to handle high battery voltages in this advanced standard
CMOS process, a passive level shifter based on all-pass network is
applied for gate oxide protection. Drain extension is proposed to
obtain high breakdown voltage of active region. The proposed
buck converter with the passive level shifter works in DCM
operation as its load current varies from 0.1-10mA. The buck
converter achieves a peak efficiency of 93.7% and 83.8% at 10mA
load current, with a supply voltage of 1.8V and 3.7V, respectively.

KeywordsCMOS DC-DC buck converter, passive level shifter,

battery powered, portable applications, high peak efficiency, all-pass
network. Fig. 1. (a) Multiple-voltage scheme. (b) Capacitor scheme.

I. INTRODUCTION
Recently, the demand for consumer electronics products
including battery powered portable applications increases
rapidly, and power management integrated circuits (ICs), such
as high switch efficiency DC-DC converters, are becoming
critical building blocks in these products. The cost of the whole
chip is proportioned to its area. Reducing the area of the chip
and integrating more devices in a certain area becomes two of
the most important targets in consumer electronics IC design.
In advanced deep submicron standard CMOS process, such
as 65nm node or 45nm node, the rated operating voltage of core Fig. 2 (a) Basic all-pass network structure. (b) The proposed passive level
shifter.
devices is approximate 1.2V. However, common lithium or
alkaline batteries with a rated voltage range of about 1.5 to 3.7V, (SC) DC-DC converters and level shifters are recommended to
will exceed the voltage upper limit of core devices in the provide multiple voltages [1]. The other method is based on a
advanced process. Therefore, a DC-DC converter is usually capacitor connected to the gate of the transistor which is used to
realized by IO devices whose rated operating voltage is much increase its effective gate oxide thickness as shown in Fig. 1(b),
higher to bear high power supply voltage. As a matter of fact, and two-capacitor scheme is also proposed (use both C1 and C2)
the area of power transistors takes a high proportion of a DC-DC [2], [3]. As for active region protection, multiple stacked power
converter chip. Utilizing IO devices dramatically increases both transistors are required [1], [4]. Drain region extension is a
the area and the cost of the whole chip, because IO devices standard CMOS process compatible option to protect the power
require longer minimum channel length, larger area of active transistors from breakdown [1], [5]-[7]. However, utilizing
region and lower trans-conductance (gm) in a certain fabrication multiple internal voltages produced by an additional SC DC-DC
process. In order to reduce the cost of the chip, it is significant converter or a level shifter increases the complexity of the DC-
to utilize core devices to implement a DC-DC converter. DC converter and causes extra conversion efficiency loss. A
capacitor connected to the gate of a transistor makes the gate
To handle high supply voltage, some existing methods are floating and the method is only suitable for constant input
published [1]-[3]. As Fig. 1 shows, for gate oxide protection, voltage [2], [3]. Serious second-order effect and extremely thin
internal voltage conversion blocks, such as switched-capacitor gate oxide of the transistor in advanced deep submicron standard
CMOS process may cause serious leakage, which reduces the
power conversion efficiency of the DC-DC converter. Stacked
This work was supported in part by the Beijing Natural Science
Foundation under Grant 4151002 and in part by National Natural Science
Foundation under Grant 61574008.

978-1-4799-5341-7/16/$31.00 2016 IEEE 445

transistors may also cause leakage and increase design
complexity [1].
In this paper, a DC-DC buck converter with all-pass network
based passive level shifter is proposed. The buck converter is
simply composed of power transistors with the passive level
shifter, a voltage feedback block, a zero current detector and
buffers, so that it is able to achieve a high conversion efficiency.
The proposed all-pass network based high voltage tolerant
structure provides the core devices with gate oxide protection,
and avoids the serious leakage current of devices, meanwhile.
The drain region extension scheme simplifies the structure of the
converter and increases the voltage upper limit of active region.
As a result, it gives us possibility to implement a high-voltage-
tolerant DC-DC converter with high conversion efficiency and
low chip area cost in advanced deep submicron standard CMOS
process. Fig. 3 A high voltage tolerant inverter realized by the proposed structure
with its key waveforms.
This paper is organized as follows. Section II describes the
proposed structure of the passive level shifter. A DC-DC buck carefully to make Equation (2) approach equality to set up a
converter demonstration for the proposed high voltage tolerant certain DC voltage on the gate. In this condition, as the red path
structure in Section III. Section IV shows the simulation results. shows, the unbalanced current compensates for the effect of gate
Finally, conclusion is given in Section V. leakage current and a certain DC voltage can be guaranteed.
In Fig. 3, a high-voltage-tolerant inverter implemented by
II. PROPOSED PASSIVE LEVEL SHIFTER
the proposed structure is shown for demonstration. The input is
A. Gate Oxide Protection Based on All-pass Network an ideal pulse signal with voltage range from 0 to VBAT and VBAT
Fig. 2(a) shows the structure of a basic all-pass network, is higher than the voltage upper limit of the core devices. After
which is actually composed of two resistors and two capacitors. selecting proper values of passive devices, as the waveform
In ideal condition, the transfer function from node VIN to node shows in Fig. 3 for example, the range of VGP and VGN
VX, Y can be expressed as: approaches VBAT/2 to VBAT and 0 to VBAT/2, respectively. As a
result, the maximum voltage between gate and bulk of a
transistor can be limited so that the gate oxide is well protected.
, 1+ Whats more, the all-pass network can also alleviate the effect
= . (1)
of leakage current of the transistors.
+
1+ 1+
B. CMOS Process Compatible Drain Extended LDMOS
If proper values of R1, R2, C1 and C2 are selected, the equation
Fig. 4 provides the implementation of the proposed drain
mentioned below will be satisfied
extended LDMOS. Core devices with thin gate oxide in a
= (2) certain fabrication process can obtain high S/D breakdown
voltage by drain region extension. In our former work [5], [6],
Equation (1) can be simplified as equation (3)
the LDMOS transistor is implemented with standard CMOS
technology by introducing STI oxide in the drift region and has
, 1+ obtained high breakdown voltage. The drain region of both
= = . (3)
+ + NMOS and PMOS can be extended [7], as simply shown in
1+ 1+
Equation (3) shows that VX, Y follows VIN and a certain DC
voltage can be set up at node VX, Y. When the values of all passive
devices satisfy Equation (2), there is no current between node X
and node Y, and the network achieves a balanced state.
Power transistors often occupy large area, as a consequence,
leakage current of the transistors, e.g., the gate tunneling current,
punch through current and subthreshold leakage current, and are
becoming a severe phenomenon in an advanced deep submicron
standard CMOS process. Therefore, the basic all-pass network
should be modified with one more current source as Fig. 2(a)
shows. Then Fig. 2(b) shows the practical situation of the gate
oxide protection scheme. A power transistor with large gate area
replaces the capacitor C2 in Fig. 2(a), and its bulk connects to the
source and ground. Considering gate leakage current which can Fig. 4 Implementation of the proposed drain extended LDMOS.
be truly detected, values of RN1, RN2 and CN1 need to be selected

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 Fig. 5. The proposed DC-DC buck converter.
Fig. 4, and P-well can be fabricated by utilizing DNW process
properly.
The width of STI oxide is determined by the applied voltage
of the batteries mentioned above is usually several volts, so the
width of the STI oxide region will not be too large. With critical
dimension of devices scaling down, drain extended LDMOS
maintains an effective method for obtaining a high breakdown
voltage in standard CMOS process. It is also an effective
method to save the area and reduce the complexity of circuits
for power applications.
III. DC-DC BUCK CONVERTER DEMONSTRATION
Fig. 5 shows the structure of the DC-DC buck converter
demonstration which is implemented in a standard 55nm CMOS
process.
A. Circuits Level Implementation
As Fig. 5 shows, the buck converter is composed of an all-
pass network based passive level shifter, a voltage feedback
block, a zero current detector and buffers. As the load current
varies from 0.1mA to 10mA, the converter is operating in light
load condition, and the inductor current becomes negative for a
certain period, which causes a significant power conversion
efficiency loss [8]. In order to reduce the inductor size while
maintaining high conversion efficiency, the discontinuous
Fig. 6 Key waveform of inductor current and time sequence in DCM
operation.
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conduction mode (DCM) operation is necessary. Fig. 6 gives
the key time sequence waveform.
The zero current detector simply consists of a conventional
PMOS input comparator and a AND gate [9]. The negative
input of the comparator detects the variation of the voltage at
input end (VX) of the inductor. With careful design of the
comparator, the 10-20ns delay of the comparator provides a
non-overlap sequence, as Fig. 6 shows, so the non-overlap
clock generator can be saved.
The voltage feedback block is composed of a conventional
comparator and a SR latch. The clock signal VCLK can be
provided by the system [10], for which the DC-DC converter
serves in reality. The SR latch samples the VCLK signal so that
the gate control signal of the power transistors VCLKP and VCLKN
can keep self-adaptive when the load current changes. In fact,
the additional clock is optional [11], and the output of the
comparator in voltage feedback module can be supplied to the
PMOS power transistor directly.
B. The Proposed Passive Level Shifter Implementation
The proposed passive level shifter is implemented by
transistors and MOM capacitors as Fig. 5 shows. Diodes or
diode-connected transistors are used to achieve large resistance
in place of the resistors in Fig. 4, and to provide several hundred
nA current to compensate the leakage current of the transistor
gate. The resistors are realized by the PMOS transistor with
1.2V operating voltage in proper size. The capacitors can be
placed above the transistors without extra area cost. The
proposed drain extended LDMOS is replaced by a cascade IO
device (RVTP and HVTP, etc.) highlighted in Fig. 5, because
stack transistors can provide the similar function as mentioned
above, and there is no existing drain extended LDMOS in the
55nm standard CMOS process. However, increasing the
number of stacked transistors for higher breakdown voltage will
decrease the power conversion efficiency of DC-DC converter
[1].The gate of the IO devices needs to be provided with a
proper bias voltage for demonstration.
IV. SIMULATION RESULTS
Fig. 7 gives key node waveforms of the proposed DC-DC
buck converter which works at 3.7V input voltage and 10mA

Fig. 7 Simulated key waveforms of the proposed DC-DC converter.
Fig. 8 Conversion efficiency of the proposed DC-DC converter.
load current. As a result, the buck converter provides a 1.2V
output with dozens of mV ripple. The peak current of the
inductor reaches approximate 80mA in this condition. The
results in Fig. 7 shows the buck converter working in DCM
operation with a nonsynchronous sequence, as mentioned
above, which guarantees a high conversion efficiency in this
load current condition. The period of VCLKP and VCLKN (as shown
in Fig. 5) is determined by the additional clock signal VCLK and
the load condition.
Fig. 8 shows the simulated power conversion efficiency
results. The converter can achieve an 83.7%-93.7% conversion
efficiency with a 1.8V input and 0.1-10mA current load. When
input voltage is increased to 3.7V, the conversion efficiency
reaches 65.3%-83.8%. Table I summarizes the performance of
the proposed buck converter and gives a comparison with state-
of-the-art works.
V. CONCLUSION
In this work, a DC-DC buck converter with all-pass network
based passive level shifter is proposed in 55nm CMOS process.
The buck converter works at load current from 0.1 to 10mA,
with 1.8-3.7V input, 1.2V output and achieves 93.7% peak
efficiency. As a result, it gives us a possibility to realize a high
voltage tolerant DC-DC converter with high conversion
efficiency and low chip area cost in advanced deep submicron
standard CMOS process. With an increase in load current,
utilizing the proposed passive level shifter also provides a
significant benefit of area reduction.
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TABLE I. PERFORMANCE SUMMARY AND COMPARISION TABLE

[1] JSSC 2011 [4] TCASII 2014 [8] JSSC 2014 [10] JSSC 2011 This work

Technology 45nm CMOS 65nm CMOS 40nm CMOS 130nm CMOS 55nm CMOS
Iuput voltage 2.8-4.2V 3.6V 0.6-1.1V 1.8V 1.8-3.7V
Output voltage 0.6-1.2V 1.8V 0.3-0.55V 0.575-1V 1.2V
Ind & Cap L=10uH C=2uF Stacked LC L=220uH - L=22uH C=2uF
87.4% 67.9% 94% 90% 93.7%
Peak efficiency @3.0V input, @3.6V input, @0.6V input, @1.8V input, @1.8V input,
12mA load 140mA load 2mA load 100uA 10mA load
Load Current 10-100 mA 140mA 0.05-10mA < 0.2mA 0.1-10 mA

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