Beruflich Dokumente
Kultur Dokumente
Typical Application
High Efficiency Buck-Boost Converter
VOUT
VIN 12V Efficiency and Power Loss
5V TO 32V + 100F +
22F
50V 4.7F
1F 16V
330F
16V
5A
VOUT = 12V, ILOAD = 5A
CER CER CER
A VIN PGOOD INTVCC D 100 10
TG2 TG1 9
0.1F 0.1F
BOOST2 BOOST1 95
8
SW2 SW1 7
B C 90
POWER LOSS (W)
LTC3780
EFFICIENCY (%)
BG2 BG1 6
ITH PLLIN 85 5
2200pF 105k
RUN ON/OFF 4
SS 1%
20k 0.1F VOSENSE 80
3
SGND FCB 7.5k
2
SENSE+ SENSE PGND 1% 75
1
70 0
0 5 10 15 20 25 30 35
0.010
VIN (V)
3780 TA01b
4.7H
3780 TA01
3780ff
Pin Configuration
TOP VIEW
TOP VIEW
BOOST1
PGOOD
TG1
PGOOD 1 24 BOOST1
NC
NC
NC
NC
SS
SS 2 23 TG1 32 31 30 29 28 27 26 25
5 ITH 3 22 EXTVCC
ITH 20 EXTVCC
VOSENSE 4 21 INTVCC
VOSENSE 6 19 INTVCC 33
SGND 5 20 BG1
SGND 7 18 BG1
RUN 6 19 PGND
RUN 8 17 PGND
FCB 7 18 BG2
FCB 9 16 BG2
PLLFTR 8 17 SW2
PLLFLTR 10 15 SW2
9 10 11 12 13 14 15 16
PLLIN 11 14 TG2
NC
PLLIN
STBYMD
NC
NC
BOOST2
TG2
STBYMD 12 13 BOOST2 NC
G PACKAGE UH PACKAGE
24-LEAD PLASTIC SSOP 32-LEAD (5mm 5mm) PLASTIC QFN
TJMAX = 125C, JA = 130C/W TJMAX = 125C, JA = 34C/W
EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB
3780ff
Electrical
The Characteristics l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25C. (Note 7) VIN = 15V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop
VOSENSE Feedback Reference Voltage ITH = 1.2V, 40C T 85C (Note 3) l 0.792 0.800 0.808 V
55C T 125C l 0.792 0.800 0.811 V
IVOSENSE Feedback Pin Input Current (Note 3) 5 50 nA
VLOADREG Output Voltage Load Regulation (Note 3)
ITH = 1.2V to 0.7V l 0.1 0.5 %
ITH = 1.2V to 1.8V l 0.1 0.5 %
VREF(LINEREG) Reference Voltage Line Regulation VIN = 4V to 30V, ITH = 1.2V (Note 3) 0.002 0.02 %/V
gm(EA) Error Amplifier Transconductance ITH = 1.2V, Sink/Source = 3A (Note 3) 0.32 mS
gm(GBW) Error Amplifier GBW (Note 8) 0.6 MHz
IQ Input DC Supply Current (Note 4)
Normal 2400 A
Standby VRUN = 0V, VSTBYMD > 2V 1500 A
Shutdown Supply Current VRUN = 0V, VSTBYMD = Open 55 70 A
VFCB Forced Continuous Threshold 0.76 0.800 0.84 V
IFCB Forced Continuous Pin Current VFCB = 0.85V 0.30 0.18 0.1 A
VBINHIBIT Burst Inhibit (Constant Frequency) Measured at FCB Pin 5.3 5.5 V
Threshold
UVLO Undervoltage Reset VIN Falling l 3.8 4 V
VOVL Feedback Overvoltage Lockout Measured at VOSENSE Pin 0.84 0.86 0.88 V
ISENSE Sense Pins Total Source Current VSENSE = VSENSE+ = 0V 380 A
VSTBYMD(START) Start-Up Threshold VSTBYMD Rising 0.4 0.7 V
VSTBYMD(KA) Keep-Alive Power-On Threshold VSTBYMD Rising, VRUN = 0V 1.25 V
3780ff
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 6: The minimum on-time condition is specified for an inductor
may cause permanent damage to the device. Exposure to any Absolute peak-to-peak ripple current 40% of IMAX (see minimum on-time
Maximum Rating condition for extended periods may affect device considerations in the Applications Information section).
reliability and lifetime. Note 7: The LTC3780 is tested under pulsed load conditions such that TJ
Note 2: TJ for the QFN package is calculated from the temperature TA and TA. The LTC3780E is guaranteed to meet specifications from 0C to 85C
power dissipation PD according to the following formula: junction temperature. Specifications over the 40C to 85C operating
TJ = TA + (PD 34C/W) junction temperature range are assured by design, characterization and
Note 3: The IC is tested in a feedback loop that servos VITH to a specified correlation with statistical process controls. The LTC3780I is guaranteed
voltage and measures the resultant VOSENSE. over the 40C to 125C operating junction temperature range, and
the LTC3780MP is tested and guaranteed over the full 55C to 125C
Note 4: Dynamic supply current is higher due to the gate charge being
operating junction temperature range.
delivered at the switching frequency.
Note 8: This parameter is guaranteed by design.
Note 5: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels. Note 9: fOSC is the running frequency for the application.
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EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
DCM
CCM CCM
70 70 70
DCM
CCM
60 60 60
50 50 50
VIN = 6V VIN = 12V VIN = 18V
VOUT = 12V VOUT = 12V VOUT = 12V
40 40 40
0.01 0.1 1 10 0.01 0.1 1 10 0.01 0.1 1 10
ILOAD (A) ILOAD (A) ILOAD (A)
3780 G01 3780 G02 3780 G03
Supply Current vs Input Voltage Internal 6V LDO Line Regulation EXTVCC Voltage Drop
2500 6.5 120
VFCB = 0V
2000 6.0 100
STANDBY 5.5 80
1500
5.0 60
1000
4.5 40
500
4.0 20
SHUTDOWN
0 3.5 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 0 10 20 30 40 50
INPUT VOLTAGE (V) INPUT VOLTAGE (V) CURRENT (mA)
3780 G04 3780 G05 3780 G06
5.95 4 0.1
NORMALIZED VOUT (%)
5.90
5.85 3 0.2
VIN = 12V
5.80
5.75 2 0.3
5.70 VIN = 6V
5.65 EXTVCC SWITCHOVER THRESHOLD 1 0.4
5.60 FCB = 0V
VOUT = 12V
5.55 0 0.5
75 50 25 0 25 50 75 100 125 75 50 25 0 25 50 75 100 125 0 1 2 3 4 5
TEMPERATURE (C) TEMPERATURE (C) LOAD CURRENT (A)
3780 G07 3780 G08 3780 G09
3780ff
SW1 SW1
10V/DIV 10V/DIV SW1
10V/DIV
VOUT
100mV/DIV VOUT VOUT
100mV/DIV 100mV/DIV
IL IL IL
2A/DIV 2A/DIV 2A/DIV
3780 G10
VIN = 6V 5s/DIV VIN = 12V 5s/DIV 3780 G11
VIN = 18V 5s/DIV 3780 G12
3780 G14
VIN = 6V 25s/DIV 3780 G13 VIN = 12V 10s/DIV VIN = 18V 2.5s/DIV 3780 G15
VOUT VOUT
VOUT
100mV/DIV 100mV/DIV
100mV/DIV
IL IL IL
1A/DIV 2A/DIV 1A/DIV
3780ff
ISENSE+ (mV)
250
VPLLFLTR = 0V 3.6
200
150 3.4 60
100
3.2
50
0 3.0 80
75 50 25 0 25 50 75 100 125 75 50 25 0 25 50 75 100 125 100 80 60 40 20 0
TEMPERATURE (C) TEMPERATURE (C) DUTY FACTOR (%)
3780 G19 3780 G20 3780 G21
ISNESE+ (mV)
50
140
0
120
50
120
100 BUCK
150 BOOST
50 160
100 BUCK
ISENSE+ (mV)
ISENSE+ (mV)
ISENSE+ (mV)
0 120
50
50 80
0
50 100 40
100 150 0
0 0.4 0.8 1.2 1.6 1.8 2.4 0 0.4 0.8 1.2 1.6 2.0 2.4 0 0.2 0.4 0.6 0.8
VITH (V) VITH (V) VOSENSE (V)
3780 G32
3780 G25 3780 G26
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IL
IL IL 5A/DIV
5A/DIV 5A/DIV
VIN
10V/DIV VIN
10V/DIV
VOUT
500mV/DIV VOUT
500mV/DIV
IL IL
1A/DIV 1A/DIV
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PGOOD (Pin 1/Pin 30): Open-Drain Logic Output. PGOOD operation. When the pin is tied to INTVCC, the constant
is pulled to ground when the output voltage is not within frequency discontinuous current mode is active in buck
7.5% of the regulation point. or boost operation.
SS (Pin 2/Pin 31): Soft-start reduces the input power PLLFLTR (Pin 10/Pin 8): The phase-locked loops
sources surge currents by gradually increasing the lowpass filter is tied to this pin. Alternatively, this pin can
controllers current limit. A minimum value of 6.8nF is be driven with an AC or DC voltage source to vary the
recommended on this pin. frequency of the internal oscillator.
SENSE+ (Pin 3/Pin 1): The (+) Input to the Current Sense PLLIN (Pin 11/Pin 10): External Synchronization Input to
and Reverse Current Detect Comparators. The ITH pin volt- Phase Detector. This pin is internally terminated to SGND
age and built-in offsets between SENSE and SENSE+ pins, with 50k. The phase-locked loop will force the rising
in conjunction with RSENSE, set the current trip threshold. bottom gate signal of the controller to be synchronized
with the rising edge of the PLLIN signal.
SENSE (Pin 4/Pin 2): The () Input to the Current Sense
and Reverse Current Detect Comparators. STBYMD (Pin 12/Pin 11): LDO Control Pin. Determines
whether the internal LDO remains active when the control-
ITH (Pin 5/Pin 3): Current Control Threshold and Error
ler is shut down. See Operation section for details. If the
Amplifier Compensation Point. The current comparator
STBYMD pin is pulled to ground, the SS pin is internally
threshold increases with this control voltage. The voltage
pulled to ground, preventing start-up and thereby provid-
ranges from 0V to 2.4V.
ing a single control pin for turning off the controller. To
VOSENSE (Pin 6/Pin 4): Error Amplifier Feedback Input. keep the LDO active when RUN is low, for example to
This pin connects the error amplifier input to an external power a wake up circuit which controls the state of the
resistor divider from VOUT. RUN pin, bypass STBYMD to signal ground with a 0.1F
SGND (Pin 7/Pin 5, Exposed Pad Pin 33): Signal Ground. All capacitor, or use a resistor divider from VIN to keep the
small-signal components and compensation components pin within 2V to 5V.
should connect to this ground, which should be connected BOOST2, BOOST1 (Pins 13, 24/Pins 14, 27): Boosted
to PGND at a single point. The QFN exposed pad must be Floating Driver Supply. The (+) terminal of the bootstrap
soldered to PCB ground for electrical connection and rated capacitor CA and CB (Figure 11) connects here. The BOOST2
thermal performance. pin swings from a diode voltage below INTVCC up to VIN
RUN (Pin 8/Pin 6): Run Control Input. Forcing the RUN + INTVCC. The BOOST1 pin swings from a diode voltage
pin below 1.5V causes the IC to shut down the switching below INTVCC up to VOUT + INTVCC.
regulator circuitry. There is a 100k resistor between the TG2, TG1 (Pins 14, 23/Pins 15, 26): Top Gate Drive. Drives
RUN pin and SGND in the IC. Do not apply >6V to this pin. the top N-channel MOSFET with a voltage swing equal to
FCB (Pin 9/Pin 7): Forced Continuous Control Input. The INTVCC superimposed on the switch node voltage SW.
voltage applied to this pin sets the operating mode of the SW2, SW1 (Pins 15, 22/Pins 17, 24): Switch Node. The ()
controller. When the applied voltage is less than 0.8V, the terminal of the bootstrap capacitor CA and CB (Figure11)
forced continuous current mode is active. When this pin connects here. The SW2 pin swings from a Schottky diode
is allowed to float, the Burst Mode operation is active in (external) voltage drop below ground up to VIN. The SW1
boost operation and the skip-cycle mode is active in buck pin swings from a Schottky diode (external) voltage drop
below ground up to VOUT.
3780ff
BG2, BG1 (Pins 16, 18/Pins 18, 20): Bottom Gate Drive. EXTVCC (Pin 20/Pin 22): External VCC Input. When EXT-
Drives the gate of the bottom N-channel MOSFET between VCC exceeds 5.7V, an internal switch connects this pin to
ground and INTVCC. INTVCC and shuts down the internal regulator so that the
controller and gate drive power is drawn from EXTVCC. Do
PGND (Pin 17/Pin 19): Power Ground. Connect this pin
not exceed 7V at this pin and ensure that EXTVCC < VIN.
closely to the source of the bottom N-channel MOSFET, the
() terminal of CVCC and the () terminal of CIN (Figure 11). VIN (Pin 21/Pin 23): Main Input Supply. Bypass this pin
to SGND with an RC filter (1, 0.1F).
INTVCC (Pin 19/Pin 21): Internal 6V Regulator Output. The
driver and control circuits are powered from this voltage.
Bypass this pin to ground with a minimum of 4.7F low
ESR tantalum or ceramic capacitor.
3780ff
BOOST2
STBYMD
TG2
FCB FCB
ILIM
+ BUCK
SW2
LOGIC INTVCC
BG2
RSENSE
PGND
IREV
+
BG1
FCB
BOOST INTVCC
SW1
1.2V LOGIC
4(VFB)
TG1
ICMP
+
BOOST1
1.2A OV
SS 0.86V
INTVCC VOUT
+
RUN
SLOPE
EA VOSENSE
100k
VFB
+ 0.80V
ITH
SHDN
RUN/
RST
SS
4(VFB)
SENSE+
SENSE
PLLIN
VREF
PHASE DET FIN
VIN
VIN 50k
5.7V +
PLLFLTR
CLK RLP
6V OSCILLATOR CLP
LDO
EXTVCC REG
0.86V
6V INTVCC
+ + PGOOD
INTERNAL
SGND SUPPLY VOSENSE
+
0.74V
3780 BD
3780ff
The LTC proprietary topology and control architecture em- BG2 B C BG1
ploys a current-sensing resistor in buck or boost modes.
The sensed inductor current is controlled by the voltage RSENSE
on the ITH pin, which is the output of the amplifier EA. The
VOSENSE pin receives the voltage feedback signal, which
3780 F01
is compared to the internal reference voltage by the EA. Figure 1. Simplified Diagram of the Output Switches
The top MOSFET drivers are biased from floating boost- 98%
strap capacitors CA and CB (Figure 11), which are normally DMAX
BOOST
recharged through an external diode when the top MOSFET A ON, B OFF
BOOST REGION
PWM C, D SWITCHES
is turned off. Schottky diodes across the synchronous DMIN
switch D and synchronous switch B are not required, but BOOST
FOUR SWITCH PWM BUCK/BOOST REGION
DMAX
provide a lower drop during the dead time. The addition of BUCK
the Schottky diodes will typically improve peak efficiency D ON, C OFF
PWM A, B SWITCHES
BUCK REGION
by 1% to 2% at 400kHz. 3%
DMIN 3780 F02
BUCK
The main control loop is shut down by pulling the RUN
pin low. When the RUN pin voltage is higher than 1.5V, an Figure 2. Operating Mode vs Duty Cycle
internal 1.2A current source charges soft-start capacitor
CSS at the SS pin. The ITH voltage is then clamped to the
and switch A is turned on for the remainder of the cycle.
SS voltage while CSS is slowly charged during start-up.
switches A and B will alternate, behaving like a typical
This soft-start clamping prevents abrupt current from
synchronous buck regulator. The duty cycle of switch A
being drawn from the input power supply.
increases until the maximum duty cycle of the converter
in buck mode reaches DMAX_BUCK, given by:
Power switch Control
DMAX_BUCK = 100% DBUCK-BOOST
Figure 1 shows a simplified diagram of how the four
power switches are connected to the inductor, VIN, VOUT where DBUCK-BOOST = duty cycle of the buck-boost switch
and GND. Figure 2 shows the regions of operation for the range:
LTC3780 as a function of duty cycle D. The power switches DBUCK-BOOST = (200ns f) 100%
are properly controlled so the transfer between modes is
and f is the operating frequency in Hz.
continuous. When VIN approaches VOUT, the buck-boost
region is reached; the mode-to-mode transition time is Figure 3 shows typical buck mode waveforms. If VIN
typically 200ns. approaches VOUT, the buck-boost region is reached.
SWITCH C CLOCK
HIGH
SWITCH D SWITCH A
0V
IL SWITCH B
IL
CLOCK 3780 F05
When the FCB pin voltage is lower than 0.8V, the controller
Boost Region (VIN < VOUT) behaves as a continuous, PWM current mode synchronous
Switch A is always on and synchronous switch B is always switching regulator. In boost mode, switch A is always on.
off in boost mode. Every cycle, switch C is turned on first. switch C and synchronous switch D are alternately turned
Inductor current is sensed when switch C is turned on. on to maintain the output voltage independent of direction
After the sensed inductor current exceeds the reference of inductor current. Every ten cycles, switch A is forced off
voltage which is proportional to VITH, switch C is turned off for about 300ns to allow boost capacitor CA (Figure 13) to
and synchronous switch D is turned on for the remainder recharge. In buck mode, synchronous switch D is always
3780ff
3780ff
3780ff
350
300 reduce the I2R losses, and must be able to handle the peak
250 inductor current without saturation. To minimize radiated
200 noise, use a toroid, pot core or shielded bobbin inductor.
150
RSENSE Selection and Maximum Output Current
100
3780ff
140
Multiple capacitors placed in parallel may be needed to
130
meet the ESR and RMS current handling requirements.
120
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
110 packages. Ceramic capacitors have excellent low ESR
characteristics but can have a high voltage coefficient.
100
0.1 1 10 Capacitors are now available with low ESR and high ripple
VIN/VOUT (V)
3780 F08
current ratings, such as OS-CON and POSCAP.
Figure 8. Load Current vs VIN/VOUT
3780ff
3780ff
3780ff
The following list summarizes the three possible connec- Run Function
tions for EXTVCC:
The RUN pin provides simple ON/OFF control for the
1. EXTVCC left open (or grounded). This will cause INTVCC LTC3780. Driving the RUN pin above 1.5V permits the
to be powered from the internal 6V regulator at the cost controller to start operating. Pulling RUN below 1.5V puts
of a small efficiency penalty. the LTC3780 into low current shutdown. Do not apply more
2. EXTVCC connected directly to VOUT (5.7V < VOUT < 7V). than 6V to the RUN pin.
This is the normal connection for a 6V regulator and
Soft-Start Function
provides the highest efficiency.
Soft-start reduces the input power sources surge cur-
3. EXTVCC connected to an external supply. If an external rents by gradually increasing the controllers current
supply is available in the 5.5V to 7V range, it may be limit (proportional to an internally buffered and clamped
used to power EXTVCC provided it is compatible with equivalent of VITH).
the MOSFET gate drive requirements.
An internal 1.2A current source charges up the CSS ca-
Output Voltage pacitor. As the voltage on SS increases from 0V to 2.4V,
the internal current limit rises from 0V/RSENSE to 150mV/
The LTC3780 output voltage is set by an external feedback
RSENSE. The output current limit ramps up slowly, taking
resistive divider carefully placed across the output capacitor.
1.5s/F to reach full current. The output current thus ramps
The resultant feedback signal is compared with the internal
up slowly, eliminating the starting surge current required
precision 0.800V voltage reference by the error amplifier.
from the input power supply.
The output voltage is given by the equation:
2.4V
R2 TIRMP = C = (1.5s/F ) CSS
VOUT = 0.8 V 1+ 1.2A SS
R1
Do not apply more than 6V to the SS pin.
Topside MOSFET Driver Supply (CA, DA, CB, DB) Current foldback is disabled during soft-start until the
Referring to Figure 11, the external bootstrap capacitors voltage on CSS reaches 2V. Make sure CSS is large enough
CA and CB connected to the BOOST1 and BOOST2 pins when there is loading during start-up.
3780ff
3780ff
4. CIN and COUT loss. The input capacitor has the difficult IL,BOOST 100
IRIPPLE,BOOST = %
job of filtering the large RMS input current to the regula- IIN
tor in buck mode. The output capacitor has the more
difficult job of filtering the large RMS output current in The highest value of ripple current occurs at VIN = VOUT/2.
boost mode. Both CIN and COUT are required to have A 6.8H inductor will produce 11% ripple in boost mode
low ESR to minimize the AC I2R loss and sufficient (VIN = 6V) and 29% ripple in buck mode (VIN = 18V).
capacitance to prevent the RMS current from causing
additional upstream losses in fuses or batteries. The RSENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
5. Other losses. Schottky diode D1 and D2 are respon- accommodation for tolerances.
sible for conduction losses during dead time and light
load conduction periods. Inductor core loss occurs 2 160mV VIN(MIN)
RSENSE =
predominately at light loads. Switch C causes reverse 2 IOUT(MAX,BOOST) VOUT + IL,BOOST VIN(MIN)
recovery current loss in boost mode.
When making adjustments to improve efficiency, the input Select an RSENSE of 10m.
current is the best indicator of changes in efficiency. If you Output voltage is 12V. Select R1 as 20k. R2 is:
make a change and the input current decreases, then the
VOUT R1
efficiency has increased. If there is no change in input R2 = R1
current, then there is no change in efficiency. 0.8
Select R2 as 280k. Both R1 and R2 should have a toler-
Design Example
ance of no more than 1%.
As a design example, assume VIN = 5V to 18V (12V nomi-
Next, choose the MOSFET switches. A suitable choice is
nal), VOUT = 12V (5%), IOUT(MAX) = 5A and f = 400kHz.
the Siliconix Si4840 (RDS(ON) = 0.009 (at VGS = 6V),
Set the PLLFLTR pin at 2.4V for 400kHz operation. The CRSS = 150pF, JA = 40C/W).
inductance value is chosen first based on a 30% ripple
The maximum power dissipation of switch A occurs in
current assumption. In buck mode, the ripple current is:
boost mode when switch A stays on all the time. Assum-
VOUT V ing a junction temperature of TJ = 150C with 150C =
IL,BUCK = 1 OUT
f L VIN 1.5, the power dissipation at VIN = 5V is:
2
IL,BUCK 100 12
IRIPPLE,BUCK = % PA,BOOST = 5 1.5 0.009 = 1.94W
5
IOUT
3780ff
12 5
QA QD
Double-check the TJ in the MOSFET at 70C ambient
temperature: D1
QB QC
TJ = 70C + 0.73W 40C/W = 99C
CIN COUT
RSENSE
LTC3780
CKT GND
3780 F10
3780ff
3780ff
PGND
RSENSE
24
23
22
21
20
19
18
17
16
15
14
13
10
11
12
1
2
3
4
5
6
7
8
9
R R
SGND
3780 F12
3780ff
G Package
24-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
7.90 8.50*
1.25 0.12
(.311 .335)
24 23 22 21 20 19 18 17 16 15 14 13
7.40 8.20
(.291 .323)
0 8
0.65
0.09 0.25 0.55 0.95
(.0256)
(.0035 .010) (.022 .037)
BSC 0.05
0.22 0.38 (.002)
NOTE:
(.009 .015) MIN
1. CONTROLLING DIMENSION: MILLIMETERS
TYP G24 SSOP 0204
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3780ff
UH Package
32-Lead Plastic QFN (5mm 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 0.05
5.50 0.05
4.10 0.05
3.45 0.05
3.50 REF
(4 SIDES)
3.45 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED BOTTOM VIEWEXPOSED PAD
PIN 1 NOTCH R = 0.30 TYP
0.75 0.05 R = 0.05 R = 0.115 OR 0.35 45 CHAMFER
5.00 0.10
TYP TYP
(4 SIDES) 31 32
0.00 0.05
0.40 0.10
PIN 1
TOP MARK
(NOTE 6) 1
2
3.45 0.10
3.50 REF
(4-SIDES)
3.45 0.10
3780ff
28
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection information
of its circuits www.linear.com/LTC3780
as described herein will not infringe on existing patent rights.
LTC3780
Revision History (Revision history begins at Rev F)
3780ff
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