A110 MIDAS: Multi-standard Integrated

Devices for broadband DSL Access and

www.medeaplus.org
home powerline communicationS

Activities. in WP3

Mechanisms, protocols and associated architectures for

Security/Safety and Quality
of Service (QoS
(QoS)) over DSL and PLC links
Contributors:
Contributors:
Alcatel (B), France Telecom R&D (F), Upzide Labs (Sw), Thomson (B), Ericsson (Sw), LTH (Sw),
ENS (F), Veyado (F)
Synoptical View Remote Powering
Responsible:
Responsible:
Line Downstream
Alcatel (B)

To line
Buffer Admission
Scheduler

ATM Processor
Activities:

ATM Filter
Activities:

Control

Priority +
1
A.3.1: Security/safety issues related to life-
life-line support, Enhanced priority based scheduler
remote powering and maintenance 8 Priority
B cells
A.3.2: Quality of Services over DSL and PLC links High
HW probe with Ethernet interface
GCR = B/T
A.3.2.a: Network traffic models, services classification, QoS requirements Low

Buffer Admission
Scheduler
A.3.2.b: Spectrum regulation, spectral management and resources management T seconds

ATM Processor
t

Policing
Control
Priority +
A.3.2.c: Bonding and inverse multiple access 1

From line
A.3.3: Higher layers protocols for QoS,
QoS, network security and user privacy Features
8 Buffer Admission Control
Scheduler
Line Upstream Policing : Dual GCRA

Quality of Service concepts SW probe linked to gateway or CPE firmware

Activities. in WP4

Building blocks and chipsets designs

for xDSL and PLC applications
Contributors:
Contributors:
ST (B), Alcatel (B), Thomson (B), ESAT-
ESAT-KUL (B), IMSE-
IMSE-CNM (Sp),
IMEC (B), DS2 (Sp)
Responsible:
Responsible:
ST (B)
Activities:
Activities:
A.4.1: Design of analogue building blocks for xDSL and PLC
High-voltage output driver Layout view of 14 bit A-D converter in 0.25m CMOS for ADSL CPE
A.4.1.a: Design of line drivers
in 2.5V 0.25m CMOS technology
A.4.1.b: Design of high-
high-speed converters
A.4.1.c: Design of integrated Analog Front-
Front-End
A.4.2: Design of digital building blocks and flexible/scalable architectures
architectures
A.4.3: Design of active splitters

Prototype board for

PLC Analogue Front-End
FPGA breadboard platform for PLC 1st generation validation

Activities. in WP5
Multi-
Multi-standard wireline integrated platforms,
platforms,
demonstration and tests First hardware version of DSP
Contributors:
Contributors: unit for VDSL Emulator,
Thomson (B), DS2 (Sp), France Telecom R&D (F), Seba service (B), IMEC- offering a noise floor better
IMEC-INTEC (B), LEA (F)
than -130 dBm/Hz
Responsible:
Responsible:
Thomson (B)
Activities:
Activities:
A.5.1: Development of integrated access platforms and gateways
A.5.2: Demonstration and tests of integrated platforms

Real Time Local Loop VDSL

Emulator based on Digital
Cable data from
Techniques
standards
demonstrations

field data
(country-specific cables)

Demonstrator set-up

STMicroelectronics Belgium N.V. For further information,

Industriepark Keiberg please contact Project Leader:
Excelsiorlaan 44-46 Patrick Wouters
B-1930 Zaventem, Belgium patrick.wouters@st.com
http://www.st.com
With thanks to all MIDAS partners
MEDEA+ Forum 2004, 23-24 November, Paris, France