Buat Ic

PSZ 19:16 (Pind.
1/97)
Universiti Teknologi Malaysia
BORANG PENGESAHAN STATUS TESISi

JUDUL : IMPROVED CHARACTERISTICS OF RADIO FREQUENCY
INTERDIGITAL CAPACITOR
(CIRI DIPERBAIKI KAPASITOR INTERDIGITAL
FREKUENSI RADIO)
SESI PENGAJIAN : 2005/2006-2
LIM YUN ROU

Saya
(HURUF BESAR)
mengaku membenarkan tesis (PSM/Sarjana/Doktor Falsafah)* ini disimpan di Perpustakaan

Universiti Teknologi Malaysia dengan syarat-syarat kegunaan seperti berikut:
1. Tesis adalah hakmilik Universiti Teknologi Malaysia.

2. Perpustakaan Universiti Teknologi Malaysia dibenarkan membuat salinan untuk tujuan
pengajian sahaja.
3. Perpustakaan dibenarkan membuat salinan tesis ini sebagai bahan pertukaran antara
institusi pengajian tinggi.
4. ** Sila tanda ( )
SULIT (Mengandsungi maklumat yang berdarjah keselamatan atau

kepentingan Malaysia seperti yang termaktud di dalam
AKTA RAHSIA RASMI 1972)
TERHAD (Mengandungi maklumat yang TERHAD yang telah ditentukan

oleh organisasi/badan di mana penyelidikan dijalankan)

TIDAK TERHAD
Disahkan oleh
(TANDATANGAN PENULIS) (TANDATANGAN PENYELIA)
Alamat Tetap:
2442, TAMAN KEMAMAN, PROF. MADYA DR. MAZLINA ESA
24000 KEMAMAN,
TERENGGANU. Nama Penyelia
Tarikh: 29th. April 2006 Tarikh: 29th. April 2006
CATATAN: * Potong yang tidak berkenaan.

** Jika tesis ini SULIT atau TERHAD, sila lampirkan surat daripada pihak berkuasa/organisasi
berkenaan dengan menyatakan sekali sebab dan tempoh tesis ini perlu dikelaskan sebagai
SULIT atau TERHAD.
i Tesis dimaksudkan sebagai tesis bagi ijazah Doktor Falsafah dan Sarjana secara penyelidikan,
atau disertai bagi pengajian secara kerja kursus dan penyelidikan, atau Laporan Projek
Sarjana Muda (PSM).
I hereby declare that I have read this project report and in my opinion this project is
sufficient in terms of scope and quality for the award of the degree of Master of
Engineering (Electrical Electronics & Telecommunication) by taught course.
Signature :
Name of Supervisor : PROF. MADYA DR. MAZLINA ESA
Date : 29th. APRIL 2006
IMPROVED CHARACTERISTICS OF RADIO FREQUENCY
INTERDIGITAL CAPACITOR
LIM YUN ROU
A project report submitted in fulfilment of the

requirements for the award of the degree of Master of Engineering
(Electrical Electronics & Telecommunication)
Faculty of Electrical Engineering

Universiti Teknologi Malaysia
APRIL, 2006
ii
I declared that this project report entitled

Improved Characteristics of Radio Frequency Interdigital Capacitor
is the result of my own research expect as cited in references. This report
has not been accepted for any degree and is not concurrently
submitted in candidature of any degree.
Signature :
Name of Author : LIM YUN ROU
Date : 29th APRIL 2006
iii
To My Beloved Family
iv
ACKNOWLEDGEMENTS
For the success of this study, I would like to thank all those who helped with
the work undertaken in this study especially to:-
My supervisor, Associate Professor Dr. Mazlina Esa for her valuable

guidance, assistance and advice, in which without her this study can never succeed.
My friends for their continuous suggestion and encouragement from the

beginning until the end of study.
Finally, I would like to dedicate my appreciation to my family for their

continuous support and encouragement.
v
ABSTRACT
Technology advances in complimentary-metal-oxide-silicon (CMOS) process

offer some interesting possibilities for radio frequency (RF) circuit designers. Some
circuits that would have to be done with GaAs monolithic microwave integrated
circuits (MMICs), for instance, are now possible in CMOS. While the transistor
speed has been improving significantly, fuller integration of RF integrated circuits
(RFICs) is often retarded by the absence of high quality, high rangebility and
efficient on-chip passive components. This thesis presents the possibilities of
improving the characteristics of an RF capacitor having interdigital configuration.
Modifications in the form of combline structure were introduced into the
conventional configuration to improve the capacitor characteristics. Performance in
the form of capacitance and Quality, Q, factor were investigated through simulations
using electromagnetic simulation software, Ansoft HFSS. The analysis and
comparison between conventional and the proposed interdigital capacitor (IDC) with
combline structure were discussed in detail. It can be concluded that the proposed
IDC with combline structure improves the capacitance of an IDC. The optimum
combline configuration which achieved useful capacitance with sufficiently high Q
factor is the design with 110 mils effective finger length. It produces 5.48 pF
capacitance at first resonance of 2 GHz, with sufficiently high Q factor of 13.88. This
is a factor of 1.72 higher than the corresponding conventional IDC having 3.18 pF at
first resonance of 3 GHz albeit 10 % slightly higher Q factor of 15.41.
vi
ABSTRAK
Kecanggihan teknologi pemprosesan silikon-oksida-logam-pelengkap

(CMOS) menawarkan peluang menarik kepada perekabentuk litar frekuensi radio.
Sesetengah litar yang perlu direkabentuk seperti menggunakan litar bersepadu
gelombang mikro monolitik (MMICs), kini boleh dilakukan dengan teknologi
CMOS. Sementara kelajuan transistor meningkat dengan pesat, penyepaduan
sepenuhnya litar bersepadu RF (RFIC) terbantut oleh ketiadaan komponen pasif atas-
cip yang berkualiti tinggi, berkebolehharapan tinggi dan tinggi kecekapan. Tesis ini
membentangkan kemungkinan untuk membuat penambahbaikan terhadap ciri
kapasitor RF menggunakan konfigurasi interdigital. Modifikasi berbentuk struktur
talian komb diperkenalkan pada kapasitor interdigital konvensional untuk
memperbaiki ciri prestasinya. Prestasi dalam bentuk kapasitan and faktor kualiti (Q)
dikaji menerusi simulasi perisian elektromagnet, Ansoft HFSS. Analisis dan
perbandingan antara kapasitor interdigital konvensional dan kapasitor interdigital
dengan struktur talian komb dibincang dengan terperinci. Dapat disimpulkan bahawa
kapasitor interdigital dengan struktur talian komb meningkatkan kapasitan bagi
kapasitor interdigital. Konfigurasi talian komb optimum yang memperoleh kapasitan
berguna dan faktor Q yang cukup tinggi adalah rekabentuk dengan panjang jari
berkesan bernilai 110 mil. Ia menghasilkan kapasitan 5.48 pF pada resonans pertama
2 GHz dengan faktor Q mencukupi sebesar 13.88. Nilai ini adalah 1.72 lebih tinggi
berbanding struktur IDC konvensional dengan 31.8 pF pada resonans pertama 3
GHz, namun dengan faktor Q = 15.41 yang 10 % sahaja lebih tinggi.
vii
TABLE OF CONTENTS
CONTENTS PAGE
TITLE i
ADMISSION ii
DEDICATION iii
ACKNOWLEDGEMENTS iv
ABTRACT v
ABSTRAK vi
TABLE OF CONTENTS vii
LIST OF TABLES x
LIST OF FIGURES xi
LIST OF SYMBOLS xvi
LIST OF ABBREVIATIONS xvii
CHAPTER I INTRODUCTION 1
1.1 Background of Study 1
1.2 Goals and Limitations of On-chip Capacitor 4

Design
viii
CONTENTS PAGE
1.3 Objectives 5
1.4 Scope of Project 6
1.5 Project Outline 7
CHAPTER II LITERATURE REVIEW 9
2.1 Basic capacitor at High Frequency 9
2.2 Capacitor Parameters and Model 13
2.3 Interdigital Capacitor (IDC) 15
2.4 Summary 22
CHAPTER III METHODOLODY 24
3.1 Introduction 24
3.2 Overall Project Flow 24
3.3 Implementation and Simulation of IDC with

Combline Structure 26
3.3.1 Layout of IDC with Combline Structure 26
3.3.2 Combline Structures as Capacitors with

Parallel Connection in High Frequency
Range 28
3.3.3 Simulation of Conventional and Combline

Interdigital Capacitor 32
ix
CONTENTS PAGE
CHAPTER IV RESULTS AND DISCUSSION 38
4.1 Introduction 38
4.2 S- and Z-parameters 38
4.3 Capacitance and Q Factor 54
CHAPTER V CONCLUSION 65
5.1 Conclusion 65
5.2 Recommendations for Future Improvement 66
REFERENCES 69
x
LIST OF TABLES
TABLE NO. TITLE PAGE
2.1 Capacitor behavior with respect to frequency range. 14
3.1 Settings and parameter assumptions in HFSS simulation

for experiment 1. 34



4.1 Summary of Capacitance and Q factor for both

conventional and combline IDC with 22 mils effective
finger length and 6 fingers (N = 6). 56


xi
LIST OF FIGURES
FIGURE NO. TITLE PAGE

Different types of CMOS or BiCMOS capacitor. (a)
1.1
MOSFET gate oxide capacitor, (b) MIM Capacitor, (c)
Double-poly capacitor, (d) IDC. 4
1.2 IDC configurations (a) basic, (b) six fingers. 6
2.1 Basic capacitor. (a)Two thin plate conductors with fixed

distance d, plate area A, and charges +Q on one plate and
Q on the other form a parallel-plate capacitor, (b)
Voltage is applied across the plates, the electric field in
the dielectric displaces electric charges. 9
2.2 System configuration consisting of two parallel plates in

the air. Fixed dimension d=8 cm, a=3 mm, h=1 mm. 10
2.3 Plots of the device susceptance against frequency for

three different localization of the input terminals. (a) d2 =
8 cm, d1 = 0 cm. (b) d2 = 6 cm, d1 = 2 cm. (c) d2 = 4 cm,
d1 = 4 cm. 12
2.4 Series RLC network representing behavior of a simple

parallel plate capacitor at high frequency. 13
2.5 Conventional interdigital capacitor layout, (a) Cross

section view. (b) Top view. 16
2.6 Interdigital capacitor in Gary D. Alley study and its low

frequency equivalent circuit. 17
xii
2.7 Coplanar interdigital capacitor. (a) Layout, (b) Circuit

model. 17
2.8 Series capacitance of coplanar interdigital capacitor with

finger length varying from 100 m to 350 m. 18
2.9 An IDC structure having zig-zag fingers. Structure

characteristics: w = 1.2 mm, t = 34 m, h = 1.27 mm, L =
2.6 mm, b = 2 mm, s = 0.2 mm, d = 0.28 mm, wf = 0.4
mm, = 90 , wb = 0.4 mm, wgx = 15.36 mm, wgy = 33.08
mm, Hr= 10.2. 18
2.10 Comparison of magnitude of S-parameter versus

frequency for conventional IDC, IDC with zig-zag
fingers and the equivalent circuit. 19
2.11 Equivalent circuit for the IDC structure with zig-zag

fingers. (a) Quasi static network, (b) nth high frequency
network. 20
2.12 Equivalent circuit of IDC. 21
2.13 LC sensors comprises of a series connected inductor and

interdigitated capacitor LC circuit printed on a plastic
substrate used in food quality control application. The
sensor is covered with a layer of polyurethane to prevent
the conductive biological medium from shorting the
capacitor and damping the resonance. 22
3.1 Flow chart showing the overall project activities. 25
3.2 Conventional IDC layout. 27
3.3 Planar IDC with combline structure and side feeder. 27
3.4 Two capacitors connected in parallel connection

operating at lower frequency and the equivalent
capacitance. 28
3.5 Capacitor model operating at high frequency range and

the simplified model. 29
xiii
3.6 Relationships of impedance versus frequency, (a) parallel

and (b) series equivalent circuit 30
3.7 Comparison of different capacitor impedance profiles. (a)

One 10 nF versus two 5 nF capacitors. (b) One 20 nF
versus two 10 nF capacitors. (c) One 20 nF versus four 5
nF capacitors. 31
3.8 Example of an combline IDC section equivalent to five

capacitors connected in parallel. 32
4.1 Simulation models in HFSS for conventional IDC with 6

fingers (N=6) and various effective fingers length, l. (a)
Simulation model with 45 view angle. (b) l = 22 mils
[1X], (b) l = 66 mils [3X] and (c) l = 110 mils [5X]. 39
4.2 Simulated return and insertion loss responses for the

conventional IDC with N=6 and increasing finger length
from 1X, 3X to 5X simulated from 1 GHz to 40 GHz. (a)
l = 22 mils, (b) l = 66 mils and (c) l = 110 mils. 40
4.3 Normalized impedance profile for conventional IDC with

N=6 and increasing effective fingers length from 1X, 3X
to 5X simulated from 1 GHz to 40 GHz. (a) l = 22 mils,
(b) l = 66 mils and (c) l = 110 mils. 42
4.4 Simulation models in HFSS for combline IDC with 6

fingers (N=6) and various effective fingers length, l. (a)
Simulation model with 45 view angle. (b) l = 22 mils
[1X], (b) l = 66 mils [3X] and (c) l = 110 mils [5X]. 43
4.5 Simulated return and insertion loss responses for the

combline IDC with N=6 and increasing finger length
from 1X, 3X to 5X simulated from 1GHz to 40 GHz. (a)
l = 22 mils, (b) l = 66 mils and (c) l = 110 mils. 44
xiv
4.6 Normalized impedance profile for the combline IDC with

N=6 and increasing finger length from 1X, 3X to 5X
simulated from 1GHz to 40 GHz. (a) l = 22 mils, (b) l
= 66 mils and (c) l = 110 mils. (b) l = 66 mils. (c) l =
110 mils 46
4.7 Simulation models in HFSS for conventional IDC with

22 mils effective fingers length (l = 22 mils) and various
finger numbers, N. (a) Simulation model with 45 view
angle, (b) N = 6 [1X], (c) N = 12 [ 2X] and (c) N = 18
[3X]. 47
4.8 Simulated return loss and insertion loss responses for the
conventional IDC with 22 mils effective finger length (l
= 22 mils) and increasing total fingers from 1X, 2X to
3X simulated from 1GHz to 40 GHz. (a) N = 6. (b) N =
12. (c) N = 18. 48
4.9 Normalized impedance profile for conventional IDC with

22 mils effective fingers length (l = 22 mils) and
increasing total fingers from 1X, 2X to 3X simulated
from 1 GHz to 40 GHz. (a) N = 6. (b) N = 12. (c) N =
18. 50
4.10 Simulation models in HFSS for combline IDC with 22

mils effective fingers length (l = 22 mils) and various
finger numbers, N. (a) Simulation model with 45 view
angle, (b) N = 6, (c) N = 12 and (d) N = 18. 51
4.11 Simulated return loss and insertion loss responses from 1

GHz to 40 GHz for combline IDC with 22 mils effective
finger length (l = 22 mils) and increasing total fingers.
(a) N = 6. (b) N = 12. (c) N = 18. 52
4.12 Normalized impedance profile for combline IDC with 22

mils effective fingers length (l = 22 mils) and various
finger numbers, N, (a) N = 6, (b) N = 12 and (c) N = 18. 53
xv
4.13 Capacitance versus frequency trend for both

conventional and combline IDCs with 22 mils effective
finger length (l = 22 mils) and 6 fingers (N = 6). 55
4.14 Q factor versus frequency trend for both the conventional

and combline IDCs with 22 mils effective finger length
(l = 22 mils) and 6 fingers (N = 6). 55
4.15 Capacitance versus frequency trend for both the

conventional and combline IDCs with 66 mils effective
4.16 Q factor versus frequency trend for both the conventional

and combline IDCs with 66 mils effective finger length
(l = 66 mils) and 6 fingers (N = 6). 57
4.17 Capacitance versus frequency trend for both

4.18 Quality factor (Q) versus frequency trend for both

4.19 Comparison of Q factor for conventional IDC with

various finger lengths. 62
4.20 Comparison of Q factor for combline IDC with various

finger lengths. 62
4.21 Comparison of Q factor for the conventional IDC with

various total finger number, N. 63
4.22 Comparison of Q factor for the combline IDC with

various total finger number, N. 64
5.1 Planar IDC with combline structure and center feeder. 67
5.2 Coplanar IDC with combline structure and center feeder. 68

xvi
LIST OF SYMBOLS
A - Area
C - Capacitance
d - Distance
f - Frequency
fo - Self resonance frequency
h - Dielectric thickness
L - Inductance
l - Fingers length
l - Effective fingers length
M - Number of capacitors connected in a network
N - Total capacitor fingers
N - Total combline fingers per finger
Q - Electric charges
R - Resistance
s - Spacing between fingers
s - Spacing between combline fingers
t - Conductor height
w - Finger width
w - Combline fingers width
Xc - Reactance
Hr - Dielectric relative permittivity
xvii
LIST OF ABBREVIATIONS
CMOS - Complementary metal oxide semiconductor

ESL - Equivalent series inductance
ESR - Equivalent series resistance
FDTD - Finite-difference time domain
FEM - Finite element model
IC - Integrated circuit
IDC - Interdigital capacitor
MIM - Metal-insulator-metal
MOSFET - Metal oxide semiconductor effect transistor
PCB - Printed circuit board
Q - Quality factor
RFIC - Radio frequency integrated circuit
CHAPTER I
INTRODUCTION
1.1 Background of Study
The growth of smaller, more power-sensitive wireless-communication

products has fueled the explosive development of radio frequency integrated circuits
(RFICs) [1]. Highly integrated RF components now populate ICs, replacing the
hybrid circuits that used discrete semiconductor devices. As a result, RFICs can be
found in applications that blanket the wireless space, ranging from cellular to
wireless LANs and everything in between. There are many challenges involved in
creating RFICs. At the transistor level, various competing technologies (GaAs, Si,
SiGe, and CMOS) each provide different benefits and drawbacks. Aside from the
transistors, the creation of passive components such as inductors, capacitors, and
resistors also pose unique challenges to the IC designer.
Passive components are referred to as glue components because they

glue integrated circuits together to make a system. For the accurate design and
fabrication of these compact high performance systems, accurate modeling of on
chip passive components is becoming very important. However, designing circuits
with these passive components is non-trivial due to electromagnetic interactions that
lead to parasitic, and ultimately non-ideal frequency behavior. Passive devices
2
generally have complex geometries, non-uniform current flow, and correspondingly

complex field patterns; therefore, suffer from parasitic effects that influence the
electrical behavior of the device at different frequencies. For this reason, accurate
models of passive components are crucial for designing and characterizing high
performance systems.
Building high-quality on-chip capacitors has attracted tremendous interest

from the RFIC design community and semiconductor manufacturers. High-quality
on-chip capacitors have been widely demonstrated as a key factor for successfully
integrating RF building blocks, such as resonant circuits and filters, voltage-
controlled oscillators, coupling between stages and bypassing [1]. Other
characteristics by which such capacitors are judged include capacitance density;
parasitic capacitance to ground; voltage, temperature and frequency coefficients; and
the maximum allowable peak repetitive voltage. As shown in Figure 1.1,
commercial CMOS or BiCMOS processes the following capacitors are generally
available:
(a) Capacitors that use the MOSFET gate oxide [2]

The highest capacitance densities are obtained with these capacitors.
Capacitance density of 6 fF/2 has been reported [2]. However, there is a trade-off
between the gate oxide thickness and the breakdown voltage. A 50-Angstrom gate
oxide capacitor in a 0.25 processes can typically withstand a maximum peak
repetitive voltage of 2.75V. Depending on the topology and circuit design this may
be a limitation. The CV characteristic varies with the particular process technology
and is non-linear. This non-linearity may cause distortion in the circuit.
(b) Metal-insulator-metal (MIM) capacitors [3, 4]

MIM capacitors are typically built near the top of the metal stack to minimize
parasitic capacitance to ground; for example, a bottom-plate using METAL4 and a
top-plate using METAL5 separated by a thin insulator layer a few hundred
Angstroms thick. The large separation between the bottom plate and substrate ( 6)
3
helps in reducing the parasitic capacitance to ground to approximately 2% of the

useful inter-metal capacitance (trans-capacitance). MIM capacitors have very good
voltage and temperature-coefficient characteristics and a capacitance density of
approximately 0.8fF/2. MIM capacitors are available in many RF CMOS and
BiCMOS processes, however, they require extra masking steps to implement and
increase the cost of the IC. Furthermore, these devices do not scale with process
technology
(c) Poly-insulator-gate poly (Double Poly) capacitors [2]

Double-poly and MOS capacitors also have parasitic capacitance associated
with them. Double-poly capacitors have about 18% parasitic capacitance to ground
while MOS capacitors can have 2~20% parasitic capacitance to ground depending
upon their design. Both MOS and double-poly capacitors have the problem of very
high series resistance to one of the two nodes.
(d) Planar Interdigital capacitor (Planar IDC) [5]

Planar Interdigital capacitors hold much promise in providing capacitors that
continue to improve with succeeding process technologies. Capacitance density
increases significantly as the number of metal layers increase and the feature size
decreases. Such capacitors can be optimized to minimize parasitic capacitance and
to make the parasitic capacitance symmetric, thus reducing noise pickup from the
substrate or nearby structures.
4
(a) (b)
(c) (d)
Figure 1.1: Different types of CMOS or BiCMOS capacitor. (a) MOSFET
gate oxide capacitor, (b) MIM Capacitor, (c) Double-poly capacitor, (d) IDC
1.2 Goals and Limitations of On-chip Capacitor Design
High-performance on-chip capacitors are required to implement RF

integrated circuits [6]. The main requirements for high-performance capacitors are
capacitance density, symmetry and high quality factor. Recent literature [6]
emphasizes exclusively either high capacitance density or high Q because
improvement in Q tends to come at the expense of capacitance density.
For a number of sensitive applications, capacitors with a Q > 15-20 at

frequency range of interest are required. However, there is a limitation in obtaining a
5
high Q factor especially at high frequency range in most of todays applications.

These limitations in the poor Q factor are primary due to the resistive losses in the
plates and contacts and due to the parasitic capacitance between the passive
component and the lossy silicon substrate [7]. Thus, lots of researches and studies
are currently on going and some has been carried out focusing on different ways to
obtain high Q and high capacitance capacitors. Some researches focus on various
capacitors layout and dimensions; some of these studies focus on material science
looking for new low loss materials which is suitable for planar capacitor
implementation. Accurate capacitor model which gives accurate simulation results
for Q factor and series resistance (ESR) is crucial as well for RF circuit design and
characterization.
1.3 Objectives
The main objective of this project is to improve the characteristics of a planar

interdigital radio frequency capacitor by employing combine structure. The
performance in the form of capacitance and Q factor of the modified interdigital
capacitor with the conventional configuration interdigital capacitor are compared. It
is aimed to obtain a planar combline interdigital capacitor which is able to produce
higher capacitance with sufficiently high Q factor of at least 15 in a wider frequency
range which suits todays application in various fields. The basic and combline
configurations are depicted in Figure 1.2.
6
(a)
(b)
Figure 1.2: IDC configurations (a) basic, (b) six fingers.
1.4 Scope of Project
The project is focused on developing an interdigital capacitor configuration

that will exhibit a high capacitance density as well as high Q-factor. The scope of
the project covers the following areas:
7
Study of the theory and fundamentals of RF interdigital capacitor.

This includes basic design of lumped elements, basic capacitor theories,
parameters that affect capacitor performance, parameters that used for capacitor
performance evaluation, electrical representation of capacitors, interdigital capacitor
design and performance improvement techniques.
Modification of the conventional interdigital configuration with combline

structure for performance improvement.
Based on the theories and work done by other researchers, the study further
explore and investigate the possibility of improving the interdigital capacitor
performance by varying different layout options with combline structure.
Electromagnetic simulations.
Simulations of the conventional and modified interdigital configurations were
performed using Ansoft HFSS electromagnetic simulation software.
Analysis of the results.

Performance comparison of the modified and conventional configuration
interdigital capacitor in terms of Q factor and capacitance density.
1.5 Outline of Thesis
Chapter one discusses the objectives and scope of the project and gives a
general introduction to RFICs and functions of on chip capacitors in RFIC. This
chapter also clearly discusses the motivation behind the study and the limitations in
order to achieve the project objectives.
8
In Chapter two, relevant literature and previous work regarding planar

interdigital capacitor characterization are reviewed. This chapter also elaborates on
the principles of capacitor and the factors that must be taken into consideration to
obtain a good capacitor for RFIC usage.
The design and analysis approach used in this project are elaborated in
Chapter three. The overall activities of this study are discussed in this chapter.
Besides, this chapter also discusses in detail the capacitor modification flow of the
proposed interdigital capacitor with combline structure and simulation flow of the
designed capacitors using Ansoft HFSS simulation software.
In Chapter four, the final results are presented and analyzed in detail. This
includes the modifications from the basic configuration to various combline
configurations.
The final chapter concludes the thesis. Suggestions for further improvement
are also presented.
CHAPTER II
LITERATURE REVIEW
2.1 Basic Capacitor at High Frequency
In principle, a capacitor is a energy storing device made up of two parallel

conductive plates separated by an insulating (dielectric) material as shown in Figure
2.1(a). Figure 2.1(b) shows when a voltage is applied across the plates, the electric
field in the dielectric displaces electric charges, and thus stores energy. It is assumed
that there are no free charges in the dielectric (at least in the ideal case), and that
while they are displaced, they are not free to move around as in a conductor [8].
(a) (b)
Figure 2.1: Basic capacitor. (a)Two thin plate conductors with fixed distance d, plate
area A, and charges +Q on one plate and Q on the other form a parallel-plate
capacitor, (b) Voltage is applied across the plates, the electric field in the dielectric
displaces electric charges [8].
10
The capacitance is calculated based on the formulation [8]:
HA
C (Eqn. 2.1)
d
where H # dielectric constant, A # area of the conductor and d # distant between two
conductors.
However, capacitor behavior changes as the operating frequency increases

from low frequency to Gigahertz range. J. A. Brandao Faria did an analysis on basic
parallel plate capacitor high frequency behavior characterization [9]. In his work, a
structure consisting two parallel plate, ordinarily identified as plane capacitor, is
analyzed from the viewpoint of a distributed parameter system. Consider the
configuration depicted in Figure 2.2 consisting of two parallel conducting plates
implanted as shown.
Figure 2.2: System configuration consisting of two parallel plates in the air. Fixed
dimension d=8 cm, a=3 mm, h=1 mm [9].
The capacitor susceptance versus frequency curves in Figure 2.3 have been
obtained considering the fixed dimension as shown in Figure 2.2. Three different
localizations of the capacitor terminals have been examined as follow.
11
Case A: d2 = d and d1 = 0
Case B: d2 = 3d/4 and d1 = d/4
Case C: d2 = d/2 and d1 = d/2
Observing the graphs in Figure 2.3, one verifies, for some frequencies that
the susceptance becomes infinite (the source connected at points A/B faces a short
circuit). Some frequencies, the susceptance goes to zero (the source at A/B face an
open circuit as in the DC regime). It is also evident that frequency bands exist where
S(Z) is negative, revealing that the device may behave as an inductive component.
From the results, it can be summarized as: system losses were neglected; dielectric
permittivity H was taken as a frequency-independent parameter; fringing field effects
at the system edges were neglected; geometry dimensions a and h were assumed to
be very small as compared to the operating wavelength. Removal of these
assumptions would lead to a more accurate analysis. The work has shown that a
simple parallel plate structure may exhibit a quite unexpected frequency behavior
when the operating wavelength is relatively smaller compared to the component size.
Dimension do affects the performance of capacitor at high frequency range.
12
Figure 2.3: Plots of the device susceptance against frequency for three different
localization of the input terminals. (a) d2 = 8 cm, d1 = 0 cm. (b) d2 = 6 cm, d1 = 2 cm.
(c) d2 = 4 cm, d1 = 4 cm [9].
13
2.2 Capacitor Parameters and Model
As mentioned in chapter one, the main requirements for high performance

capacitors are capacitance density, symmetry and high Q factor. One of the most
important parameters in evaluating a high frequency on chip capacitor is the Q factor
or the related equivalent series resistance (ESR, in ohms). Ideal capacitor exists only
in theory. A perfect capacitor would exhibit an ESR or 0 (zero) ohms and would be
purely reactive with no real (resistive) component [10]. The current going through
the capacitor would lead the voltage across the capacitor by exactly 90 degrees at all
frequencies [10].
In real world usage, no capacitor is perfect, and will always exhibit some
finite amount of ESR [10]. The ESR varies with frequency for a given capacitor, and
is equivalent because its source is from the characteristics of the conducting
electrode structures and in the insulating dielectric structure. All practical capacitors
behave similarly to the series RLC network shown in Figure 2.4. For the purpose of
modeling, the ESR is represented as a single series parasitic element in the RLC
network [11].
Figure 2.4: Series RLC network representing behavior of a simple parallel plate
capacitor at high frequency [11].
Capacitor behavior changes with the increasing frequency range. The

behavior can be break down into three frequency range [11] as shown in Table 2.1.
14
Table 2.1: Capacitor behavior with respect to frequency range
Frequency Impedance
Low Capacitive
Self Resonance Resistive
High Inductive
At low frequencies, the capacitors impedance looks just like what everyone would
expect from the specified capacitor value. At self resonance, the capacitive and
inductive impedances cancel each other out leaving only a resistive component. The
resistive component is also referred to as ESR. Above self- resonance, the inductive
reactance takes over as it grows much larger than the capacitive reactance and ESR.
The self resonance is given by the formulation [11]:
1
fo (Eqn. 2.2)
2S LC
where fo # self resonance frequency (Hz), L # inductance (H) and C # capacitance.
The Q factor is a dimensionless number that is given by the formulation [11]:
XC
Q (Eqn. 2.3)
ESR
where |XC| is the absolute value of the reactance in ohms and is given by [11]:
15
1
XC (Eqn. 2.4)
2S f C
The value of Q changes greatly with frequency as both reactance and

resistance change with frequency. The reactance of a capacitor changes tremendously
with frequency or with the capacitance value, and therefore the Q value could vary
by a great amount. To obtain a capacitor with high Q factor, the capacitors ESR
need to be as low as possible.
2.3 Interdigital Capacitor (IDC)
The interdigital (or interdigitated) capacitor is a passive element which

produces a capacitor-like, high pass characteristic using microstrip lines. The shape
of conductor is defined by the parameters shown in Figure 2.5. The long conductor
also known as fingers provide coupling between the input and output ports across
the gaps. Typically, the gaps (G) between fingers and at the end of the fingers (GE)
are the same. The length (L) and width (W) of the fingers are also specified. Since the
conductors are mounted on a substrate, the substrate height (h) and its dielectric
constant (Hr) will also affect the capacitor performance. In addition, the thickness of
the conductor (t) and its resistivity (U) also impact the electrical characteristics.
16
Figure 2.5: Conventional interdigital capacitor layout, (a) Cross section view. (b)
Top view.
Gary D. Alley was the founder of interdigital capacitor and proposed the
equivalent circuit at year 1970 as shown in Figure 2.6 [12]. He analyzed the
frequency response of interdigital capacitors, which leads to an optimal design, and
given along with an expression for the static gap capacitance. The capacitor Q factor
is given in terms of its geometry which consists of a planar interdigital conductor
deposited on the surface of a relatively high dielectric constant substrate.
Capacitance values ranging from 0.1 to 10 pF at L band with measured Qs in excess
of 400 are realizable using 2-rail line and space widths on a 99.5-percent alumina
substrate with a dielectric constant of 10.3 [12]. For a maximum capacitance density
with this configuration, the finger width and space width must be equal.
17
Figure 2.6: Interdigital capacitor in Gary D. Alley study and its low frequency
equivalent circuit [12].
Coplanar interdigital capacitor in Figure 2.7 was proposed at 1979 after

modified from Alleys previous work, where the ground reference is designed
surrounding the signal microstrip lines. The effect of extra lines between A and B, as
well as A and B were de-embedded and included in the model. This configuration
provides increasing capacitance with the finger length increment, shown in Figure
2.8 [13].
Figure 2.7: Coplanar interdigital capacitor. (a) Layout, (b) Circuit model [13].
18
Figure 2.8: Series capacitance of coplanar interdigital capacitor with finger length
varying from 100 m to 350 m [13].
Besides coplanar interdigital capacitor, another modification from the

conventional configuration was proposed. Figure 2.9 shows the proposed structure
where the straight fingers are modified to be zig-zag fingers. Interdigital capacitor
with zig-zag fingers was found to perform better than straight fingers [14].
Figure 2.9: An IDC structure having zig-zag fingers. Structure characteristics: w =

1.2 mm, t = 34 m, h = 1.27 mm, L = 2.6 mm, b = 2 mm, s = 0.2 mm, d = 0.28 mm,
wf = 0.4 mm, = 90 , wb = 0.4 mm, wgx = 15.36 mm, wgy = 33.08 mm, Hr= 10.2.
[14].
19
The structure in Figure 2.9 was analyzed by matched at both ends, and
excited by a 50 1 voltage source of unit amplitude. The substrate has thickness h =
1.27 mm and conductivity g = 0.01 S/m, while the ground plane and the metallic
traces forming the device have thickness t = 34 m and conductivity g = 5.8u107
S/m. The magnitude of the scattering parameters in the frequency range 06 GHz,
obtained employing the FDTD technique, is given in Figure 2.10. Comparing these
curves, it appears that only a small high-frequency circuital degradation takes place
in the structure having zig-zag fingers. This happens because zig-zag discontinuities
enhance emission phenomena in terms of surface and volume waves. A capacitance
0.49 pF, for the conventional IDC structure, and a capacitance 0.54 pF, for that
having zig-zag fingers, have been found. Hence, obtaining an increment of about
10% of the parameter. This confirms that better performances can be obtained using
IDC structures having zig-zag fingers.
Figure 2.10: Comparison of magnitude of S-parameter versus frequency for

conventional IDC, IDC with zig-zag fingers and the equivalent circuit [14].
A frequency independent equivalent circuit of this structure is shown in

Figure 2.11. The circuit is composed of an infinite number of shunt sub -networks
used to model all the dynamic phenomena excited in the device. In particular, the
resistancecapacitance (RC) network models the quasi-static device behavior, while
20
the resistanceinductancecapacitance (RLC) networks take into account for the

dynamic effects related to the distributed nature of the device. The resistive elements
in the low-frequency network take into account for the dielectric losses, while those
present in the high-frequency networks are also representative for metal and radiation
losses.
(a) (b)
Figure 2.11: Equivalent circuit for the IDC structure with zig-zag fingers. (a) Quasi
static network, (b) nth high frequency network [14].
The design and characterization of an IDC based on artificial neural network

(ANN) and genetic algorithm (GA) is another approach presented in [15]. The
multilayer feed-forward neural network models were presented for the fast design
and characterization of IDC. The training and testing samples were first calculated by
finite-difference time-domain (FDTD). The physical dimensions of the IDC and the
desired frequency were the input to the neural network model. The S-parameters of
designed IDC over the respective frequency band were the output. The equivalent
circuit of IDC used in this design is shown in Figure 2.12, where the dominant
element is the capacitor C. The capacitor C1 is the scattering capacitance with respect
to the ground plane and its magnitude decrease with increasing substrate thickness.
The resistor R results from the energy loss of the circuit.
21
Figure 2.12: Equivalent circuit of IDC [15].
The relationships between C, R and C1 with the scattering parameters of the

IDC are as follows:
2 S 21
C imaginary (Eqn. 2.5)
(1 S11 S 21 ) (1 S11 S 21 ) Z
2 S 21
R real (Eqn. 2.6)
(1 S11 S 21 ) (1 S11 S 21 ) Z
1 S11 2 S 21
C1 imaginary
(Eqn. 2.7)
(1 S11 S 21 ) Z
From Equations 2.5 to 2.7 [15], the capacitance and Q factor of the IDC can
be subsequently obtained using the S-parameters extracted from the model by
applying the following formulation:
22
Xc 1
Q(Z ) (Eqn. 2.8)
R ZC R
Some examples of the IDC application in real circuit implementation are

phase shift circuit design, IDC as sensors for resonant LC circuit sensors used in food
quality control application and RFIC filters design [16]. Figure 2.13 shows one of
the examples of IDC used for LC sensor design.
Figure 2.13: LC sensors comprises of a series connected inductor and interdigitated

capacitor LC circuit printed on a plastic substrate used in food quality control
application. The sensor is covered with a layer of polyurethane to prevent the
conductive biological medium from shorting the capacitor and damping the
resonance [16].
2.4 Summary
It has been observed that IDC is one of the passive components being widely
used in RF circuit designs. Thus it is important to have an IDC which is high quality
and high rangebility to ensure that the same capacitor can be used across different
applications and design purposes. It can be summarized that there are several
23
important parameters that can change the characteristics of a capacitor especially in

the high frequency range. These are the dimensions, stack-up and layout of the
capacitor. It is possible to perform the characterization of capacitor in both time
domain and frequency domain. Capacitance values and Quality factor of a capacitor
can be computed based from its S-parameters.
CHAPTER III
METHODOLOGY
3.1 Introduction
This chapter discusses step by step flow in this project. At the end of this
chapter, a complete set of flowchart of the project is given.
3.2 Overall Project Flow
Figure 3.1 is the flow chart showing the overall project activities. This
project begins with the literature review on fundamentals of capacitor, capacitor
behaviors at high frequency range and study of radio frequency integrated circuits
(RFICs). With the understanding of capacitor theory, scope of literature review is
then focused to the previous research done in interdigital capacitors. It is important to
understand the motivation behind interdigital capacitors, how does it works, what is
the goal and limitation in interdigital capacitor design, critical parameters that affect
the performance and what are the techniques to improve and optimize the
performance.
25
By applying the knowledge and theory gained from the literature studies, this
project is then proceed with the investigation of possibilities to improve the
performance and characteristics of conventional interdigital capacitors. Combline
structure IDC layout modification was proposed to improve the capacitance density
and quality factor (Q) of the capacitor. Simulation of the conventional and proposed
modified interdigital capacitors is then performed using Ansoft HFSS
electromagnetic simulation software.
Simulation results in the form of S, Y and Z parameters are obtained. The

capacitance value and Q factor of the layout under test are with respect to frequency
are then computed from the S, Y and Z parameters obtained from the simulation.
Capacitance density and Q factor of the conventional and modified IDC are then
compared and analyzed. If the modified configuration does not provide a better
performance compared to the conventional configuration, dimension of the proposed
layout will be varied and simulate to obtain an optimized layout. This step is repeated
until an performance improvement is obtained.
Figure 3.1: Flow chart showing the overall project activities.

26
3.3 Implementation and Simulation of IDC with Combline Structure
The capacitance of a capacitor as given by Equation 2.1 in Chapter 2 is

affected by the area of the plates, the distance between the plates, and the ability of
the dielectric to support electrostatic forces. By varying these parameters, it affects
the capacitance of a capacitor. Larger plates provide greater capacity to store electric
charge. Therefore, as the area of the plates increase, capacitance increases.
Capacitance is directly proportional to the electrostatic force field between the plates.
This field is stronger when the plates are closer together. Therefore, as the distance
between the plates decreases, capacitance increases. Dielectric materials are rated
based upon their ability to support electrostatic forces in terms of a number called a
dielectric constant. The higher the dielectric constant, the greater is the ability of the
dielectric to support electrostatic forces. Therefore, as the dielectric constant
increases, capacitance increases. Besides, ESR of the capacitor also plays an
important role in defining its Q factor.
This section explored the effect of capacitor dimension and placement to the
capacitance value and Q factor. Subsequently, IDC modifications with combline
structure are presented. This chapter also fully discussed the step by step design and
simulation flow of the conventional and proposed interdigital capacitor with
combline structure using Ansoft HFSS electromagnetic simulation software.
3.3.1 Layout of IDC with Combline Structure
This section presented the proposed layout configurations of interdigital

capacitor with combline structure. Figure 3.2 illustrates the conventional IDC layout.
Figure 3.3 shows the layout of a side feed planar IDC with combline structure. The
proposed layout has additional fingers on the conventional fingers. The additional
27
combline structures are intended to add more coupling between the two microstrip
lines, and subsequently increase the total capacitance of the capacitor.
Figure 3.2: Conventional IDC layout.
Figure 3.3: Planar IDC with combline structure and side feeder.
28
3.3.2 Combline Structures as Capacitors with Parallel Connection in High

Frequency Range
When capacitors are connected in parallel, the total capacitance is the sum of
the individual capacitors' capacitances. If two or more capacitors are connected in
parallel, the overall effect is that of a single equivalent capacitor having the sum total
of the plate areas of the individual capacitors. The total capacitance of capacitors
connected in parallel in Figure 3.4 can be calculated by the formulation:
C Total C1 C 2 .... C n (Eqn. 3.1)
where CTotal = Total capacitance in parallel connection and C1 , C2 , Cn = Capacitance

value for each capacitor in parallel. For example, a 10 nF capacitor is equivalent to
two 5 nF capacitors.
Figure 3.4: Two capacitors connected in parallel connection operating at lower

frequency and the equivalent capacitance [17].
At high frequency range, capacitors experience parasitic ESL and ESR. When
N number of capacitors with equal capacitance value connected in parallel as shown
in Figure 3.5, it gives the equivalent capacitance with lower effective ESL and ESR.
The effective values are as follow.
29
ESL
ESLeq (Eqn. 3.2)
N
ESR
ESReq (Eqn. 3.3)
N
C eq C u N (Eqn. 3.4)
where ESLeq = Total ESL in parallel connection, ESL = ESL value for each
individual capacitor, ESReq = Total ESR in parallel connection, ESR = ESR value for
each individual capacitor, Ceq = Total capacitance in parallel connection, C =
Capacitance value for each individual capacitor and N = number of capacitors
connected in the network
Equivalent to
Figure 3.5: Capacitor model operating at high frequency range and the simplified
model [17].
To prove that the circuits are equivalent, two models of impedance versus
frequency are computed. The models are parallel and series equivalent circuits,
respectively. The relationships are shown in Figure 3.6. It is clearly seen that both
curves correlated very well.
30
(a) (b)
Figure 3.6: Relationships of impedance versus frequency, (a) parallel and (b) series
equivalent circuit.
In the next examples, single capacitors are compared with parallel

combinations of smaller capacitors, giving same equivalent capacitance values.
Figure 3.7 shows the relationships. Based on the impedance profiles shown in Figure
3.7(a), by connecting two 5 nF capacitors in parallel compared to one 10 nF
capacitor, the impedance curve shifts to the right. This is due to the reduction of
effective ESL. The impedance after resonance frequency is also lower caused by the
reduction of inductance relatively. Impedance profile in Figure 3.7(b) shows the
same trend as well. Figure 3.7(c) is the comparison of impedance profile for a circuit
made up by four 5 nF capacitors and one 20 nF capacitor. The curve shifted further
to the right side compared to Figure 3.7(b). This proves that when more capacitors
are connected in parallel, the effective ESL will be lower.
31
(a) (b)
(c)
Figure 3.7: Comparison of different capacitor impedance profiles. (a) One 10 nF versus
two 5 nF capacitors. (b) One 20 nF versus two 10 nF capacitors. (c) One 20 nF versus
four 5 nF capacitors.
The high frequency characteristics of capacitors connected in parallel gives

an advantage to interdigital capacitor. By designing the interdigital capacitor layout
with parallel connection, it provides the equivalent capacitance value and lower
effective ESL and ESR. Figure 3.8 shows the example on how an interdigital
capacitor can be considered as a number of capacitors connected in parallel.
Since an interdigital capacitor is equivalent to few shunt capacitance, by

designing more fingers to the IDC, its total capacitance will increase and at the same
time reduce the effective ESL and ESR. Thus, the three proposed IDC with
combline structures are expected to have a increment of capacitance and Q factor by
32
a factor of 2 respectively. However, the additional fingers might create more mutual
coupling between fingers end which may increase the fringing effect. Thus, it is
important to simulate and validate these proposed configurations to ensure the
fringing effect will not affect the overall performance of the capacitor.
C1 C2 C3 C4 C5
C1
C2
C3
+ -
C4
C5
Figure 3.8: Example of an combline IDC section equivalent to five capacitors

connected in parallel.
3.3.3 Simulation of Conventional and Combline Interdigital Capacitor
In this study, Ansoft HFSS V9.0 electromagnetic simulation software has

been used to simulate and analyze the conventional and combline IDC. The
33
conventional IDC simulation is used as the control case while the combline IDC
simulation is used as the experimental case and compared to the control case. The
analysis was done on three-dimensional (3D) basis in order to check the behavior of
both IDCs under high frequency operating condition. This section focuses on the
description of model dimension, material, experimental setting and other critical
criteria of simulation and analysis.
(a) General overview of Ansoft HFSS V9.0
HFSS is the industry-standard software for S-parameter and full-wave SPICE

extraction and for the 3D electromagnetic simulation of high-frequency and high-
speed components. HFSS is widely used for the design of on-chip embedded
passives, PCB interconnects, antennas, RF/microwave components, and high-
frequency IC packages. It employs 3D full wave Finite Element Method (FEM) and
adaptive meshing to compute the electrical behavior of high frequency components
or structures. HFSS can be used to extract the parasitic parameters (S, X, Z),
visualize 3D electromagnetic fields (near- and far-field), generate broadband SPICE
models and optimize design performance. It accurately characterizes the electrical
performance of components including transmission path losses, reflection loss due to
impedance mismatch, parasitic coupling and radiation. Since the study of IDC is
focused on the high frequency operating range, the characteristics of IDC are highly
affected by the transmission path losses, parasitic coupling and radiation. Thus HFSS
software is suitable for the study.
(b) IDC Structure Building in HFSS
The study is divided into two sections to investigate the effects of finger
length and total capacitor width to the characteristics of the capacitor. Some
assumptions made in the study are tabulated in Tables 3.1 to 3.4. Simulations were
34
then carried out by sweeping the frequency from 1 GHz to 40 GHz. The simulation
results in terms of S, Y and Z parameters were obtained.
Table 3.1: Settings and parameter assumptions in HFSS simulation for experiment 1.
Experiment Experiment Setting
1. Conventional IDC with varying finger length
Parameter Values
Dielectric material 99.5-percent alumina
Dielectric relative permittivity, Hr 10.2
Dielectric thickness, h 24 mils
Conductor material Copper (Hr = 1)
Conductor height, t 1.4 mils
Total fingers, N 6
Finger width, w 2 mils
Spacing between fingers, s 2 mils
Fingers length, l (a) 24 mils
(b) 68 mils
(c) 112 mils
Fingers effective length, l (a) 22 mils [ 1X ]
(b) 66 mils [ 3X ]
(c) 110 mils [ 5X ]

35
Experiment Experiment setting
2. Combline IDC with varying finger length
Parameter Values
Total fingers, N 6
Fingers width, w 2 mils
Combline fingers width, w 2 mils
Spacing between combline fingers, s 2 mils
Fingers length, l (a) 24 mils
(b) 68 mils
(c) 112 mils
Fingers effective length, l (a) 22 mils [ 1X ]
(b) 66 mils [ 3X ]
(c) 110 mils [ 5X ]
(a) 3
Total Combline fingers per finger, N (b) 8
(c) 14
36
Experiment Experiment setting
3. Conventional IDC with varying finger number
Parameter Values
Total fingers, N (a) 6 [ 1X ]
(b) 12 [ 2X ]
(c) 18 [ 3X ]
Finger width, w 2 mils
Fingers length, l 24 mils
Fingers effective length, l 22 mils

37
Experiment Experiment Setting
4. Combline IDC with varying finger number
Parameter Values
Total fingers, N (a) 6 [ 1X ]
(b) 12 [ 2X ]
(c) 18 [ 3X ]
Fingers width, w 2 mils
Combline fingers width, w 2 mils
Spacing between combline fingers, s 2 mils
Fingers length, l 24 mils
Fingers effective length, l 22 mils
Total Combline fingers per finger, N 3

CHAPTER IV
RESULTS AND DISCUSSION
4.1 Introduction
This chapter presents the simulation results extracted from HFSS for both the
conventional and combline IDC configurations with the four experimental settings
stated in Chapter 3. The computation of capacitance values and Q factor of the IDCs
from the simulation results are also presented. The results presented are then
discussed in depth.
4.2 S- and Z-parameters
This section presents the S- and Z-parameters extracted from HFSS for both
conventional and combline IDCs. These values are used in the later part in the
studies to mathematically compute the capacitance and Q factor based on
formulations presented in Chapter 3. Figure 4.1 shows the simulation models built
in HFSS for experiment 1 as mentioned in Chapter 3 with the assumptions and
settings stated in Table 3.1. Two 50 ohm lumped ports are assigned to the input and
39
output of the models for impedance matching purposes. These models are then
simulated by sweeping the frequency from 1 GHz to 40 GHz with 0.1 GHz
incremental step. Simulation results are shown in Figure 4.2 in the form of return
loss (S11) and insertion loss (S21) responses. The S22 and S12 values are assumed to be
identical to the S11 and S21 measured values since a capacitor is a symmetrical 2-port
device.
(a) (b)
(c) (d)
Figure 4.1: Simulation models in HFSS for conventional IDC with 6 fingers (N=6)
and various effective fingers length, l. (a) Simulation model with 45 view angle.
(b) l = 22 mils [1X], (b) l = 66 mils [3X] and (c) l = 110 mils [5X].
40
Legend:
S11
S21
(a)
Legend:
S11
S21
(b)
Legend:
S11
S21
(c)
Figure 4.2: Simulated return and insertion loss responses for the conventional IDC
with N=6 and increasing finger length from 1X, 3X to 5X simulated from 1 GHz to
40 GHz. (a) l = 22 mils, (b) l = 66 mils and (c) l = 110 mils.
41
From Figure 4.2, it is clearly observed that the slopes of S11 and S21 profiles
change more frequently as the finger length increases from 1X, 3X to 5X. It can be
seen that a dip of S11 = -27 dB occurred at 24 GHz in Figure 4.2(a). Two peaks of
-13 dB and -7 dB appeared at 13 GHz and 38 GHz, respectively. The S21 profile is
seen to be decreasing as the frequency increases. The two profiles cross each other
at 28 GHz when both are of -15 dB. In Figure 4.2(b), the IDC with finger length 3X
longer than the previous model showed that both S11 and S21 have more peaks and
dips, indicating more resonances within the RF range.
The same trend is observed in Figure 4.2(c), where the finger length is 5X
longer than the first model. More resonances appeared. Thus, it can be concluded
that with the same total number of fingers, as fingers length increase, more resonant
present in the same frequency range. This indicates that the capacitor has beneficial
decoupling effects at the self resonant frequencies. As the fingers length increase, it
can be widely used for various applications which operate at different operating
frequencies.
Z-parameter is another parameter that can be extracted from HFSS simulation

for analyzing the capacitor performance. Figure 4.3 shows the normalized
impedance profile for the same experiment as discussed above. The normalized
impedance profile shows the same trend as seen in S11 and S21. With the increment in
finger length, more dips and peaks are observed in the same frequency range.
Besides, the profiles in Figure 4.3 shows repeated rising and falling edges. This
trend matches with the theoretical impedance profile of a capacitor in frequency
domain. The curve sections having negative slope show the frequencies at which the
overall reactance of the capacitor inverts and become inductive in nature due to
resistive losses. On the other hand, the curve sections having positive slope shows
the frequencies at which the overall reactance of the capacitor is capacitive. The dips
are representing the self resonance frequency of the capacitor.
42
100
10
|Im[Zin/50]|
1
0 5 10 15 20 25 30 35 40
0.1
0.01
Freq (GHz)
(a)
10
1
0 5 10 15 20 25 30 35 40
|Im[Zin/50]|
0.1
0.01
Freq (GHz)
(b)
10
1
0 5 10 15 20 25 30 35 40
|Im[Zin/50]|
0.1
0.01
0.001
Freq (GHz)
(c)
Figure 4.3: Normalized impedance profile for conventional IDC with N = 6 and
increasing effective fingers length from 1X, 3X to 5X simulated from 1 GHz to 40
GHz. (a) l = 22 mils, (b) l = 66 mils and (c) l = 110 mils.
43
The same experiment has been done by simulating the modified IDC with
combline structures added to the capacitor fingers. The purpose of adding the sub-
fingers is to increase the coupling effect between the fingers and subsequently
increase the capacitance. The simulation models built in HFSS for experiment 2 as
mentioned in Chapter 3 with the assumptions and settings stated in Table 3.2 are
shown in Figure 4.4. The same approach is used to match the impedance where two
50 ohm lumped ports are assigned at the input and output sections of the model. The
extracted S11 and S21 are shown in Figure 4.5.
(a) (b)
(c) (d)
Figure 4.4: Simulation models in HFSS for combline IDC with 6 fingers (N = 6) and
various effective fingers length, l. (a) Simulation model with 45 view angle. (b) l
= 22 mils [1X], (b) l = 66 mils [3X] and (c) l = 110 mils [5X].
44
Legend:
S11
S21
(a)
Legend:
S11
S21
(b)
Legend:
S11
S21
(c)
Figure 4.5: Simulated return and insertion loss responses for the combline IDC with
N=6 and increasing finger length from 1X, 3X to 5X simulated from 1 GHz to 40
GHz. (a) l = 22 mils, (b) l = 66 mils and (c) l = 110 mils.
45
From Figure 4.5 it is clearly shown that the impact of increasing finger
lengths to S11 and S21 for the combline IDC is similar as the conventional IDC.
Increasing the capacitor finger length results in more resonances appears in both S11
and S21. Besides, looking from another perspective by comparing the S11 and S21
responses of conventional and combline IDC with the same number of fingers and
same finger length, it is noted that the combline IDC has more resonances compared
to conventional IDC. This behaviour is the expected since combline IDC has
additional sub-fingers that caused more coupling between the fingers end. By
considering both graphs in Figures 4.2(a) and 4.5(a) as examples, S11 for
conventional IDC has one dip while S11 for combline IDC has 2 dips in the same
frequency range. This indicates that the combline IDC which has the same attributes
with the conventional IDC can be used in a wider frequency range for more
applications which operate in different operating frequencies. The same trend can be
observed for Figures 4.2(b) and 4.5(b), and Figures 4.2(c) and 4.5(c).
The corresponding normalized impedances for the combline IDC are

computed by dividing the absolute value of imaginary Z11 extracted from HFSS
simulation by 50 ohm. The resulting computations for each capacitor having
different finger length are shown in Figure 4.6. The normalized impedance profile
shows the same trend as seen in S11 and S21 profiles, where with the increment in
finger length, more dips and peaks are observed in the same frequency range.
Besides, it can also be seen that the combline IDC has more resonances than the
conventional IDC within the same frequency range.
46
10
1
0 5 10 15 20 25 30 35 40
|Im[Zin/50]| 0.1
0.01
Freq (GHz)
(a)
10
1
0 5 10 15 20 25 30 35 40
|Im[Zin/50]|
0.1
0.01
Freq (GHz)
(b)
10
1
0 5 10 15 20 25 30 35 40
|Im[Zin/50]|
0.1
0.01
Freq (GHz)
(c)
Figure 4.6: Normalized impedance profile for the combline IDC with N = 6 and
increasing finger length from 1X, 3X to 5X simulated from 1 GHz to 40 GHz. (a) l
= 22 mils, (b) l = 66 mils and (c) l = 110 mils.
47
The next part of the study is to investigate the impact of increasing the
capacitor width by adding total finger number to the capacitor performance. The
following discussion focuses on this topic. Three conventional IDC models with the
same attributes, but maintaining total finger number, are built and simulated using
HFSS. The assumptions are stated in Table 3.3. The models are shown in Figure
4.7 while the extracted S11 and S21 for each case are illustrated in Figure 4.8.
(a) (b)
(c) (d)
Figure 4.7: Simulation models in HFSS for conventional IDC with 22 mils effective
fingers length (l = 22 mils) and various finger numbers, N. (a) Simulation model
with 45 view angle., (b) N = 6 [1X], (c) N = 12 [ 2X] and (c) N = 18 [3X].
48
Legend:
S11
S21
(a)
Legend:
S11
S21
(b)
Legend:
S11
S21
(c)
Figure 4.8: Simulated return loss and insertion loss responses for the conventional
IDC with 22 mils effective finger length (l = 22 mils) and increasing total fingers
from 1X, 2X to 3X simulated from 1GHz to 40 GHz. (a) N = 6. (b) N = 12. (c) N =
18.
49
It can be observed from Figure 4.8 that more resonances occurred as the
width of capacitor increases from 1X, 2X to 3X of the first model. This indicates
that capacitor width did affect the performance of the capacitor. Thus, capacitor
width is one of the factors that can be modified to improve its characteristics.
However, the amplitude delta of increasing the finger length is higher and more
significant compared to finger numbers increment. Despite this, another observation
from Figure 4.8 is that as the capacitor width increases, the first resonance occurred
at a lower frequency. For example, the first resonance observed in Figure 4.8(a) is at
24 GHz while the first resonance observed in Figure 4.8(b) is at 12 GHz and the
subsequent resonances are at 25 GHz and 35 GHz.
The extracted Z11 from HFSS are then normalized and the normalized
impedance profile for conventional IDC with different finger numbers are plotted in
Figure 4.9. The normalized impedance shows similar trend where more resonances
can be observed as the capacitor width increased.
50
100
10
|Im[Zin/50]|
1
0 5 10 15 20 25 30 35 40
0.1
0.01
Freq (GHz)
(a)
10
1
|Im[Zin/50]|
0 10 20 30 40
0.1
0.01
Freq (GHz)
(b)
10
1
0 5 10 15 20 25 30 35 40
|Im[Zin/50]
0.1
0.01
freq (GHz)
(c)
Figure 4.9: Normalized impedance profile for conventional IDC with 22 mils
effective fingers length (l = 22 mils) and increasing total fingers from 1X, 2X to 3X
simulated from 1GHz to 40 GHz. (a) N = 6. (b) N = 12. (c) N = 18.
51
Three combline IDC models with the same attributes but with varying total
finger number are built and simulated using HFSS. The assumptions are stated in the
Table 3.4. The models are shown in Figure 4.10 while the extracted S11 and S21 for
each case are illustrated in Figure 4.11. The normalized impedance profiles are also
illustrated in Figure 4.12.
(a) (b)
(c) (d)
Figure 4.10: Simulation models in HFSS for combline IDC with 22 mils effective
fingers length (l = 22 mils) and various finger numbers, N. (a) Simulation model
with 45 view angle, (b) N = 6, (c) N = 12 and (d) N = 18.
52
Legend:
S11
S21
(a)
Legend:
S11
S21
(b)
Legend:
S11
S21
(c)
Figure 4.11: Simulated return loss and insertion loss responses from 1 GHz to 40
GHz for combline IDC with 22 mils effective finger length (l = 22 mils) and
increasing total fingers. (a) N = 6. (b) N = 12. (c) N = 18.
53
10
1
0 5 10 15 20 25 30 35 40
|Im[Zin/50]|
0.1
0.01
Freq (GHz)
(a)
10
1
0 5 10 15 20 25 30 35 40
|Im[Zin/50]|
0.1
0.01
0.001
Freq (GHz)
(b)
10
1
0 5 10 15 20 25 30 35 40
|Im[Zin/50]|
0.1
0.01
Freq (GHz)
(c)
Figure 4.12: Normalized impedance profile for combline IDC with 22 mils effective
fingers length (l = 22 mils) and various finger numbers, N, (a) N = 6, (b) N = 12 and
(c) N = 18.
54
From Figures 4.11 and 4.12, it can be concluded that the insertion loss, return
loss and impedance profile of combline IDC have the same trend as the conventional
IDC when the capacitor width increases. Nevertheless, the resonances for the
combline IDC is appear more frequent compared to conventional IDC within the
same frequency range. These results are as expected and are attributed by the
presence of additional sub-fingers in the combline IDC cause more coupling
effects compared to the conventional IDC. Thus, impedance varies more as the
frequency increase and thus causes more reflections as a signal passes through the
capacitor. Hence, the return loss and insertion loss vary and resonate more as the
frequency increases.
4.3 Capacitance and Q Factor
From the S- and Z-parameters obtained in Section 4.2, the values are used to
calculate the capacitance and Q factor of the capacitors for performance and
characteristics analysis. This section illustrates the calculated capacitance and Q
factor for each capacitor in the four experiments discussed in Section 4.2. The
capacitances of the capacitor with respect to frequency are calculated based on
Equation 2.5, while the Q factor with respect to frequency are calculated based on
Equation 2.8. The computed relationships are presented in Figures 4.13, 4.15 and
4.16 as the capacitance versus frequency comparison plots for both the conventional
and combline IDCs with various finger length within 1 GHz to 40 GHz frequency
range; and Figures 4.14, 4.16 and 4.18 are the Q factor versus frequency comparison
plots for both the conventional and combline IDCs with various finger length within
1 GHz to 40 GHz frequency range.
55
Capacitance Vs Frequency Trend for Both Conventional and Combline IDC

with 24mils finger and N=6
1E-11
9E-12
8E-12
C apacitance (F) 7E-12
6E-12
Conventional_IDC
5E-12
Combline_IDC
4E-12
3E-12
2E-12
1E-12
0
1 4 7 10 13 16 19 22 25 28 31 34 37 40
Freq (GHz)
Figure 4.13: Capacitance versus frequency trend for both conventional and combline
IDCs with 22 mils effective finger length (l = 22 mils) and 6 fingers (N = 6).
Quality Factor for Conventional and Combline IDC with 24 mils finger and N=6
900
800
700
Q u a l ity F a c to r (Q )
600
500 Conventional IDC
400 Combline IDC
300
200
100
0
1.00E+00 1.00E+01 1.00E+02
Freq (GHz)
Figure 4.14: Q factor versus frequency trend for both the conventional and combline
IDCs with 22 mils effective finger length (l = 22 mils) and 6 fingers (N = 6).
56
In Figure 4.13, it is observed that the conventional IDC has the first
resonance frequency at 14 GHz with 6.69 pF capacitance; and the second resonance
is at 36 GHz with 1.09 pF. At these resonances, the Q factor is 0.8083 and 0.4755,
respectively. With the same attributes, combline IDC has more resonances within
1 GHz to 40 GHz frequency range. Its first resonance occurs at 8 GHz with 9.52 pF
capacitance. The next resonance is at 21 GHz with 6.5 pF capacitance while the third
resonance is at 31 GHz with 3.7 pF capacitance. The corresponding Q factors are
1.0394, 0.105 and 0.0683, respectively. It can be concluded that the combline IDC
has higher capacitance and more resonances compared to conventional IDC in the
same frequency range. Besides, the first resonance frequency for combline IDC is
generally lower compared to conventional IDC. However from Figure 4.14, it is
shown that the Q factor for combline IDC is always lower compared to conventional
IDC at all frequencies. This is due to the higher resistive loss caused by the
additional sub-fingers of the combline structures. Generally, Q factor decrease
exponentially as frequency increase for both conventional and combline IDC.
Table 4.1 summarizes the capacitance values and Q factors for both the
conventional and combline IDCs at the respective resonance frequencies obtained
from Figures 4.13 and 4.14.
Table 4.1: Summary of Capacitance and Q factor for both the conventional and
combline IDCs with 22 mils effective finger length and 6 fingers (N = 6).
Resonance Conventional IDC Combline IDC
Freq Capacitance Q Freq Capacitance Q
1st harmonic 14 GHz 6.69 pF 0.8083 8 GHz 9.52 pF 1.0394
2nd harmonic 36 GHz 1.09 pF 0.4755 21 GHz 6.50 pF 0.1050
3rd harmonic nil nil nil 31 GHz 3.70 pF 0.0683

57
Capacitance Vs Frequency for Both Conventional and Combline IDC with 66 mils finger and N=6
6.00E-12
5.00E-12
4.00E-12
C ap a citace (F )
C_conventional_IDC
3.00E-12
C_combline_IDC
2.00E-12
1.00E-12
0.00E+00
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
Freq (GHz)
Figure 4.15: Capacitance versus frequency trend for both the conventional and
combline IDCs with 66 mils effective finger length (l = 66 mils) and 6 fingers
(N = 6).
Quality Factor for Conventional and Combline IDC with 66mils finger and N=6
500
400
Q u a lity F a c to r (Q )
300
Conventional IDC
200
Combline IDC
100
0
1.00E+00 1.00E+01 1.00E+02
-100
Freq (GHz)
Figure 4.16: Q factor versus frequency trend for both the conventional and
combline IDCs with 66 mils effective finger length (l = 66 mils) and 6 fingers
(N = 6).
58
Figure 4.15 shows the capacitance versus frequency for both the conventional
and combline IDCs with 66 mils effective finger length and 6 fingers. Figure 4.16
shows the corresponding Q factor with respect to frequencies ranges from 1 GHz to
40 GHz. Both plots showed the same trend as the comparison plot for the
conventional and combline IDCs with 22 mils effective finger length. Overall,
combline IDC exhibits higher capacitance and more resonances with a lower first
resonance frequency compared to the conventional IDC. Q factor for combline IDC
is lower across the frequency range compared to conventional IDC. For conventional
IDC with 66 mils effective finger length, four main resonance frequencies are at 6
GHz, 14 GHz, 20 GHz and 30 GHz with corresponding 3.82 pF, 4.21 pF, 1 pF and
2.04 pF capacitances. The Q factors at these frequencies are 3.7637, 0.3523, 0.963
and 0.3783, respectively. As mentioned previously, Q factor decrease exponentially
as frequency increase. Combline IDC in this case has six resonance points, which
are at 4 GHz with 5.38 pF capacitance, 9 GHz with 1.01 pF capacitance, 13 GHz
with 0.8 pF capacitance, 20 GHz with 4 pF capacitance, 30 GHz with 0.56 pF
capacitance and lastly at 36 GHz with 1.37 pF capacitance. Out of the six resonance
points, the highest Q factor is obtained at the first resonant frequency with Q factor
of 4.077. Q decreases exponentially across the frequency range.
Table 4.2 summarizes the capacitance values and Q factors for both the
conventional and combline IDCs at their respective resonance frequencies obtained
from Figures 4.15 and 4.16.
59
Table 4.2: Summary of Capacitance and Q factor for both the conventional and
combline IDCs with 66 mils effective finger length and 6 fingers (N = 6).
3rd harmonic 20 GHz 1.00 pF 0.9630 13 GHz 0.80 pF 1.2864
4th harmonic 30 GHz 2.04 pF 0.3783 20 GHz 4.00 pF 0.2011
5th harmonic nil nil nil 30 GHz 0.56 pF 0.0414
6th harmonic nil nil nil 36 GHz 1.37pF 0.0666
As the effective finger length increases from 66 mils to 110 mils, Figure 4.17
shows its capacitance versus frequency of the conventional and combline IDC while
the Q factor is presented in Figure 4.18. From Figure 4.17, it is clearly shown that
there are more resonances occurred for IDC having 110 mils fingers compared to the
previous IDC with 66 mils fingers. Q factor for this experiment setting is lower
compared to the IDC having 66 mils fingers. In addition, comparison between the
conventional and combline IDCs having 110 mils fingers showed that the combline
IDC possesses lower Q factor. The capacitance and Q factor at resonance frequency
observed in both Figures 4.17 and 4.18 are summarized in Table 4.3.
60
Capacitance Vs Freq for Both Conventional and Combline IDC with 110mils finger and =6
6.00E-12
5.00E-12
C a pa c ita nc e (F) 4.00E-12
Conventional_IDC
3.00E-12
Combline_IDC
2.00E-12
1.00E-12
0.00E+00
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
Freq (GHz)
Figure 4.17: Capacitance versus frequency trend for both conventional and combline
IDC with 110 mils effective finger length (l = 110 mils) and 6 fingers (N = 6).
Quality Factor for Conventional and Combline IDC with 110mils finger and
N=6
300
250
Q u ality F acto r (Q )
200
Conventional IDC
150
Combline IDC
100
50
0
1.00E+00 1.00E+01 1.00E+02
Freq (GHz)
Figure 4.18: Quality factor (Q) versus frequency trend for both conventional and
combline IDC with 110 mils effective finger length (l = 110 mils) and 6 fingers
(N = 6).
61
Table 4.3: Summary of Capacitance and Q factor for both conventional and
combline IDC with 110 mils effective finger length and 6 fingers (N = 6).
3rd harmonic 12 GHz 0.77 pF 1.9746 12 GHz 1.74 pF 0.6556
Next, it is of interest in this context to directly compare the Q factor of the

conventional and combline IDC different dimensions. This is to investigate the
dependency of Q factor on the capacitor dimension. Figure 4.19 shows the Q factor
versus frequency of three conventional IDCs with different finger lengths. Figure
4.20 shows the same parameter of three combline IDCs with different finger length.
Note that for both the conventional and combline IDCs, the Q factor decreases
exponentially as the frequency increases. The average frequency range that has
relatively high Q factor with Q > 50 is at 1 GHz up to approximately 8 GHz
frequency range. Combline IDC exhibits lower Q compared to the conventional
IDC. In Figure 4.19, the maximum Q >700 can be obtained at 1 GHz for
conventional IDC with 22 mils effective finger length. As the effective finger length
increases to 66 mils, the maximum Q factor at 1 GHz dropped to Q450, which is
approximately 36% drop in Q factor. Continue increasing the effective finger length
to 110 mils leads to a significant drop in Q where the maximum Q obtained at 1GHz
is now Q300. This yield almost 57% drop of Q compared to the first model.
62
900
Legend:
800
700 l = 22 mils
l = 66 mils
Q u a l i ty F a c to r (Q )
600
500 l = 110 mils

400
300
200
100
0
1.00E+00 1.00E+01 1.00E+02
Freq (GHz)
Figure 4.19: Comparison of Q factor for conventional IDC with various finger
lengths.
700
Legend:
600
l = 22 mils
500
l = 66 mils
400
Q u a lity F a cto r (Q )
l = 110 mils
300
200
100
0
1.00E+00 1.00E+01 1.00E+02
-100
Freq (GHz)
Figure 4.20: Comparison of Q factor for combline IDC with various finger lengths.
The profiles in Figure 4.20 have the same trend for the combline IDC where
Q dropped not only when frequency increases, but also when the effective finger
length is increased. It is observed that the increment in effective finger length from
22 mils to 66 mils has yield the Q dropped from Q22mils = 580 to Q66mils = 290, which
is equivalent to 50% drop. On the other hand, the increment in effective finger
length from 66 mils to 220 mils has yield the Q dropped from Q66mils = 290 to Q110mils
= 150, which is equivalent to approximately 48% drop.
63
The same comparison can be made between the Q factor of the conventional
IDC with various total finger numbers as well as the combline IDC with various total
finger numbers. The purpose of this comparison is to clearly illustrate the effect of
increasing the capacitor width to its Q factor. The results are shown in Figures 4.21
and 4.22 for the conventional IDC and combline IDCs, respectively.
The maximum Q factor for the conventional IDC with 6 fingers and 22 mils
effective finger length can be obtained at 1 GHz with Q780. This value decreases
exponentially as frequency goes up and then it became close to zero when the
frequency goes higher than 10 GHz. By maintaining the same finger length, another
six fingers are added to the capacitor and thus cause the width to be 2X of the
original model. From the graph, it shows that the Q dropped close to 600, which is
approximately 23% drop. This experiment proceeded by adding another 6 more
fingers to this model and now the capacitor has a total of 18 fingers. The Q factor
again dropped to approximately 400, which is approximately 33% lower than the
second model.
y g
900
Legend:
800
700 N=6
600
N = 12
Quality Factor (Q)
500
N = 18
400
300
200
100
0
1 10 100
-100
Fre q (GHz)
Figure 4.21: Comparison of Q factor for the conventional IDC with various total
finger number, N.
64
700
Legend:
600
N=6
500
N = 12
400
Quality Factor (Q)
N = 18
300
200
100
0
1 10 100
-100
Freq (GHz)
Figure 4.22: Comparison of Q factor for the combline IDC with various total finger
number, N.
Figure 4.22 shows the comparison of Q factor for the combline IDC with
various finger numbers. For the combline IDC with 22 mils effective finger length
and 6 fingers, the highest Q can be obtained at 1 GHz where Q580. This is much
lower compared to the conventional IDC having the same attributes. As the
capacitor width doubled up, Q at 1 GHz dropped to 350 and it continued to drop
when the capacitor width increased to 3X of the original model. The Q factor when
the capacitor has 18 fingers is approximately 180 at 1 GHz. The Q has dropped 40%
as the capacitor width doubled and dropped 69% as the capacitor width becomes 3X
of the original width.
CHAPTER V
CONCLUSION
5.1 Conclusion
Microstrip IDCs are key passive lumped elements, which are widely used in
microwave integrated circuits. The electrical characteristics of IDCs are of interest
over a frequency band, and this has become more crucial as the frequency of most
applications is increasing from Megahertz to Gigahertz range. This thesis presented
an overview of underlying principles of IDC, applications of IDC, and limitations of
the existing IDC. An experimental investigation through simulations on two
attributes of IDC, which are the finger length and capacitor width have been
performed. Besides, a new layout configuration with combline structures has been
explored and simulated.
From the investigations made, it can be concluded that:
Dimension of the IDC regardless of finger length or capacitor width affects

the characteristics of IDC.
Comparing conventional and combline IDC with the same total fingers,
combline IDC demonstrates higher capacitance. However the first self
66
resonance frequency for the combline IDC is lower than that of the
conventional IDC.
As the capacitor effective finger length increase, more resonance frequency

occurs for both conventional and combline IDC within the same frequency
range. Longer finger length has lower first self resonance frequency.
Q factor for combline IDC is always lower than conventional IDC. This is
due to higher resistive loss seen in combline IDC. Q decreases exponentially
with frequency increase. Higher resistive loss is observed in higher
frequency range.
Combline IDC design has improved the capacitance of a conventional IDC at

RF range, albeit slightly lower Q factor. The optimum combline
configuration which achieved useful capacitance with sufficiently high Q
factor is the design with 110 mils effective finger length. It produces 5.48 pF
capacitance at first resonance of 2 GHz with sufficiently high Q = 13.88. This
is a factor of 1.72 higher than the corresponding conventional IDC having
3.18 pF at first resonance of 3 GHz albeit 10 % slightly higher Q factor of
15.41.
5.2 Recommendations for Future Improvement
There are some areas that can be further improved and investigated in order
to obtain a combline IDC with better performance. Since the proposed combline
capacitor managed to achieve a sufficiently high Q due to high resistive substrate
loss, more studies can be done concentrating in low lost substrate material to reduce
resistive loss and increase Q factor. This is important because a capacitor with high
capacitance but low Q is generally not beneficial as most design require high Q
capacitors.
67
This project can also be enhanced with a study to obtain the accurate
electrical model to represent the proposed IDC, so that it can be used in simulations
to accurately represent the behavior of the IDC especially at high frequency region.
Modeling of the proposed IDC is beyond the scope of this thesis.
Studies should be done to look into different capacitor layouts that are able to
produce higher capacitances while having high quality factor. Research can be done
in exploring effect of stack-up (such as coplanar or stripline) to the behavior of IDC.
Figures 5.1 and 5.2 show two different configurations which can be considered.
Figure 5.1: Planar IDC with combline structure and center feeder.
68
Figure 5.2: Coplanar IDC with combline structure and center feeder.
69
REFERENCES
[1] C.-J. Chao, S.-C. Wong, C.-H. Kao, M.-J. Chen, L.-Y. Leu, K.-Y. Chiu,
Characterization and Modeling of On-Chip Spiral Inductors for Si RFICs,
IEEE Transactions on Semiconductor Manufacturing, vol. 15, No. 1,
February 2002, pp. 19-29.
[2] National Semiconductor Corporation, 0.25um CMOS Process Electrical
Design Rules and Characterization Data, May 2001.
[3] TSMC, CMOS RF/ Mixed-Signal 0.25um process design guide, 2000.
[4] Jeffery A. Babcock, et. Al, Analog Characteristics of Metal-Insulator-Metal
Capacitors using PECVD Nitride Dielectrics, IEEE Electron Device
Letters, vol. 22, No. 5, May 2001, pp. 230-232
[5] http://www.eagleware.com/pdf/apps/0009_AccuracyProofMidcap.pdf
[6] J. Kim, J.-O. Plouchartz, N. Zamdmerl, M. Sheronyl, L.-H. Lul, Y. Tan,
M. Yoon, Keith A. Jenkins, M. Kumarl, A. Ray, L. Wagner, 3-Dimensional
Vertical Parallel Plate Capacitors in an SO1 CMOS Technology for
Integrated RF Circuits VLSl Circuits Digest Symposium, 2003.
[7] S. Jenei, S. Decoutere, Stefaan V. Huylenbroeck, G. Vanhorebeek, B.
Nauwelaers, High Q Inductors and Capacitors on Si substrate, IEEE, 2001,
pp. 64-70.
[8] http://www.alaska.net/~natnkell/simplcap.html
[9] J. A. Brandao Fario, Capacitor Modeling at High Frequencies A
Pedagogigal Example of Application of Distributed Circuit Analysis for
Introductory Electromagnetic or Microwave Courses, IEEE Transactions
on Education, vol. 35, No. 3, August 1992, pp. 214-216.
[10] Johanson Technology Corporation, Q and ESR Explained, November 2004.
[11] http://www.ecircuitcenter.com/Circuits/cmodel1/cmodel1.htm
70
[12] Gary D. Alley, Interdigital Capacitors and Their Application to Lumped-

Element Microwave Integrated Circuits, IEEE Transactions on Microwave
Theory and Techniques, vol. 18, No. 12, December 1970, pp. 1028-1033.
[13] F. Aryanfar, Kamal Sarabandi, Characterization of Semi-lumped CPW
Elements for Millimeter-Wave Filter Design, IEEE Transactions on
Microwave Theory and Techniques, vol. 53, No. 4, April 2005, pp. 1288-
1293.
[14] D. Caratelli, R. Cicchetti, A Full-Wave Analysis of Interdigital Capacitors
for Planar Integrated Circuits, IEEE Transactions on Magnetic, vol. 39, No.
3, May 2003. pp. 1598-1601.
[15] R. S. Chen, X. Zhang, K.F. Tsang, K.N. Yung, Modeling and Design of
Interdigital Capacitor Based on Neural Networks and Genetic Algorithm,
Microwave and Optical Technology Letters, vol. 38, No. 3, August 2003. pp.
231-235.
[16] K. G. Ong, J. S. Bitler, C. A.Grimes, Remote Query Resonant-Circuit
Sensors for Monitoring of Bacteria Growth: Application to Food Quality
Control, Sensors, June 2002, pp. 219-232.
[17] W. Young, J. Starck, Series and Parallel Capacitors, Lessons in Electric
Circuits, vol. 1, 2002.
[18] R. Esfandiari, D. W. Maki, M. Siracusa, Design of interdigitated capacitors
and their application to gallium arsenide monolithic filters, IEEE
Transactions on Microwave Theory Technology, vol. 31, No. 1, 1983, pp.
57-64.
[19] S. G. Spartak, M.Torten, L. J. L. Peter, L. K. Erik, CAD Model for
Multilayered Substrate Interdigital Capacitors, IEEE Transactions on
Microwave Theory and Techniques, vol. 44, No. 6, June 1996, pp. 896-904.
[20] L. Yu, S. N. Amit, G. E. Erich, R. T. Troy, S. James, A. Y. Robert,
BaSrTiO3 Interdigitated Capacitors for Distributed Phase Shift
Applications, IEEE Microwave and Guided Wave Letters, vol. 10, No. 11,
November 2000, pp. 448-450.
[21] L. H. John, Optimization of Interdigital Capacitors, IEEE Transactions on
Microwave Theory and Techniques, vol. MTT-27, No. 9, September 1979,
pp. 788-791.

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PSZ 19:16 (Pind.

BORANG PENGESAHAN STATUS TESISi

SESI PENGAJIAN : 2005/2006-2

LIM YUN ROU

mengaku membenarkan tesis (PSM/Sarjana/Doktor Falsafah)* ini disimpan di Perpustakaan

1. Tesis adalah hakmilik Universiti Teknologi Malaysia.

SULIT (Mengandsungi maklumat yang berdarjah keselamatan atau

TERHAD (Mengandungi maklumat yang TERHAD yang telah ditentukan

(TANDATANGAN PENULIS) (TANDATANGAN PENYELIA)

Tarikh: 29th. April 2006 Tarikh: 29th. April 2006

CATATAN: * Potong yang tidak berkenaan.

LIM YUN ROU

A project report submitted in fulfilment of the

Faculty of Electrical Engineering

I declared that this project report entitled

My supervisor, Associate Professor Dr. Mazlina Esa for her valuable

My friends for their continuous suggestion and encouragement from the

Finally, I would like to dedicate my appreciation to my family for their

Technology advances in complimentary-metal-oxide-silicon (CMOS) process

Kecanggihan teknologi pemprosesan silikon-oksida-logam-pelengkap

TABLE OF CONTENTS vii

LIST OF SYMBOLS xvi

LIST OF ABBREVIATIONS xvii

1.1 Background of Study 1

1.2 Goals and Limitations of On-chip Capacitor 4

1.4 Scope of Project 6

1.5 Project Outline 7

CHAPTER II LITERATURE REVIEW 9

2.1 Basic capacitor at High Frequency 9

2.2 Capacitor Parameters and Model 13

2.3 Interdigital Capacitor (IDC) 15

CHAPTER III METHODOLODY 24

3.2 Overall Project Flow 24

3.3 Implementation and Simulation of IDC with

3.3.1 Layout of IDC with Combline Structure 26

3.3.2 Combline Structures as Capacitors with

3.3.3 Simulation of Conventional and Combline

CHAPTER IV RESULTS AND DISCUSSION 38

4.2 S- and Z-parameters 38

4.3 Capacitance and Q Factor 54

5.2 Recommendations for Future Improvement 66

TABLE NO. TITLE PAGE

2.1 Capacitor behavior with respect to frequency range. 14

3.1 Settings and parameter assumptions in HFSS simulation

3.2 Settings and parameter assumptions in HFSS simulation

3.3 Settings and parameter assumptions in HFSS simulation

3.4 Settings and parameter assumptions in HFSS simulation

4.1 Summary of Capacitance and Q factor for both

4.2 Summary of Capacitance and Q factor for both

4.3 Summary of Capacitance and Q factor for both

FIGURE NO. TITLE PAGE

1.2 IDC configurations (a) basic, (b) six fingers. 6

2.1 Basic capacitor. (a)Two thin plate conductors with fixed

2.2 System configuration consisting of two parallel plates in

2.3 Plots of the device susceptance against frequency for

2.4 Series RLC network representing behavior of a simple

2.5 Conventional interdigital capacitor layout, (a) Cross

2.6 Interdigital capacitor in Gary D. Alley study and its low

2.7 Coplanar interdigital capacitor. (a) Layout, (b) Circuit

2.8 Series capacitance of coplanar interdigital capacitor with

2.9 An IDC structure having zig-zag fingers. Structure

2.10 Comparison of magnitude of S-parameter versus

2.11 Equivalent circuit for the IDC structure with zig-zag