Subramanya Hegde

FPGA Engineer/Embedded Hardware and Software

subramanya.mhegde@gmail.com

Summary
Currently working as a Design Verification Engineer at Xilinx Inc.

Motivated self-starter with a strong background on FPGA tools and flows.

Specialities include :
1.) End to End FPGA flow from Design Entry to Board Level Validation.
2.) Embedded Microprocessor flows involving embedded harware and software projects verified on FPGA test
boards.
3.) System level design creation and debug with various Xilinx IPs.
4.) High Level Synthesis using C
5.) Test Plan Creation followed by comprehensive testing including systematic testing, automation testing,
exploratory testing and brute force testing.
6.) Creation of Utilities using TCl scripting that help automation and debug of different flows.
7.) Analyze back end flows including Timing, Place and Route for complex FPGA Designs

Experience
Design Solutions Verification Engineer at Xilinx
January 2014 - Present (3 years 1 month)
Responsible for testing Xilinxs Vivado IDE by creating system level designs to validate Synthesis,
Implementation, Partial Reconfiguration, Debug, IP Packaging, ECO, Embedded Software flows and the
GUI.
Performed Timing closure on critical paths and constrained designs to optimize Performance, Area and
Power.
Created designs using High level synthesis for high speed communication using PCIE and Ethenet IP
Created Utilities using TCl scripting that helped in automation and debug of different flows like Routing,
ECO and Embedded Processor flows.

Hardware Engineer II at Cisco Systems

June 2013 - December 2013 (7 months)
Worked on verification of Security Module for next generation Ethernet Switch ASIC. Flow includes
Encryption, Decryption and Authentication of L2, L3 and L4 packets. Environment in C++

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 Developed a verification Environment of Supervisor Module that performs register and memory reads and
writes and interrupt handling of all the modules of the ASIC. Primary communication interface between CPU
and ASIC through PCIe. Environment written in System Verilog.
Worked on full-chip register and memory read/write tests, both back-door and front-door, to verify complete
accessibility of all modules in the ASIC. Wrote snippets of code to automate the tests and run regression
using make files.

Teaching Associate at San Jose State University

January 2013 - May 2013 (5 months)
Teaching Associate for Digital Design Lab at Department of Electrical Engineering, San Jose State
University. :
Taught Digital Logic Design using Verilog HDL and Schematic Modeling using Xilinx ISE 14.2 tool
Developed intermediate to complex logic circuits on breadboard followed by analysis of performance
metrics such as gate count and propagation delay based on their electrical and timing characteristics
Implemented logic design operations on Xilinx Spartan 3 XC3S200 FPGA

Computer Vision/Machine Learning Intern at Gen-9 Inc.

June 2012 - August 2012 (3 months)
Developed programs in C for depth sensors like Kinect and Kinect-like devices, in accordance with the
research protocol and goals (mainly for medical-related applications).
Integrated various open source libraries like OpenNI and OpenCV to implement real time object tracking.
Objects included a simple pendulum, double pendulum and a wheeled robot.
Developed and optimized programs to track the motion of objects on a wheeled telepresence robot.

Education
San Jose State University
Master of Science (MS), MSEE Digital Design, 2011 - 2013
Activities and Societies: Institute of Electrical and Electronic Engineers (IEEE) Association for Computing
Machinery (ACM)
Visvesvaraya Technological University
Bachelor of Engineering (BE), Electrical, Electronics and Communications Engineering, 2006 - 2010
Activities and Societies: Institute of Electrical and Electronic Engineers (IEEE) The Institution of Electronics
and Telecommunication Engineers (IETE) Association for Computing Machinery (ACM)

Certifications
C-based Design: High-Level Synthesis with the Vivado HLx Tool
Xilinx November 2015
Introduction to Programming with MATLAB
Coursera Course Certificates License 8QH2GSYE5T June 2015
Vivado Design Suite Advanced XDC and Static Timing Analysis

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Xilinx March 2015
System Verilog for Verification
Synopsys Inc July 2013
System Verilog Assertions
Synopsys Inc July 2013
Learn to Program: The Fundamentals
Coursera December 2012

Projects
Real Time Disparity Map Generation on FPGA with Software Implementation
August 2012 to May 2013
Members:Subramanya Hegde
Implemented a stereo vision algorithm that generates a disparity map on a low cost Xilinx Spartan 6 FPGA
with a stereo camera module and optimized the speed, with highest achievable frame rate.
Developed a software prototype of the design using two cameras using OpenCV and Matlab.
Developed a depth detection algorithm using a Microsoft Kinect Depth sensor, that provides ground truth
verification of the above two prototypes. Used C, OpenCV and OpenNI, for the development.
Tools used : OpenCV, Matlab, VHDL, Xilinx ISE, Microblaze
Verification of a 64-point FFT Design using System Verilog
November 2012 to December 2012
Members:Subramanya Hegde, Adarsh Bhupalam
Verification of a 64 point FFT design created by the design team.
Implementation of a Driver, Monitor and Checker using System Verilog to carry out verification
Included Coverage to verify complete coverage of all the test cases
Tools Used : Synopsys VCS, Modelsim
A Single-Precision Floating-Point Addition Unit
March 2012 to May 2012
Members:Subramanya Hegde
Designed an IEEE754 standard 32-bit single-precision floating-point addition unit using Verilog HDL.
Includes RTL design, simulation, synthesis using tc240c library at 100MHZ, logic and timing verification,
gate level simulation. Synthesis performed both at RTL and netlist level.
Tools used : Synopsys VCS, Modelsim, Design Vision
Embedded control I2C controller with a ring bus interface
April 2012 to May 2012
Members:Subramanya Hegde, Rajesh Reddy, Kinshuk Sharma
Design of a novel ring bus with 32 bits/cycle (low speed version) used to communicate with the I2C device
followed by simulation and synthesis.
A test bench is provided which generates random test values which are used to communicate with the I2C
device. The frequency of operation is 300MHz
Tools used : Synopsys VCS, Iverilog, NC Verilog, Design Vision

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Speed optimization of a circle co-ordinate generator using pipelining
February 2012 to February 2012
Members:Subramanya Hegde
Increased the clock speed of a circle co-ordinate generator from 2 MHz to 300 MHz by 48 stages of
pipelining.
Used verilog for RTL design and verified the same using synopsis VCS, NC Verilog and IVerilog.
Synthesis & static timing analysis carried out in Design Vision, post synthesis and dynamic timing analysis
in VCS. Perl Script was used to carry out the verification.
Tools Used : Synopsys VCS, Design Vision, Iverilog, NCVerilog
Implementation of a Keypad Controller with a built-in FIFO
March 2012 to March 2012
Members:Subramanya Hegde
Implemented a FIFO to synchronize the speed of a fast input device (4 X 4 Keypad) and slower output
device (7 Segment Display).
The FIFO implemented was circular in nature with a size of 1024 X 4 bits.
Tools used : Iverilog, Design Vision
Vision System For Pick and Place Robot
January 2009 to June 2010
Members:Subramanya Hegde, Sid Hegde, Venkatesh G M, Sindhu Priya
Worked in a team of four to develop an intelligent algorithm for a Vision System consisting of two phases
namely, The Learning Phase and The Identification Phase.
Developed the code for Vision System using VC++ and successfully interfaced the hardware and
successfully interfaced the Vision System to a Pick and Place Robot and ensured complete working of the
system.
Tools used : VC++

Skills & Expertise

Digital Design
Verilog
System Verilog
Synopsys VCS
Design Vision
Silos
ModelSim
Cadence Encounter
Xilinx ISE
Altera Quartus
Matlab
C
C++
Visual C++

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Perl
OpenCV
OpenNI
Windows
Ubuntu
MS Office Suite
Open Office
Simulink
OVM
UVM
SystemVerilog
Python
Synopsys tools
Microsoft Office
Logic Design
Cadence
Integrated Circuit Design
ASIC
FPGA
Field-Programmable Gate Arrays (FPGA)

Publications
Vision System for Pick and Place Robot
Second National Conference on Emerging Trends In Control, Communication, Signal Processing & VLSI
Techniques - CCSV 2010, The Oxford College of Engineering, Bangalore April 21, 2010
Authors: Subramanya Hegde, Sid Hegde, Venkatesh G M, Sindhu Priya
The paper describes a machine vision system that can recognise a variety of objects. It consists of two phases
namely The Learning Phase and The Identification Phase.

The learning phase is an offline phase which learns the objects and stores the required parameters in a
model base. The algorithm makes use of features that are invariant to translation, scaling and rotation of an
object. We then generate a binary interpretation tree using the extracted features. The use of timing analysis
generates the tree in the minimum time using the features that take the least time of computation, further
optimising the algorithm.

The identification phase is an online phase that takes an unknown object and identifies it using the model
base generated during the learning phase. In this algorithm, at each node the feature is extracted from the
unknown object image in correspondence to the nodes of the interpretation tree to speed up the process of
identification. This phase takes only one fourth of the time taken by the learning phase.

Courses
Master of Science (MS), MSEE Digital Design

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San Jose State University
Advanced Digital System Design and Synthesis EE 271
SoC Design and Verification with System Verilog EE 272
ASIC CMOS Design EE 287
Digital Design for DSP & Communications EE 278
Digital Signal Processing I EE253

Bachelor of Engineering (BE), Electrical,

Electronics and Communications Engineering
Visvesvaraya Technological University
Logic Design
Fundamentals of HDL
Fundamentals of CMOS VLSI
Digital Signal Processing
Digital Image Processing

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Teaching Associate
San Jose State University
Digital Design Lab EE 118 Lab

Languages
English (Native or bilingual proficiency)
Kannada (Native or bilingual proficiency)
Hindi (Native or bilingual proficiency)
Sanskrit (Limited working proficiency)

Interests
Online Research, New Technologies, Robotics, Web Hosting, Website Template Customization, Philately

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Subramanya Hegde
FPGA Engineer/Embedded Hardware and Software
subramanya.mhegde@gmail.com

Contact Subramanya on LinkedIn

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