International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 7 (2016) pp 4922-4929

Research India Publications. http://www.ripublication.com

Review of Tunnel Field Effect Transistor (TFET)

Satish M Turkane
Research Scholar, Department of Electronics & Telecommunication,
Matoshri College of Engineering & Research Centre, Nashik,
Savitribai Phule Pune University, Pune, Maharashtra, India.

A. K. Kureshi
Principal, Vishwabharti Academys College of Engineering, Ahmednagar,
Savitribai Phule Pune University, Pune, Maharashtra, India.

Abstract Ultra-low power and ultra-low voltage.

An upcoming emerging device type of transistor is the TFET
that is Tunnel Field Effect transistors. MOSFET (Metal Oxide
Semiconductor Field Effect Transistors) is generally used for
low energy usable electronics devices. The structure of TFET
is approximately closer to MOSFET, however with different
fundamental switching mechanism. Switching of TFET is
done by modulating quantum tunneling through a barrier
instead of modulating thermionic emission over a barrier as in
traditional MOSFETs. The purpose of this paper is to do
Survey of TFET from its initial stage to till today. This paper
studies and reviews various types of TFET available for
design. Surface Tunnel Transistor is first tunnel transistor
deals with speed, power and IOFF/ION ratio. Then first TFET
basic p-i-n structure is invented which deals with speed,
power, IOFF/ION, tuning range etc. After that feedback TFET,
p-n-i-n TFET, NEMFET, Raised Buried Oxide TFET,
Junctionless TFET, Double gate TFET (DG-TFET), Vertical
TFET, Dopingless PNPN TFET are studied. Along with these
different structures of TFET DG-TFET, Dopingless PNPN
TFET and Vertical DG-TFET shows superior performance
than other studied.
Keywords:TFET; MOSFET; Surface tunnel transistor; DG-
TFET; Junctionless TFET; Dopingless PNPN TFET;
Protection; LVTSCR (Low-Voltage Trigger SCR).
Introduction
MOSFET had played a vital role in building most of the
integrated circuits while minimizing its size over the half
decade of century in the past by way of scaling its size to
nano-meters as of today. Reduction in the size of MOSFET
decade by decade, the integrated circuits build on it worked
faster at reduced power then their earlier counterparts [1].
Scaling down of the MOSFET for the sake of reducing the
power density resulted into reduction in the operating supply
voltage as well.
Tunnel Transistor has been evolved in 1992 by T. Baba, as
one of the promising alternatives to the conventional
MOSFETs based on various performance parameters as
mentioned bellows:
Potential for exceeding the 60mV/decade sub-
threshold swing.
Short Channel Effects.
Reduction in the leakage currents.
Exceeding the Speed requirements due to tunneling
effects.
Ability to work on sub-threshold and super-threshold
voltage.
Similarity in fabrication process as compared with
MOSFET.
Higher IOFF/ION current ratio [2].
Taking into consideration the above parameters, the MOSFET
could be replaced by a potential substitute in terms of TFET
for the purpose of high speed, ultra-low power, and energy
efficient applications in the domain of integrated circuits [2].
In this paper, we have accumulated and studied different
designs of TFET from its inception in year 1992 to till May,
2015 with a brief introduction scaling of MOSFET and
elaborated the exceeding performance of TFET with its
conventional counterpart MOSFET. Section II provides a
detail literature survey about TFET. Section III is dedicated to
the TFET device physics and operation. Section IV highlights
the different structures of TFET like feedback TFET, p-n-i-n
TFET, NEMFET, Raised Buried Oxide TFET, Junctionless
TFET, Double gate TFET(DG-TFET), Vertical TFET,
Dopingless PNPN TFET are studied. The design parameters
which have been developed in year 2015 have been explored
to a maximum extent. Section V makes a conclusion.
Literature Review
The scaling of the MOSFET has various bottlenecks in terms
of its ability to work in ultra-low power, leakage currents,
short Channel Effects (SCE), speed improvements etc. had led
to limitation of the performance of MOSFET. Maintaining
intact the electric fields while scaling down the MOSFET the
channel length (Lg) and oxide thickness (tox) are scaled by
1/K while the substrate doping is scaled up by K, where K is a
scalar constant. The aforementioned dimension scaling will
enable the applied voltage to be scaled by 1/K. This type of
scaling is known as R. Dennard scaling [3].
For modern devices, R. Dennard scaling doesn't work as it
used to be in the past. The reason can be explained using
Fig.1. The figure shows the variation in supply voltage (VDD)

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Research India Publications. http://www.ripublication.com
and threshold voltage (VT). Where VT is a function of
channel length (Lg) [3]. As can be seen, as the channel length
reduces below 0. 35 um the linear dependencies between
VDD and VT is no longer linear. For example, as if we reduce
initial value of VDD up to 1/5th then VT reduces to 50% of its
initial value [4].
Figure 1: The plot of technology generation Vs voltage (i. e.
supply voltage and threshold voltage) where reduction of VT
is quite less but reduction of VDD is occur with respect to
device parameters [5].
The most important consequence of scaling is that the gate
overdrive voltage (VGS-VT equivalent to VDD-VT) remains
almost constant for advanced technology nodes (short channel
lengths). When gate overdrive voltage decreases, the on-
current decreases, which negatively affects device
performances such as ION/IOFF ratio and dynamic speed
(CVDD/Ion). There are two possible solutions to this problem
of low on-current of advanced technology nodes, (a) Increase
VDD (b) Reduce VT [4].
Increasing VDD
For an inverter, the dynamic power consumption [6] can be
expressed in (1)
Pdynamic = f CL VDD2 (1)
Where f is the frequency of operation and CL is the capacitive
load.
As can be seen, with increase in VDD the dynamic loss in the
gate inverter increases. Similarly, the static power
consumption [6] is given by (2)
Pleakage = Ileak VDD (2)
Where Ileak is switch off leakage current of MOSFET in the
device structure. It is clear from the above expressions that
both static and dynamic power loss of the devices increases as
a function of supply voltage (VDD).
Reduce VT
Second option for keeping the high gate overdrive is to scale
down VT. For an average 60 mV/decade reduction in VT, the
off-current (IOFF) or sub-threshold current increase by 10 times
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of its initial value which results in increase in leakage power
[4].
Now as technology is scaled down up to nanometers,
transistors count per unit chip area increases therefore its
leakage power constraints are also increases. Due to this its
standby power consumption in the device is also gets
increases. The decrease in the VT is not the proper solution
from the above discussion [4].
In order to solve these issues, recent literatures have proposed
Tunnel FETs (TFETs). The advantages of TFET are low sub-
threshold current which leads to low leakage per device and
its high ION/IOFF ratio can be suitable for memory application,
etc. As discussed above there are limitations with VDD and VT
scaling. Fig. 2 represents the changes of leakage energy (EL)
and dynamic energy (EDYN) with supply voltage VDD for both
MOSFET and TFET [7].
Figure 2: Showing EDYN and EL variations with supply
voltage VDD, Energy dissipation is lower for lower SS devices
(TFET) [7].
The expression for (EDYN) and (EL) are as given below [7]:
EDYN VDD2 (3)
EL / V DD 2 10(-VDD/SS) (4)
Where SS is the sub-threshold slope of the TFET. Equations
(3) and (4) states that for MOSFETs, both leakage and
2
dynamic energy are proportional to . However, leakage
energy also has an additional exponential dependence on SS.
Equation (4) shows that lower the sub-threshold slope lower
will be the EL [8]. As mentioned before, changing VDD, affects
the device performance. Therefore, one way is to find a device
with lower sub-threshold slope (SS < 60 mV/dec). TFET
exhibits these characteristics. Therefore, at lower voltages
(VDD), TFET exhibits lower ET (Total energy = EL + EDYN)
compared to a MOSFET [4].
The TFET follows band-to-band tunneling mechanism with
the quantum-mechanical generation of carriers. Scaling of a
gate length in the MOSFET, it shows short channel effects for
a span of higher number of the electron wave-length. TFET is
 International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 7 (2016) pp 4922-4929
Research India Publications. http://www.ripublication.com

highly compatible for standard CMOS process flow. For junction electric field on the gate-source voltage should be
TFET optimization of the doping profile and better control of maximized [4].
one mask are important factors but these are not important for
the CMOS flow [9]. Therefore, TFET is an emerging Different Structures of TFET
alternative type for next scaling of the gate length however
which is not affected by short channel effects [10]. As the
device structure of TFET is decreased then its static power
consumption is gets reduced ultimately [9].
In the ON state of TFET, the carriers tunnel through the
barrier which is band gap between valence band and
conduction band for the flow of current from drain-to-source.
Whereas in OFF state, available barrier maintains off current
magnitude lower than that of off current magnitude of the
conventional MOSFET. The inherent properties of TFETs
make them suitable for low power digital applications [4].

TFET Device Physics and Operation

Band to Band Tunneling (BTBT)
This phenomenon provides an expression for the tunneling Figure 3: Evaluation of Tunnel Field Effect Transistor.
transmission of carriers and can be achieve by Wentzel,
Kramers and Brillouin (WKB) approximation and A. Surface Tunnel Transistors (1992-2000)
considering the tunnel barrier as a triangular shaped potential Toshio Baba presented the surface tunnel transistor (STT)
barrier. According to WKB approximation, which was a new type of tunnel device which could operate
4 2. 3 normally even in very small structures with gate lengths of
2
exp [ . ( ) ] (5)
3 less than 0.1m at room temperature. The STT consists of an
n+/i/p+ diode structure with an insulated gate in the i-region.
Equation (5) is a common way to express BTBT transmission. Highly degenerated drain had a sharp doping profile for a low
Here -the electron effective mass, -Planck's constant doped substrate and makes a tunnel junction with the 2D
divided by 22, Eg is the band gap of the semiconductor electron channel under the gate. The STTs were fabricated
material at the tunnel junction, and F is the electric field using a GaAs/AlGaAs Heterojunction in order to study the
measured in V/m. This equation can be improved slightly by basic characteristics of this new device. Their current-voltage
making it more specific to tunneling transitory [10]. There are characteristics exhibited transistor action without saturation
four important conditions in order for band-to-band tunneling characteristics in the drain current similar to a vacuum triode
to take place: operation. These characteristics of STTs were anticipated by
1. Available states to tunnel-from, the theory of interband tunneling [13].
2. Available states to tunnel-to,
3. An energy barrier that is sufficiently narrow for
tunneling to take place and
4. Conservation of momentum [11].

Subthreshold swing in Tunnel FETs

In order to describe the expression for the sub-threshold swing
of a BTBT device, consider the BTBT current is given below
[11-12] for reverse-biased p-n junction:

= (6)

Where
2.

3
= (7)
2 2

Where A is the device cross sectional area and

3
2
= 4 . (8)
3

Accordingly, the sub-threshold swing in a TFET increases

with gate-source voltage and much steeper at lower gate
voltages. The second term describes that the derivative of the
a. Thermal equilibrium

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peak-to-valley ratio of 5 and higher current tunneling densities

than GaAs MJ-STTs that is 500-times [15].

B. Basic p-i-n structure (2004)

Toshio baba proposed tunnel FET (TFET) with the aim of
steep swing in 2004 [13]. This device structure is having
similarity to Lubistor. It requires higher doping levels and
source/drain junction to be abrupt. The TFET works like
reverse biased PN diode, where the insulated gate controls the
tunneling [16].

b. Weak carrier accumulation

(a)

(b)

Figure 5: (a) Device structure of TFET, (b) band diagram of

c. Strong carrier accumulation TFET [16].
Figure 4 (a,b,c): Schematic cross section of an STT and band Bhuwalka et al. predict that after their simulation if the gate
diagram at the semiconductor surfaces [13]. oxide gets broader then it will increase a SS. Addition of a
+ layer adjacent to the + terminal, it improves the electric
Fig. 4a shows cross sectional view of the proposed STTs field in between i-to-+ . Proposed SS formula is given by
which consists of a drain, a source and an insulated gate. [16]:
Although the STT structure is match to Si-MOSFET or ln(10).2
HEMT, the doping polarity of the drain terminal is different = 3
(9)
2
from the source terminal. This is an important difference from 2+

conventional FETs. These are crucial factors for STT Where BKane and D are the constants. Equation (9) shows that
operation [13]. As surface tunnel transistor is already for sharp swing VG should be low as possible [16]. By
proposed and then it developed as a new NDR device for high considering ID with BTBT current (IBTBT), by simplifying
performance with GaAs and InGaAs materials [14]. BTBT current equation we get equation (9). (Igen) is the semi-
Then new STTs were proposed as MJ-STTs (multiple- classical thermal generation current around the junction of
junction surface tunnel transistors). To increase its semiconductor devices which are operating at room
functionality, in its structure source, gated n+/p+ tunnel- temperature [16]:
junctions and drain are connected in series respectively. MJ- EID= IBTBT +Igen (10)
STTs have improved in-terms of the characteristics with
added logics for multiple-valued circuits. For 6 successive When IBTBT>Igen, Equation (10) gets the equation for the swing
NDR characteristics of transistors operations were accurately value [16]:
demonstrate with InGaAs based MJ-STTs also it has high

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(11) E. Raised Buried Oxide Tunnel FET (2012)
1+ ( ) The flow of current in the tunnel FET depends on tunneling

probability. As it has a disadvantage of ION in large band gap
silicon is lower, so Raised Buried Oxide TFET is designed.
As device is operating at room temperature ( )takes a
Non equilibrium Greens function formalism is used for the

negative value then we get >STunnel,
which is an quantum capacitance determination. A heterogate oxide and
intrinsic disadvantage of the structure. Also we can say that on SOI structure with Raised Buried Oxide in drain is proposed
the purity of tunneling process a sharp swing is depend. Based to achieve ITRS requirement and reduced Miller capacitances.
on the gate voltage polarity, one of the issues of TFET which For reduction of parasitic bipolar current and increment of
rises is about the gate-induced transversal field which current heterogate dielectric structure is used. This proposed
increases/decreases the reverse-biased tunnel of the junction structure is used to achieve:
[16]. Maximum ION,
For TFET, if gate bias is applied then it works as a reverse Minimum IOFF,
biased pin-diode which is an advantage of the TFET. Purity of Maximum ION/ IOFF ratio,
the surface defines the static leakage current of the diode and Minimum SS and
diode reduces it by 2x of magnitude [17]. But it also has a
Reduced Miller capacitance effect.
limitation that its sharp swing is present for very thin gate
voltage range, at least up to now [16].
A low band gap material improves the tunneling probability
like Ge. Hence it has maximum ION (>1mA),
C. Feedback FET (2008)
transconductance (gm), output conductance, and dynamic
Alvaro Padilla et al. proposed the feedback FET which is
power consumption (Pdynamic) of 0. 067X10-5 watt achieved at
designed to achieve a steep swing. Its device structure is
109 ION/IOFF ratio and significantly improved overshoot and
closer to Lubistor; but it has under lapped gate electrode. It
undershoots with respect to conventional TFET. Therefore,
has gate side walls for energy barrier purpose for electrons
RBO Tunnel FET is widely used for ultra-low power digital
around n+-i junction (source junction) and for holes i-p+
applications [19].
junction (drain junction). As positive gate voltage is applied
at the source and drain junction near the gate sidewalls, some
F. Junctionless TFET (2013)
holes and electrons are trapped which lowers the potential of
The proposed JL-TFET is a Si-channel heavily n-type-doped
holes and electrons near the drain and source junction
with different isolated gates (Control-Gate, P-Gate) with
respectively. Due to this sudden decrement of barrier height
different work-functions. This is because of JL-TFET should
and an abrupt SS (~2mV/decade) occurs [16].
be similar to conventional TFET.
For transition of the OFF state to ON state it requires gate side
The subthreshold swing of JL-TFETs is lower than
wall insulator to be charged. It however not a disadvantage of
60mV/decade. These are actually quantum mechanical
the proposed device, but has some issues like:
devices which are based on band-to-band tunneling (BTBT)
1. The VT on the forward sweep and on the reverse
principle. It has higher electrical performance but lower
sweep is different.
variability than MOSFET. This happens due to absence of p-n
2. The VT always depends on the VD [16].
junctions. JL-TFET is mostly attractive because of better
tunneling current and low band-gap hetero structure channel
D. p-n-i-n TFET (2011)
[20].
Wei Cao proposed a new structure which is basically a
conventional TFET with a narrow n-layer at the tunneling
F-1. Asymmetric Junctionless
junction. It has two main advantages like higher ION and lower
For efficient ON-OFF switching, source and drain are
SS with respect to the conventional TFET. Its IV
optimized by using the asymmetric junctionless source/body
characteristics and reliability are assured. Recent researches
region and junctional drain/body region separately. Due to n-
note that reliability issue is one of the major hurdles for
drain/p+body junction, the off-state tunnel barrier can be
TFET. It happens due to near tunneling junction at the
extended into the drain due to drain/body junction. Therefore,
channel/dielectric interface, where there is strong electric field
AJ-TFET is an alternative approach for sub-10-nm region
in parallel and antiparallel directions [18].
[21].
The j (E) is tunneling current density is given by the nonlocal
model for the BTBT [18], i. e.
G. Double gate TFET (DG-TFET) (2008-2015)
j (E) = T(E)f(Ef1, Efr)E (12)
The DG-TFET has an added gate which improves or doubled
the current. Due to that its On current gets boosted and OFF
Here -constant, T(E)-tunneling coefficient depended on
current gets in the range of fempto amperes or Pico amperes
energy, f(Ef1, Efr)-state occupation factor function of quasi-
or it can be increases by some factor but remains extremely
Fermi levels at the two different tunneling junction. E-
low. It is a lateral n-type TFET in narrow silicon layer. The
energy range. The thin n-pocket increases the tunneling field
separation of this device layer from substrate is done by using
Ey. The increment is higher at center of body (x = Tsi/2) than
dielectric material layer. In between intrinsic and p+ region
that of the surface of Si (x = 0. 1 nm). Thus changing in
tunneling take place [22].
device process, the sensitivity of the TFET characteristics may
get improved [18].

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G-1. Dual Material DG-TFET Subthreshold Swing in upcoming days will be highly
Rajat Vishnoi et al. proposed a double material gate TFET important parameter. So we can consider that Vertical TFET
(DMG) [23]. It has lower work function for tunneling gate is useful for obtaining maximum ION/IOFF ratio. This can be
than auxiliary gate for a n-channel TFET and higher than useful for Si based devices, also could be applied to scaled
auxiliary gate for a p-channel TFET [32]. It has maximum ION devices which follow Moore's law [24].
and minimum IOFF and SS with reduced drain saturation
voltage [23]. I. Dopingless PNPN TFET (2013-2015)
I-1. PNPN TFET
G-2. Triple Metal DG-TFET In this semiconductor device gate controls, the BTBT
The main aim of the selection of three metals with different tunneling current between source and channel using
work function is to increase ON current and make a barrier in modulation due to extra n pocket. For the removal kink effect
the channel, due to that its OFF current gets reduced. The in PNPN TFET the silicon film thickness optimized [25].
surface potential ( ()) under different metals and the The PNPN Tunnel Structure (Fig. 6) has a tunneling junction
electric fields ( (), ()) (lateral and vertical electric formed in between the p+ source and fully depleted thin n-
field respectively) are calculated for the tunneling current layer (n-pocket) in the gate. It helps in the reduction of
value using 2-D Poissons equation and Kanes model. tunneling width and it creates local band bending. Addition of
The surface potential under different metals is expressed as: thin n pocket region improves the tunneling rate, improves
subthreshold and with the same instant of time gives
1 () = () + () 1 (13)
maximum ION with respect to conventional design of TFET
0 1 1
[25].
2 () = (( 1))

+ (( 1)) 2 (14)
1 (1 + 2) 2
3 () = (( 1 2))

(( 1 2)) 3 (15)
(1 + 2) 3
The expression for Electric Field is,
Figure 6: PNPN Tunnel Structure [26].
For Lateral Electric Field-
(,)
1 () = 1 | = () + ()
=0
Table I: Comparative analysis of PNPN TFET and Conv.
(16)
TFET [25]
0 1
2 (, )
2 () = | Lg PNPN TFET Conventional TFET
=0 (nm) Ron SS Ion/ Ron SS Ion/
= (( 1)) (K/m) (mV/dec) Ioff (K/m) (mV/dec) Ioff
+ (( 1)) (17) 30 42.6 53.1 108 64.1 93.2 105
1 (1 + 2)2 35 46.1 55.3 4107 61.2 90 105
3 (, )
3 () = | 40 48 62 6107 60 91.2 0.1106
=0 45 48.5 65.6 4.2107 58.6 91 0.2106
= (( 1 2)) 50 50.2 68 107 57 90 0.4106
+ (( 1 2)) (18) 55 53.3 72.2 0.6107 53.8 72 0.7106
(1 + 2) 3 60 62 73.2 106 50 71.3 106

For vertical Electric Field-

(,) Therefore, PNPN is suitable for low power requirement
1 () = 1 = 11 () 212 () (19) applications [26].

0 1 (19) For PNPN TFET IDS is
3
(,) 1 2 )/(
2 () = 2 = 21 () 222 () (20) = 2 2 2 (
.)
(22)

1 (1 + 2)2
(,)
3 () = 3 = 31 () 232 () (21) Where,
3
(1 + 2) = ( 2 0 2 ) (182 ) (23)

H. Vertical TFET (2006-2015) 1

Vertical TFET have SS in very small range of mV/dec. The = (0 2 ) (2) (24)
doping profile and design flow situations also changes the SS.
Therefore, it is an alternative TFET to give lower

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Sub-threshold Swing of TFET,
1 Its Application to Digital Circuits, Indian Institute
( )
= ( ) (25)
Sub-threshold Slope,
2
[6]
= ( )[mV/decade] (26)
5.75( +)
I-2. Dopingless PNPN
The charge plasma concept is used for the design of doping-
less TFET designed on a narrow i-silicon layer. Due to charge
plasma concept, dopings are not required for source and
drain. Instead we choose different work functions for source,
drain and both metal electrodes. For fabrication of doping-less
TFET high-temperature doping/annealing process is not used
therefore ultimately it reduces the thermal budget [26].
Surface depletion width is given by[27],
(, , , ) = () (27) Newport Beach, CA, USA, pp 90-95, August 2004.
Dopingless TFET is candidate for low-power and low-cost
applications in the future [28]. It shows promising switching
behaviour and quite decrement in PVT variations on
subthreshold swing and drive current than that of
conventional-TFET [29]. Now doping-less TFET shows very
good electrostatic control over the channel with reduced
thermal budget and process complexity.
Conclusion
This paper explains different types of TFET from initial stages
of its inception to till recent. Surface Tunnel Transistor is first
tunnel transistor deals with speed, power and IOFF/ION ratio.
Then first TFET basic p-i-n structure is invented which deals
with speed, power, IOFF/ION, tuning range etc. After that
feedback TFET, p-n-i-n TFET, NEMFET, Raised Buried
Oxide TFET, Junctionless TFET, Double gate TFET (DG-
TFET), Vertical TFET, Dopingless PNPN TFET are studied.
Along with these different structures of TFET DG-TFET,
Dopingless PNPN TFET and Vertical DG-TFET shows
superior performance than other studied.
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simulation model, and its application, International
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716, 23-26 May 2004.
[18] Wei Cao, C. J. Yao, G. F. Jiao, Daming Huang, H. Y.
Yu, and Ming-Fu Li, Improvement in Reliability of Satish M Turkane is Pursuing his Ph. D
Tunneling Field-Effect Transistor with p-n-i-n and working as Associate Professor in
Structure, IEEE Transactions on Electron Devices, E&Tc Engineering at Pravara Rural
Vol. 58, no. 7, July 2011. Engineering College Loni,
[19] Alvaro Padilla, Chun Wing Yeung, Changhwan Shin, Ahmednagar, Maharashtra, India. He
Chenming Hu, and Tsu-Jae King Liu, Feedback has more than 16 Years of teaching
FET: A Novel Transistor Exhibiting Steep Switching experience. His area of interest is in the
Behavior at Low Bias Voltages, IEEE International field of Low power FPGA, Interconnects and Post CMOS
Electron Devices Meeting, San Francisco, 15-17 Devices and Circuits in Analog and Digital domain. He is a
December 2008. Life Member of ISTE, IEI and IETE.
[20] Balmukund Rahi, Bahniman Ghosh and Pranav
Asthana, A simulation-based proposed high-k
heterostructureAlGaAs/Si junctionless n-type tunnel
FET, Journal of Semiconductors, 2014. A K Kureshi had completed his Ph. D
[21] Chun-Hsing Shih and Nguyen Dang Chien, Sub-10- in 2010 in the area of Low Power
nm Tunnel Field-Effect Transistor with Graded Techniques and Architecture of FPGAs.
Si/Ge Heterojunction, IEEE Electron Device He is working as a Principal at
Letters, pp 1498-1500, November 2011. Vishvabharti Academys College of
[22] Adrian Ionescu, Double Gate Tunnel FET with Engineering, Ahmednagar,
ultrathin silicon body and high-k gate dielectric, Maharashtra, India. He has more than 19 Years of teaching
European Solid-State Device Research Conference, experience. His area of interest is in the field of Carbon Nano
September 2006. Tubes as Interconnects and logics and in Multi-layer
[23] M. Jagadesh Kumar and Sindhu Janardhanan, Graphene domain. He is a Member of IEEE and Life Member
Doping-Less Tunnel Field Effect Transistor: Design of ISTE, IEI and IETE.
and Investigation, IEEE Transactions on Electron
Devices, pp 3285-3290, October 2013.
[24] Zhong-Fang Han, Guo-Ping Ru and Gang Ruan, A
Simulation Study of Vertical Tunnel Field Effect
Transistors, 9th International Conference
Association of Surgeons of India, pp 25-28, Xiamen,
October 2011.
[25] Brinda Bhowmick, Srimanta Baishya and Rajsekhar
Kar, Length scaling of Hetero-gate dielectric SOI
PNPN TFET, 2011 Annual IEEE India conference,
(INDICON),Hyderabad, pp.1-4,16-18 December
2011.
[26] L. Megala, B. Devanathan, R. Venkatraman and A.
Vishnukumar , Tunneling Field Effect Transistors
for Low Power Digital Systems, International
Journal of Innovative Technology and Exploring
Engineering, Vol. 2, pp.296-299, April 2013.
[27] Cui Ning, Liang Renrong, Wang Jing, Zhou Wei,
and Xu Jun, A PNPN tunnel field-effect transistor
with high-k gate and low-k fringe dielectrics,
Journal of Semiconductors, Vol. 33, no. 8, August
2012.
[28] M. Saketh Ram, Dawit Burusie Abdi, Dopingless
Tunnel FET with a Hetero-Material Gate: Design and
Analysis, IEEE 2nd International Conference on
Emerging Electronics (ICEE- 2014), Bengaluru, 3-6
December, 2014.
[29] Avinash Lahgere, Chitrakant Sahu, and Jawar Singh,
PVT Aware Design of Dopingless Dynamically
Configurable Tunnel FET, IEEE Transactions on
Electron Devices, Vol. 62, Issue. 8, pp.2404-2409,
2015.

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