Unit I

INTRODUCTION

The microprocessor is a programmable integrated device that has computing

decision-making capability similar to that of central processing unit (CPU) of a
computer. The microprocessor communicates and operates in the binary numbers 0 and 1,
called bits. Each microprocessor has a fixed set of instruction in the form of binary
patterns called a machine language. However, it is difficult for humans to communicate
in the language of 0s and 1s. Therefore, the binary instructions are given abbreviated
names, called mnemonics, which form the assembly language for a given microprocessor.

GENERAL 8-BIT MICROPROCESSOR AND ITS ARCHITECTURE

A Simplified but formal structure of a microprocessor based system. At the center

of all operation is the microprocessor unit (MPU). The MPU needs a power supply and
clock connections. The clock may be a separate circuit or may reside with in the
microprocessor chip.

A simple microprocessor unit might have 16 address lines, which form one way
address bus. For an 8 bit processor the MPU also has the typical 8-buffered data lines,
which connect to the two way data bus.
 There are two types of semiconductor memory used in this system. The ROM is
the permanent memory, which probably contains the monitor program for the system.
The ROM has address inputs along with chip-select and read-enable input lines. For an 8-
bit microprocessor the ROM also has 8-bit buffered three-state outputs connected to the
data bus. Each memory word is then 8-bit wide.

The architecture also shows a RAM as the temporary read /write storage devices.
The RAM has address inputs along with chip-select and read /write enable inputs. The
RAM has 8-bit buffered three-state outputs connected to the data bus. This RAM inputs,
outputs and stores data as8-bit words.

The microcomputer system shown uses a keyboard as input device. Power

connections to the keyboard are shown along with data lines to a special IC called a
keyboard interface. The interface circuit stores data and coordinates the keyboard inputs.
The keyboard interface circuit has address, chip-select and control inputs for activating
the unit. The microprocessor unit accepts the new input data via data bus.

The microcomputer uses a group of seven-segment display for output. The display
is connected to the power supply on the right. A special display interface circuit or IC is
used to store the data and drive the displays. When activated by the address, chip-select
and enable signal displays continuously, showing the data stored in the display interface
in visual form.

THE 8085 BUS STRUCTURE

The 8085 MPU performs the functions using three set of communication lines
called buses. 1 address bus. 2 data bus. 3 control bus. These buses are shown in one group
called the system bus.
ADDRESS BUS

The address bus is a group of 16 lines generally identified as A 0 to A15. The

address bus is unidirectional. The bits flow in one direction, from the MPU to peripheral
devices. The MPU uses the address bus to perform the first function, identifying a
peripheral device or a memory location.

DATA BUS

Data bus is a group of eight lines used for data flow. These lines are bidirectional,
data floe in both directions between the MPU and memory and peripheral devices. The
MPU uses the data bus to perform the second function, transferring data.

CONTROL BUS

It is the bus, which totally controls the operation of the system. It is also used to
control the timing of execution. The Control bus is not groups of lines like address or
data buses, but individual lines that provide a pulse to indicate an MPU operation. The
MPU generates specific control signals for every operation (such as memory read or I/O
write) it performs.

INTEL 8085 PIN DIAGRAM

The INTEL 8085 is a 8-bit microprocessor.

It operates on 8-bit data and uses 16-bit address to access the memory.
With the help of 16-bit address, 8085 can access 2 16 = 65536 = 64K memory
locations.
It is a 40-pin DIP chip designed using NMOS.
It operates with a power supply of +5 volts and GND.
8085 generates the clock signal internally by dividing the external supplied clock
signal by two.
Pin Description

Address bus
The 8085 has eight signal lines, A15 A8 which are unidirectional and used as the
high order address bus.

Multiplexed Address/Data bus

The signal lines AD7 AD0 are bidirectional, they serve dual purpose. They are used as
lower order address bus as well as the data bus. During opcode fetch operation in the first
clock cycle, the lines are used as lower order address bus (A0 A7). In subsequent clock
cycle the lines are used as data bus.

Control and status signal

This group of signal includes two control signals (RD - WR), three status signals
(IO/ M, S1 and S0) to identify the nature of operation, and one special signal (ALE) to
indicate the beginning of the operation.

ALE (Output) Address Latch Enable

It occurs during the first clock cycle of a machine state and enables the address to
get latched into the on chip latch of peripherals. The falling edge of ALE is set to
guarantee setup and hold times for the address information. ALE can also be used to
strobe the status information. ALE is never 3stated.

RD (Output 3state) READ Memory or I/O Device.

This indicates the selected memory or I/O device is to be read and that the Data
Bus is available for accepting the data from memory or I/O transfer.

WR (Output 3state) WRITE Memory or I/O Device

This indicates the data on the Data Bus is to be written into the selected memory
or 1/0 location.

IO/ M, (Output) Select Memory or an I/O Device

This status signal indicates that the read / write operation relates to whether the
memory or I/O device. It goes high to indicate an I/O operation and when it is low, it
indicates a memory operation.

These status signals (S1 and S0) are used to know the type of current operation the
CPU performs.
S1 S0 DATA BUS STATUS

0 0 HALT

0 1 WRITE

1 0 READ

1 1 FETCH

READY (Input)
If Ready is high during a read or write cycle, it indicates that the memory or
peripheral is ready to send or receive data. If Ready is low, the CPU will wait for Ready
to go high before completing the read or write cycle.

HOLD (Input)
Indicates that another Master is requesting the use of the Address and Data uses.
The CPU, upon receiving the Hold request. will relinquish the use of buses as soon as the
completion of the current machine cycle. Internal processing can continue. The processor
can regain the buses only after the Hold is removed. When the Hold is acknowledged, the
Address, Data, RD, WR, and IO/M lines are 3stated.

HOLD (Input)
Indicates that another Master is requesting the use of the Address and Data Buses.
The CPU, upon receiving the Hold request. will relinquish the use of buses as soon as the
completion of the current machine cycle. Internal processing can continue. The processor
can regain the buses only after the Hold is removed. When the Hold is acknowledged, the
Address, Data, RD, WR, and IO/M lines are 3stated.

HLDA (Output) HOLD ACKNOWLEDGE

Indicates that the CPU has received the Hold request and that it will relinquish the
buses in the next clock cycle. HLDA goes low after the Hold request is removed. The
CPU takes the buses one half clock cycle after HLDA goes low.

INTR (Input) INTERRUPT REQUEST

It is used as a general purpose interrupt. It is sampled only during the next to the
last clock cycle of the instruction. If it is active, the Program Counter (PC) will be
inhibited from incrementing and an INTA will be issued. During this cycle a RESTART
or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is
enabled and disabled by software. It is disabled by Reset and immediately after an
interrupt is accepted.

INTA (Output) INTERRUPT ACKNOWLEDGE

It is used instead of (and has the same timing as) RD during the Instruction cycle
after an INTR is accepted. It can be used to activate the 8259 Interrupt chip or some other
interrupt port.

RST 5.5

RST 6.5 - (Inputs)

RST 7.5

RESTART INTERRUPTS
These three inputs have the same timing as I NTR except they cause an internal
RESTART to be automatically inserted.

RST 7.5 ~~ Highest Priority

RST 6.5

RST 5.5 o Lowest Priority

The priority of these interrupts is ordered as shown above. These interrupts have a higher
priority than the INTR.

TRAP (Input)
Trap interrupt is a non-maskable restart interrupt. It is recognized at the same time
as INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of
any interrupt.

RESET IN (Input)
Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-
flops. None of the other flags or registers (except the instruction register) are affected The
CPU is held in the reset condition as long as Reset is applied.

RESET OUT (Output)

Indicates CPU is being reset. Can be used as a system RESET. The signal is
synchronized to the processor clock.
X1, X2 (Input)
Crystal or R/C network connections to set the internal clock generator X1 can also
be an external clock input instead of a crystal. The input frequency is divided by 2 to give
the internal operating frequency.

CLK (Output)
Clock Output for use as a system clock when a crystal or R/ C network is used as
an input to the CPU. The period of CLK is twice the X1, X2 input period.

IO/M (Output)
IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold
and Halt modes.

SID (Input)
Serial input data line The data on this line is loaded into accumulator bit 7
whenever a RIM instruction is executed.

SOD (output)
Serial output data line. The output SOD is set or reset as specified by the SIM
instruction.

Vcc
+5 volt supply.

Vss
Ground Reference.

INTEL 8085 ARCHITECTURE

The architecture of.8085 is shown in figure given below. The internal architecture
of 8085 includes the ALU, timing and control unit, instruction register and decoder,
register array, interrupt control and serial I/O control.
OPERATIONS PERFORMED BY 8085

Accumulator
Accumulator is an 8- bit register. It holds one of the data to be processed by
arithmetic logic unit (ALU). It also stores the result of the operation. The accumulator is
also called as A- register.

Temporary Register
The temporary register receives one data to be processed by ALU from external
memory or general purpose registers.

Arithmetic and Logic Unit ALU

The operations performed by ALU of 8085 are addition, subtraction, increment,
decrement, logical AND, OR, EXCL U8IVE -OR, compare, complement and left / right
shift. The accumulator and temporary register are used to hold the data during an
arithmetic / logical operation. After an operation the result is stored in the accumulator
and the flags are set or reset according to the result of the operation.

FLAG REGISTER
There are five flags in 8085, which are sign flag (8), zero flag (Z), auxiliary carry
flag (AC), parity flag (P) and carry flag (CY). The bit positions reserved for these flags in
the flag register are shown in figure below.

After an ALU operation, if the most significant bit of the result is 1, then sign flag is set.
The zero flag is set, if the ALU operation results in zero and it is reset if the result is non-
zero. In an arithmetic operation, when a carry is generated by the lower nibble, the
auxiliary carry flag is set. After an arithmetic or logical operation, if the result has an
even number of 1 's the parity flag is set, other wise it is reset.

If an arithmetic operation results in a carry, the carry flag is set other wise it is reset.
Among the five flags, the AC flag is used internally for BCD arithmetic and other four
flags can be used by the programmer to check the conditions of the result of an operation.

REGISTER ARRAY
Apart from Accumulator (A-register), there are six general-purpose
programmable registers B, C, D, E, H and L.
They can be used as 8-bit registers or paired to store l6-bit data. The allowed pairs
are B-C, D-E and H-L.
The temporary registers W and Z are intended for internal use of the processor
and it cannot be used by the programmer.

STACK POINTER (SP)

Stack Pointer is a 16-bit register used as a memory pointer. The stack
pointer SP, holds the address of the stack top. The stack is a sequence of RAM
memory locations defined by the programmer. The stack is used to save the
content of registers during the execution of a program.
PROGRAM COUNTER (PC)
The program counter (PC) keeps track of program execution. To execute a
program the starting address of the program is loaded in program counter. The PC
sends out an address to fetch a byte of instruction from memory and increment its
content automatically. Hence, when a byte of instruction is fetched, the PC holds
the address of the next byte of the instruction or next instruction.

INSTRUCTION REGISTER & DECODER

Instruction register and decoder is an 8-bit register. When an instruction is fetched
from memory it is placed in instruction register. The instruction decoder decodes the
contents of the instruction register. It also determines the operation to be followed in
executing the entire instruction and directs the timing and control unit accordingly.

TIMING & CONTROL UNIT

The timing and control unit synchronizes all the microprocessor operations with
the clock and generates the control signals necessary for communication between the
microprocessor and peripherals.

Interrupt Control

Sometimes it is necessary to interrupt the execution of the main program to

answer the request from I/O device. For instance an I/O device may send an interrupt
signal to the interrupt control unit to indicate that data is ready for input. The processor
temporarily stops the execution of main program, inputs the data and then returns to the
main program.

Serial I/O Control

Sometimes, I/O devices work with serial data rather than parallel. In such case the
serial data stream from an input device must be converted to 8-bit parallel data before the
processor can use it. Likewise the 8-bit data coming out of the processor must be
converted to serial form before a serial output device can use it.
The serial input data enters 8085 through pin 5 (SID-Serial Input Data) and leaves
through pin 4 (SOD-Serial Output Data).
Pin diagram 8086
Signal Description of 8086
The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged
in a 40 pin CERDIP or plastic package.
The 8086 operates in single processor or multiprocessor configuration to achieve high
performance. The pins serve a particular function in minimum mode (single processor
mode) and other function in maximum mode configuration (multiprocessor mode).
The 8086 signals can be categorised in three groups. The first are the signal having
common functions in minimum as well as maximum mode.
The second are the signals which have special functions for minimum mode and third
are the signals having special functions for maximum mode.

The following signal descriptions are common for both modes.

AD15-AD0
These are the time multiplexed memory I/O address and data lines.
Address remains on the lines during T1 state, while the data is available on the data bus
during T2, T3, Tw and T4.
These lines are active high and float to a tristate during interrupt acknowledge and local
bus hold acknowledge cycles.

A19/S6,A18/S5,A17/S4,A16/S3
These are the time multiplexed address and status lines.
During T1 these are the most significant address lines for memory operations.
During I/O operations, these lines are low. During memory or I/O operations, status
information is available on those lines for T2,T3,Tw and T4.
The status of the interrupt enable flag bit is updated at the beginning of each clock cycle.
The S4 and S3 combinedly indicate which segment register is presently being used for
memory accesses as in below fig.
These lines float to tri-state off during the local bus hold acknowledge. The status line
S6 is always low.
The address bit are separated from the status bit using latches controlled by the ALE
signal.

S3 S4 Indication
0 0 Alternate Data
0 1 Stack
1 0 Code or none
1 1 Data
BHE /S7
The bus high enable is used to indicate the transfer of data over the higher order
( D15-D8 ) data bus as shown in table. It goes low for the data transfer over D15-D8 and
is used to derive chip selects of odd address memory bank or peripherals. BHE is low
during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be
transferred on higher byte of data bus. The status information is available during T2, T3
and T4. The signal is active low and tri-stated during hold. It is low during T1 for the first
pulse of the interrupt acknowledges cycle.

BHE A0 Indication
0 0 Whole Word
0 1 Upper Byte from or even address
1 0 Lower Byte from or even address
1 1 None

RD Read
This signal on low indicates the peripheral that the processor is performing
memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of
any read cycle. The signal remains tri-stated during the hold acknowledge.

READY
This is the acknowledgement from the slow device or memory that they have
completed the data transfer. The signal made available by the devices is synchronized by
the 8284A clock generator to provide ready input to the 8086. The signal is active high.

INTR-Interrupt Request
This is a triggered input. This is sampled during the last clock cycles of each
instruction to determine the availability of the request. If any interrupt request is pending,
the processor enters the interrupt acknowledge cycle.
This can be internally masked by resulting the interrupt enable flag. This signal is
active high and internally synchronized.

TEST
This input is examined by a WAIT instruction. If the TEST pin goes low,
execution will continue, else the processor remains in an idle state. The input is
synchronized internally during each clock cycle on leading edge of clock.

CLK- Clock Input

The clock input provides the basic timing for processor operation and bus control
activity. Its an asymmetric square wave with 33% duty cycle.

MN/MX
The logic level at this pin decides whether the processor is to operate in either
minimum or maximum mode.
The following pin functions are for the minimum mode operation of 8086.

M/ IO Memory/IO
This is a status line logically equivalent to S2 in maximum mode. When it is low,
it indicates the CPU is having an I/O operation, and when it is high, it indicates that the
CPU is having a memory operation. This line becomes active high in the previous T4 and
remains active till final T4 of the current cycle. It is tri-stated during local bus hold
acknowledge .

INTA Interrupt Acknowledge

This signal is used as a read strobe for interrupt acknowledge cycles. i.e. when it
goes low, the processor has accepted the interrupt.

ALE Address Latch Enable

This output signal indicates the availability of the valid address on the
address/data lines, and is connected to latch enable input of latches. This signal is active
high and is never tri-stated.

DT/R Data Transmit/Receive

This output is used to decide the direction of data flow through the trans-receivers
(bidirectional buffers). When the processor sends out data, this signal is high and when
the processor is receiving data, this signal is low.

DEN Data Enable

This signal indicates the availability of valid data over the address/data lines. It is
used to enable the trans-receivers (bidirectional buffers) to separate the data from the
multiplexed address/data signal. It is active from the middle of T2 until the middle of T4.
This is tri-stated during hold acknowledge cycle.

HOLD, HLDA- Acknowledge

When the HOLD line goes high, it indicates to the processor that another master
is requesting the bus access. The processor, after receiving the HOLD request, issues the
hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after
completing the current bus cycle. At the same time, the processor floats the local bus and
control lines. When the processor detects the HOLD line low, it lowers the HLDA signal.
HOLD is an asynchronous input, and is should be externally synchronized.
If the DMA request is made while the CPU is performing a memory or I/O cycle,
it will release the local bus during T4 provided:
1. The request occurs on or before T2 state of the current cycle.
2. The current cycle is not operating over the lower byte of a word.
3. The current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A Lock instruction is not being executed.
The following pin functions are applicable for maximum mode operation of
8086.

S2, S1, S0 Status Lines

These are the status lines which reflect the type of operation, being carried out by the
processor. These become activity during T4 of the previous cycle and active during T1
and T2 of the current bus cycles.

S2 S1 S0 Indication
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O Port
0 1 0 Write I/O Port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive

LOCK
This output pin indicates that other system bus master will be prevented from
gaining the system bus, while the LOCK signal is low. The LOCK signal is activated by
the LOCK prefix instruction and remains active until the completion of the next
instruction. When the CPU is executing a critical instruction which requires the system
bus, the LOCK prefix instruction ensures that other processors connected in the system
will not gain the control of the bus.
The 8086, while executing the prefixed instruction, asserts the bus lock signal
output, which may be connected to an external bus controller.

QS1, QS0 Queue Status

These lines give information about the status of the code pre-fetch queue. These
are active during the CLK cycle after while the queue operation is performed. This
modification in a simple fetch and execute architecture of a conventional microprocessor
offers an added advantage of pipelined processing of the instructions.
The 8086 architecture has 6-byte instruction pre-fetch queue. Thus even the
largest (6-bytes) instruction can be pre-fetched from the memory and stored in the pre-
fetch. This results in a faster execution of the instructions.
In 8085 an instruction is fetched, decoded and executed and only after the
execution of this instruction, the next one is fetched. By pre-fetching the instruction, there
is a considerable speeding up in instruction execution in 8086. This is known as
instruction pipelining.
At the starting the CS:IP is loaded with the required address from which the
execution is to be started. Initially, the queue will be empty an the microprocessor starts a
fetch operation to bring one byte (the first byte) of instruction code, if the CS:IP address
is odd or two bytes at a time, if the CS:IP address is even.
The first byte is a complete op-code in case of some instruction (one byte op-code
instruction) and is a part of op-code, in case of some instructions (two byte op-code
instructions), the remaining part of code lie in second byte.
The second byte is then decoded in continuation with the first byte to decide the
instruction length and the number of subsequent bytes to be treated as instruction data.
The queue is updated after every byte is read from the queue but the fetch cycle is
initiated by BIU only if at least two bytes of the queue are empty and the EU may be
concurrently executing the fetched instructions. The next byte after the instruction is
completed is again the first op-code byte of the next instruction. A similar procedure is
repeated till the complete execution of the program. The fetch operation of the next
instruction is overlapped with the execution of the current instruction. As in the
architecture, there are two separate units, namely Execution unit and Bus interface unit.
While the execution unit is busy in executing an instruction, after it is completely
decoded, the bus interface unit may be fetching the bytes of the next instruction from
memory, depending upon the queue status.

QS3 QS4 Indication

0 0 No Operation
0 1 First byte op-code from the queue
1 0 Empty queue
1 1 Subsequent byte from the queue

RQ / GT0, RQ / GT1 Request/Grant

These pins are used by the other local bus master in maximum mode, to force the
processor to release the local bus at the end of the processor current bus cycle.
Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1.
RQ/GT pins have internal pull-up resistors and may be left unconnected.

Request/Grant sequence is as follows

1. A pulse of one clock wide from another bus master requests the bus access to 8086.
2. During T4 (current) or T1 (next) clock cycle, a pulse one clock wide from 8086 to the
requesting master, indicates that the 8086 has allowed the local bus to float and that it
Will enter the hold acknowledge state at next cycle. The CPU bus interface unit is likely
to be disconnected from the local bus of the system.
3. A one clock wide pulse from another master indicates to the 8086 that the hold request
is about to end and the 8086 may regain control of the local bus at the next clock cycle.
Thus each master to master exchange of the local bus is a sequence of 3 pulses.
There must be at least one dead clock cycle after each bus exchange.
The request and grant pulses are active low. For the bus request those are received
while 8086 is performing memory or I/O cycle, the granting of the bus is governed by the
rules as in case of HOLD and HLDA in minimum mode.
Internal Architecture of 8086

8086 ARCHITECTURE
The 8086 processor is divided into two independent functional units. They
are,
The bus interface unit (BIU).
The Execution Unit (EU).
These two units are linked using an internal data bus.

The BIU performs all bus operations such as instruction fetching, reading and writing
operands for memory and calculating the addresses of the memory operands. The
instruction bytes are transferred to the instruction queue. BIU contains Instruction queue,
Segment registers, Instruction pointer, and Address adder
EU executes instructions from the instruction system byte queue. EU contains Control
circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.
Both units operate asynchronously to give the 8086 an overlapping instruction fetch
and execution mechanism which is called as Pipelining. This results in efficient use of the
system bus and system performance.
Bus Interface Unit
The Bus interface unit (BIU) fetches instruction, reads data from memory
and peripherals and writes data into memory and peripherals.
It contains segment registers, instruction pointer, instruction queue and
address generation / bus control circuit to provide functions such as
fetching and queuing of instruction and bus control.
The BIUs instruction queue is a First in First out (FIFO) group of registers
in which up to six bytes of instruction code are projected from memory.
This is done to speed up program execution by overlapping instruction
fetch with execution. This mechanism is referred to as pipe lining.
If queue is full, the BIU does not perform any bus cycle, BIU does not pre-
fetch any instructions. Therefore, BIU may pre-fetch the instructions from
memory until queue is full.
While fetching the instruction from memory. if the Execution Unit (EU)
interrupts the BIU for memory access, the BIU first complete fetching and
then services the EU.
If a subroutine call or Jump instructions are encountered, the BIU will reset
the queue and begin refilling after passing the new instruction to the EU.
BIU contains an adder, which is used to produce the 20-bit address. The bus
control logic of the BIU generates all the bus control signals such as read
and writes signals for memory and I/O.

Segment registers

It has four, 16 bit registers. These are

Code segment (CS) registers,
Data segment (DS) registers
Stack segment (SS) registers
Extra segment (ES) registers
8086 processor consists of I Mega Byte memory and is divided into segments
of up to 64 Kbytes each.

Code segment (CS)

All program instructions must be located in main memory pointed to
by the 16 bit CS register with a 16 bit offset in the segment
contained in the 16 bit Instruction pointer. The BIU computes the 20
bit physical address.
Therefore the CS the start of the current code segment and IP
contains the offset from this address to the next instruction byte to be
fetched.
Stack segment (SS)
The SS register points to the current stack.
The 20-bit physical stack address is calculated from SS & SP for
stack instructions.
The programmer can use the BP registers instead of SP for
accessing the stack using the based addressing mode. In this case,
the 20-bit physical stack address is calculated from SS & BP.

Data segment (DS)

The DS register points to current data segment, i.e. operands for most
instructions are fetched from this segment.
The 16 bit contents of Source Index (SI) or Destination Index (DI) are
used as offset for calculating the 20 bit physical address.

Extra segment (ES)

This register points to the extra segment, which excess data, is stored.
The DI is used as offset for calculating the 20-bit physical address.
String ES and DI to calculate the 20-bit address for the destination.

Execution Unit

The EU decodes and executes instructions.

A decoder in the EU, translates the instructions.
It has a 16 bit ALU to perform arithmetic and logic operations.

General Purpose Register

It has eight 16 bit registers (AX, BX, CX, DX, SP, BP, SI & DI).
These 16 bit registers are used to store 16 bit/ 8 bit data.
Each 16 bit register (AX, BX, CX, DX) is combination of two 8 bit register
ie., AH (higher byte) and AL (lower byte) combines together to store a 16
bit data in (AX).
AX acts as the 16 bit accumulator in which the Arithmetic & Logical
operation are carried out.
AL is the 8-bit accumulator.
BX is the only general-purpose register, which is used for addressing 8086
memory.
 CX register is the counter register in which the contents always be
decremented by 1.
DX is the data register is used to hold excess 16 bit result while performing
multiplication, division, etc.
SP & BP are point registers, which are used to access data in stack segment.
These are used as offset for SS.
The EU also contains a 16-bit flag register which holds the status flags
typically after an ALU operation.
The flag register of 8086 micro processor is,

Control Circuitry and instruction decoder

The Execution unit fetches instruction from the instruction queue. The
above instruction is stored in the decoder. The decoder translates each instruction
into sequence of action, which execution unit carries out.

All the above actions are controlled by the control circuitry. Control
circuitry generates appropriate signals at fixed intervals of time.

Flag register

X X X X O D I T S Z X AC X P X CY

O Overflow Flag
D Direction Flag
I Interrupt Flag
T Trap Flag
S Sign Flag
Z Zero Flag
AC Auxiliary Carry Flag
P Parity Flag
CY Carry Flag
X Not Used

The flags are divided into two classifications. They are,

(A) Condition code Flags

These flags reflect the result of Operations Performed by ALU. They
are,
 Over flow flag (O): This flag is set, if an overflow occurs during the
arithmetic operation of two signed numbers.
Sign flag (S): This flag is set, if an MSB of the accumulator is set after any
computation.
Zero flag (Z): This flag is set, if the result of any computation is zero.
Auxiliary carry flag (AC): This flag is set, if there is a carry from the third
bit, during addition or borrow.
Parity flag (P): The flag is set, if the lower byte result contains
even number of 1s.
Carry flag (CY): This flag is set, if any computation result contains a
carry.

(B) Machine control flags

Direction Flag: This flag is set, if the string is processed from higher
address towards lower address. Otherwise, the flag is reset. This is used
only in string manipulation instructions.
Interrupt flag: This flag is set, only when maskable interrupts are
recognized.
Trap flag: When a trap interrupt is received by the processor, this flag is
set, which indicates, the processor to execute the current instruction and to
transfer the control to trap service routine. In Other words, When 8086
enters in single step mode, this flag is set.

Some Important Terms in Microprocessor

Bus a group of lines (wires) used to transfer bits between the microprocessor and
other components of the computer system.

Bit a binary digit, 0 or 1

Byte a group or eight bits.

Word a group of bits the computer recognizes and process at a time.

The microprocessor (MPU) primarily performs four operations: Memory Read,

Memory Write, I/O Read, and I/O Write. For each operation, it generates the
appropriate control signal.
ALE The signal is used to differentiate address and data in the multiplexed address
data bus. It generates pulse at the beginning of every machine cycle which
is used to latch the lower order address from the multiplexed bus.

The IO/M is a status signal When it is high, it indicates an I/O operation; when it
is low, it indicates a memory operation.

WR It is writing control signal and it is asserted low whenever processor writes date
to memory or I/O port

The basic units of microprocessor are ALU, Register Array and control Unit.

The 8086 can operate in two modes and they are minimum (or uniprocessor)
mode and maximum ( or multiprocessor) mode.

The 8086 can operate on either 8-bit or 16-bit data. The 8086 uses 20 bit address
to access memory and 16-bit address to access 1/0 devices.

In pipelined architecture the processor will have number of functional units and the
execution time of functional units are overlapped. Each functional unit
works independently most of the time.

The number of address lines required to determined by the number of registers

in the chip (2n = Number of registers where n is the address lines).

214 = 16384 memory registers

= 16 KB
Review Questions
Part A

1. What is Microprocessor?
2. What are the basic units of a microprocessor?
3. What is a bus?
4. Define Bit, Byte and Word.
5. Why the data bus is bidirectional?
6. What is the function of Accumulator?
7. List the four operations commonly performed by the MPU.
8. Specify the function of the address bus and the direction of the information flow
on the address bus.
9. What is pipelined architecture?
10. What is the function of the WR signal on the memory chip?
11. How many memory locations can be addressed by a microprocessor with 14
address lines?
12. State the function of ALE signal of the 8085microprocessor.
13. Show the bit position of various flags in 8085.
14. What is program counter?
15. Mention the names of various registers in 8085 along with its size.
16. What are the machine control flags of 8086?
17. List the flags of 8086
18. What is instruction pipelining?
19. What is queue? How queue is implemented in 8086?
20. What are the functional units available in 8086 architecture?
21. State the function of Data Segment in 8086.
22. What are the modes in which 8086 can operate?
23. State the function of IO/M in 8086.
24. What are the various segment registers in 8086?
25. What is the data and address size in 8086?
 Part B

1. Sketch the functional block diagram of general 8-bit microprocessor and explain
its function.
2. Draw the functional block diagram of 8085 p and explain their functions.
3. Draw the pin diagram of 8085 p and explain the function of each pin.
4. Draw and explain about
i) Bus structure of 8085 p
ii) Flag register of 8085 p
5. Discuss the function of following
i) General purpose registers.
ii) Timing and control unit
iii) Stack pointer
6. Draw the Architecture of 8086 p and explain their functions.
7. Draw the pin diagram of 8086 p and explain the pin functions for minimum mode
operation.
8. With neat sketch explain the following
i) Flag register of 8086 p.
ii) Segment register.
9. Sketch the pin diagram of 8086 p and explain the pin functions for maximum mode
operation.
10. Discuss about the following
i) General purpose register of 8086
ii) Control circuitry and instruction decoder.