Flash memory

For the neuropsychological concept related to human medical electronics. In addition to being non-volatile,
memory, see Flashbulb memory. ash memory oers fast read access times, although not
Flash memory is an electronic (solid-state) non-volatile as fast as static RAM or ROM.[2] Its mechanical shock
resistance helps explain its popularity over hard disks in
portable devices, as does its high durability, ability to
withstand high pressure, temperature and immersion in
water, etc.[3]
Although ash memory is technically a type of EEP-
ROM, the term EEPROM is generally used to refer
specically to non-ash EEPROM which is erasable in
small blocks, typically bytes. Because erase cycles are
slow, the large block sizes used in ash memory erasing
give it a signicant speed advantage over non-ash EEP-
ROM when writing large amounts of data. As of 2013,
ash memory costs much less than byte-programmable
EEPROM and had become the dominant memory type
wherever a system required a signicant amount of non-
volatile solid-state storage.
A USB ash drive. The chip on the left is the ash memory. The
controller is on the right.

computer storage medium that can be electrically erased

and reprogrammed.
1 History
Toshiba developed ash memory from EEPROM (elec- Flash memory (both NOR and NAND types) was in-
trically erasable programmable read-only memory) in thevented by Fujio Masuoka while working for Toshiba circa
early 1980s and introduced it to the market in 1984. The
1980.[4][5] According to Toshiba, the name ash was
two main types of ash memory are named after the suggested by Masuokas colleague, Shji Ariizumi, be-
NAND and NOR logic gates. The individual ash mem- cause the erasure process of the memory contents re-
ory cells exhibit internal characteristics similar to those
minded him of the ash of a camera.[6] Masuoka and
of the corresponding gates. colleagues presented the invention at the IEEE 1984 In-
Whereas EPROMs had to be completely erased before ternational Electron Devices Meeting (IEDM) held in San
being rewritten, NAND-type ash memory may be writ- Francisco.[7]
ten and read in blocks (or pages) which are generally
Intel Corporation saw the massive potential of the inven-
much smaller than the entire device. NOR-type ash al- tion and introduced the rst commercial NOR type ash
lows a single machine word (byte) to be writtento an
chip in 1988.[8] NOR-based ash has long erase and write
erased locationor read independently. times, but provides full address and data buses, allowing
The NAND type operates primarily in memory cards, random access to any memory location. This makes it a
USB ash drives, solid-state drives (those produced in suitable replacement for older read-only memory (ROM)
2009 or later), and similar products, for general storage chips, which are used to store program code that rarely
and transfer of data. NAND or NOR ash memory is also needs to be updated, such as a computers BIOS or the
often used to store conguration data in numerous digital rmware of set-top boxes. Its endurance may be from as
products, a task previously made possible by EEPROM little as 100 erase cycles for an on-chip ash memory,[9]
or battery-powered static RAM. One key disadvantage of to a more typical 10,000 or 100,000 erase cycles, up to
ash memory is that it can only endure a relatively small 1,000,000 erase cycles.[10] NOR-based ash was the ba-
number of write cycles in a specic block.[1] sis of early ash-based removable media; CompactFlash
Example applications of both types of ash memory was originally based on it, though later cards moved to
include personal computers, PDAs, digital audio play- less expensive NAND ash.
ers, digital cameras, mobile phones, synthesizers, video NAND ash has reduced erase and write times, and re-
games, scientic instrumentation, industrial robotics, and quires less chip area per cell, thus allowing greater storage

1
2 2 PRINCIPLES OF OPERATION

density and lower cost per bit than NOR ash; it also has 2.1 Floating-gate transistor
up to 10 times the endurance of NOR ash. However, the
I/O interface of NAND ash does not provide a random- Main article: Floating-gate MOSFET
access external address bus. Rather, data must be read on
a block-wise basis, with typical block sizes of hundreds
to thousands of bits. This makes NAND ash unsuitable In ash memory, each memory cell resembles a standard
as a drop-in replacement for program ROM, since most MOSFET, except that the transistor has two gates instead
microprocessors and microcontrollers require byte-level of one. On top is the control gate (CG), as in other MOS
random access. In this regard, NAND ash is similar to transistors, but below this there is a oating gate (FG) in-
other secondary data storage devices, such as hard disks sulated all around by an oxide layer. The FG is interposed
and optical media, and is thus, highly suitable for use in between the CG and the MOSFET channel. Because the
mass-storage devices, such as memory cards. The rst FG is electrically isolated by its insulating layer, electrons
NAND-based removable media format was SmartMedia placed on it are trapped until they are removed by another
in 1995, and many others have followed, including: application of electric eld (e.g. Applied voltage or UV
as in EPROM). Counter-intuitively, placing electrons on
the FG sets the transistor to the logical 0 state. Once
MultiMediaCard the FG is charged, the electrons in it screen (partially can-
cel) the electric eld from the CG, thus, increasing the
Secure Digital
threshold voltage (VT) of the cell. This means that now
Memory Stick, and xD-Picture Card. a higher voltage(VT) must be applied to the CG to make
the channel conductive. In order to read a value from the
transistor, an intermediate voltage between the threshold
A new generation of memory card formats, including RS- voltages (VT & VT) is applied to the CG. If the channel
MMC, miniSD and microSD, feature extremely small conducts at this intermediate voltage, the FG must be un-
form factors. For example, the microSD card has an area charged (if it were charged, we would not get conduction
of just over 1.5 cm2 , with a thickness of less than 1 mm. because the intermediate voltage is less than VT), and
microSD capacities range from 64 MB to 256 GB, as of hence, a logical 1 is stored in the gate. If the channel
May 2016. [11] does not conduct at the intermediate voltage, it indicates
that the FG is charged, and hence, a logical 0 is stored
in the gate. The presence of a logical 0 or 1 is sensed
by determining whether there is current owing through
the transistor when the intermediate voltage is asserted
on the CG. In a multi-level cell device, which stores more
than one bit per cell, the amount of current ow is sensed
Source
Line
Bit Line (rather than simply its presence or absence), in order to
Word Line
Control Gate determine more precisely the level of charge on the FG.
Float Gate

N P N

2.1.1 Internal charge pumps

Despite the need for high programming and erasing volt-

A ash memory cell. ages, virtually all ash chips today require only a single
supply voltage, and produce the high voltages using on-
chip charge pumps.
Over half the energy used by a 1.8 V NAND ash chip
2 Principles of operation is lost in the charge pump itself. Since boost convert-
ers are inherently more ecient than charge pumps, re-
Flash memory stores information in an array of memory searchers developing low-power SSDs have proposed re-
cells made from oating-gate transistors. In single-level turning to the dual Vcc/Vpp supply voltages used on all
cell (SLC) devices, each cell stores only one bit of in- the early ash chips, driving the high Vpp voltage for all
formation. In multi-level cell (MLC) devices, including ash chips in a SSD with a single shared external boost
triple-level cell (TLC) devices, can store more than one converter.[13][14][15][16][17][18][19][20]
bit per cell. In spacecraft and other high-radiation environments, the
The oating gate may be conductive (typically polysilicon on-chip charge pump is the rst part of the ash chip to
in most kinds of ash memory) or non-conductive (as in fail, although ash memories will continue to workin
SONOS ash memory).[12] read-only modeat much higher radiation levels.[21]
2.3 NAND ash 3

2.2 NOR ash Erasure via tunneling

0V
In NOR ash, each cell has one end connected directly
to ground, and the other end connected directly to a bit
200A
line. This arrangement is called NOR ash because it oating
gate
acts like a NOR gate: when one of the word lines (con- open
nected to the cells CG) is brought high, the correspond-
ing storage transistor acts to pull the output bit line low.
NOR ash continues to be the technology of choice for SOURCE DRAIN
embedded applications requiring a discrete non-volatile
12 V
memory device. The low read latencies characteristic of
NOR devices allow for both direct code execution and
data storage in a single memory product.[22]

Erasing a NOR memory cell (setting it to logical 1), via quantum

tunneling.
Bit Line

Word Word Word Word Word Word

an elevated on-voltage (typically >5 V) is applied to

Line 0 Line 1 Line 2 Line 3 Line 4 Line 5

the CG

the channel is now turned on, so electrons can ow

N N, GND N N, GND
P
N N, GND N
from the source to the drain (assuming an NMOS
transistor)

the source-drain current is suciently high to cause

some high energy electrons to jump through the in-
sulating layer onto the FG, via a process called hot-
NOR ash memory wiring and structure on silicon
electron injection.

Programming via hot electron injection 2.2.2 Erasing

12 V
To erase a NOR ash cell (resetting it to the 1 state),

200A a large voltage of the opposite polarity is applied be-
oating
gate tween the CG and source terminal, pulling the electrons
0V
o the FG through quantum tunneling. Modern NOR
ash memory chips are divided into erase segments (of-
ten called blocks or sectors). The erase operation can be
SOURCE DRAIN performed only on a block-wise basis; all the cells in an
12 V erase segment must be erased together. Programming of
NOR cells, however, generally can be performed one byte
or word at a time.

2.3 NAND ash

Programming a NOR memory cell (setting it to logical 0), via
hot-electron injection. NAND ash also uses oating-gate transistors, but they
are connected in a way that resembles a NAND gate: sev-
eral transistors are connected in series, and the bit line is
2.2.1 Programming pulled low only if all the word lines are pulled high (above
the transistors VT). These groups are then connected via
A single-level NOR ash cell in its default state is logically some additional transistors to a NOR-style bit line array
equivalent to a binary 1 value, because current will ow in the same way that single transistors are linked in NOR
through the channel under application of an appropriate ash.
voltage to the control gate, so that the bitline voltage is Compared to NOR ash, replacing single transistors with
pulled down. A NOR ash cell can be programmed, or serial-linked groups adds an extra level of addressing.
set to a binary 0 value, by the following procedure: Whereas NOR ash might address memory by page then
4 3 LIMITATIONS

2.4.1 Structure

Bit Line V-NAND uses a charge trap ash geometry (pioneered

Ground
Select
Transistor
Word
Line 0
Word
Line 1
Word
Line 2
Word
Line 3
Word
Line 4
Word
Line 5
Word
Line 6
Word
Line 7
Bit Line
Select
Transistor
in 2002 by AMD) that stores charge on an embedded sil-
icon nitride lm. Such a lm is more robust against point
defects and can be made thicker to hold larger numbers
of electrons. V-NAND wraps a planar charge trap cell
into a cylindrical form.[23]
N N N N N N N N N N N

An individual memory cell is made up of one planar

P

polysilicon layer containing a hole lled by multiple con-

centric vertical cylinders. The holes polysilicon surface
acts as the gate electrode. The outermost silicon dioxide
cylinder acts as the gate dielectric, enclosing a silicon ni-
tride cylinder that stores charge, in turn enclosing a silicon
NAND ash memory wiring and structure on silicon dioxide cylinder as the tunnel dielectric that surrounds a
central rod of conducting polysilicon which acts as the
[23]
word, NAND ash might address it by page, word and bit. conducting channel.
Bit-level addressing suits bit-serial applications (such as Memory cells in dierent vertical layers do not interfere
hard disk emulation), which access only one bit at a time. with each other, as the charges cannot move vertically
Execute-in-place applications, on the other hand, require through the silicon nitride storage medium, and the elec-
every bit in a word to be accessed simultaneously. This tric elds associated with the gates are closely conned
requires word-level addressing. In any case, both bit and within each layer. The vertical collection is electrically
word addressing modes are possible with either NOR or identical to the serial-linked groups in which conventional
NAND ash. NAND ash memory is congured.[23]
To read data, rst the desired group is selected (in the
same way that a single transistor is selected from a NOR 2.4.2 Construction
array). Next, most of the word lines are pulled up above
the VT of a programmed bit, while one of them is pulled Growth of a group of V-NAND cells begins with an al-
up to just over the VT of an erased bit. The series group ternating stack of conducting (doped) polysilicon layers
will conduct (and pull the bit line low) if the selected bit and insulating silicon dioxide layers.[23]
has not been programmed.
The next step is to form a cylindrical hole through these
Despite the additional transistors, the reduction in ground layers. In practice, a 128 Gibit V-NAND chip with 24
wires and bit lines allows a denser layout and greater stor- layers of memory cells requires about 2.9 billion such
age capacity per chip. (The ground wires and bit lines are holes. Next the holes inner surface receives multiple
actually much wider than the lines in the diagrams.) In coatings, rst silicon dioxide, then silicon nitride, then a
addition, NAND ash is typically permitted to contain a second layer of silicon dioxide. Finally, the hole is lled
certain number of faults (NOR ash, as is used for a BIOS with conducting (doped) polysilicon.[23]
ROM, is expected to be fault-free). Manufacturers try to
maximize the amount of usable storage by shrinking the
size of the transistors. 2.4.3 Performance

As of 2013, V-NAND ash architecture allows read and

2.3.1 Writing and erasing write operations twice as fast as conventional NAND and
can last up to 10 times as long, while consuming 50 per-
NAND ash uses tunnel injection for writing and tunnel cent less power. They oer comparable physical bit den-
release for erasing. NAND ash memory forms the core sity using 10-nm lithography, but may be able to increase
of the removable USB storage devices known as USB bit density by up to two orders of magnitude.[23]
ash drives, as well as most memory card formats and
solid-state drives available today.
3 Limitations
2.4 Vertical NAND
3.1 Block erasure
Vertical NAND (V-NAND) memory stacks memory
cells vertically and uses a charge trap ash architecture. One limitation of ash memory is that, although it can
The vertical layers allow larger areal bit densities without be read or programmed a byte or a word at a time in a
requiring smaller individual cells.[23] random access fashion, it can be erased only a block at a
3.3 Read disturb 5

time. This generally sets all bits in the block to 1. Starting routers, which are programmed only once or at most a few
with a freshly erased block, any location within that block times during their lifetimes.
can be programmed. However, once a bit has been set to In December 2012, Taiwanese engineers from Macronix
0, only by erasing the entire block can it be changed back
revealed their intention to announce at the 2012 IEEE
to 1. In other words, ash memory (specically NOR International Electron Devices Meeting that it has gured
ash) oers random-access read and programming oper- out how to improve NAND ash storage read/write cycles
ations, but does not oer arbitrary random-access rewrite
from 10,000 to 100 million cycles using a self-healing
or erase operations. A location can, however, be rewrit-
process that uses a ash chip with onboard heaters that
ten as long as the new values 0 bits are a superset of the
could anneal small groups of memory cells.[26] The built-
over-written values. For example, a nibble value may bein thermal annealing replaces the usual erase cycle with
erased to 1111, then written as 1110. Successive writes
a local high temperature process that not only erases the
to that nibble can change it to 1010, then 0010, and nally
stored charge, but also repairs the electron-induced stress
0000. Essentially, erasure sets all bits to 1, and program-
in the chip, giving write cycles of at least 100 million.[27]
ming can only clear bits to 0. File systems designed for
The result is a chip that can be erased and rewritten over
ash devices can make use of this capability, for example,
and over, even when it should theoretically break down.
to represent sector metadata. As promising as Macronixs breakthrough could be for
Although data structures in ash memory cannot be up- the mobile industry, however, there are no plans for a
dated in completely general ways, this allows members commercial product to be released any time in the near
to be removed by marking them as invalid. This tech- future.[28]
nique may need to be modied for multi-level cell de-
vices, where one memory cell holds more than one bit.
Common ash devices such as USB ash drives and mem-
ory cards provide only a block-level interface, or ash 3.3 Read disturb
translation layer (FTL), which writes to a dierent cell
each time to wear-level the device. This prevents incre- The method used to read NAND ash memory can cause
mental writing within a block; however, it does not help nearby cells in the same memory block to change over
the device from being prematurely worn out by intensive time (become programmed). This is known as read dis-
write patterns. turb. The threshold number of reads is generally in the
hundreds of thousands of reads between intervening erase
operations. If reading continually from one cell, that cell
3.2 Memory wear will not fail but rather one of the surrounding cells on a
subsequent read. To avoid the read disturb problem the
Another limitation is that ash memory has a nite num- ash controller will typically count the total number of
ber of programerase cycles (typically written as P/E cy- reads to a block since the last erase. When the count
cles). Most commercially available ash products are exceeds a target limit, the aected block is copied over
guaranteed to withstand around 100,000 P/E cycles be- to a new block, erased, then released to the block pool.
fore the wear begins to deteriorate the integrity of the The original block is as good as new after the erase. If
storage.[24] Micron Technology and Sun Microsystems the ash controller does not intervene in time, however,
announced an SLC NAND ash memory chip rated for a read disturb error will occur with possible data loss
1,000,000 P/E cycles on 17 December 2008.[25] if the errors are too numerous to correct with an error-
correcting code.[29][30]
The guaranteed cycle count may apply only to block zero
(as is the case with TSOP NAND devices), or to all
blocks (as in NOR). This eect is mitigated in some chip
rmware or le system drivers by counting the writes and 3.4 X-ray eects
dynamically remapping blocks in order to spread write
operations between sectors; this technique is called wear
leveling. Another approach is to perform write verica- Most ash ICs come in ball grid array (BGA) packages,
tion and remapping to spare sectors in case of write fail- and even the ones that do not are often mounted on a
ure, a technique called bad block management (BBM). PCB next to other BGA packages. After PCB Assem-
For portable consumer devices, these wearout manage- bly, boards with BGA packages are often X-rayed to see
ment techniques typically extend the life of the ash if the balls are making proper connections to the proper
memory beyond the life of the device itself, and some pad, or if the BGA needs rework. These X-rays can erase
data loss may be acceptable in these applications. For programmed bits in a ash chip (convert programmed 0
high reliability data storage, however, it is not advisable bits into erased 1 bits). Erased bits (1 bits) are not af-
to use ash memory that would have to go through a large fected by X-rays.[31][32]
number of programming cycles. This limitation is mean- Some manufacturers are now making X-ray proof SD[33]
ingless for 'read-only' applications such as thin clients and and USB[34] memory devices.
6 4 LOW-LEVEL ACCESS

4 Low-level access 4.2 NAND memories

The low-level interface to ash memory chips diers
from those of other memory types such as DRAM, ROM,
and EEPROM, which support bit-alterability (both zero
to one and one to zero) and random access via externally
accessible address buses.
NOR memory has an external address bus for reading and
programming. For NOR memory, reading and program- Typical block sizes include:
ming are random-access, and unlocking and erasing are
block-wise. For NAND memory, reading and program-
ming are page-wise, and unlocking and erasing are block-
wise.
4.1 NOR memories
NAND ash architecture was introduced by Toshiba in
1989.[36] These memories are accessed much like block
devices, such as hard disks. Each block consists of a num-
ber of pages. The pages are typically 512[37] or 2,048 or
4,096 bytes in size. Associated with each page are a few
bytes (typically 1/32 of the data size) that can be used for
storage of an error correcting code (ECC) checksum.
32 pages of 512+16 bytes each for a block size of
16 kB
64 pages of 2,048+64 bytes each for a block size of
128 kB[38]
64 pages of 4,096+128 bytes each for a block size
of 256 kB[39]
128 pages of 4,096+128 bytes each for a block size
of 512 kB.

Reading from NOR ash is similar to reading from While reading and programming is performed on a page
random-access memory, provided the address and data basis, erasure can only be performed on a block basis.[40]
bus are mapped correctly. Because of this, most micro-
NAND devices also require bad block management by
processors can use NOR ash memory as execute in place the device driver software, or by a separate controller
(XIP) memory, meaning that programs stored in NOR
chip. SD cards, for example, include controller circuitry
ash can be executed directly from the NOR ash without to perform bad block management and wear leveling.
needing to be copied into RAM rst. NOR ash may be
When a logical block is accessed by high-level software, it
programmed in a random-access manner similar to read- is mapped to a physical block by the device driver or con-
ing. Programming changes bits from a logical one to a troller. A number of blocks on the ash chip may be set
zero. Bits that are already zero are left unchanged. Era- aside for storing mapping tables to deal with bad blocks,
sure must happen a block at a time, and resets all the bits
or the system may simply check each block at power-up
in the erased block back to one. Typical block sizes are to create a bad block map in RAM. The overall memory
64, 128, or 256 KiB. capacity gradually shrinks as more blocks are marked as
Bad block management is a relatively new feature in NOR bad.
chips. In older NOR devices not supporting bad block NAND relies on ECC to compensate for bits that may
management, the software or device driver controlling the spontaneously fail during normal device operation. A
memory chip must correct for blocks that wear out, or the typical ECC will correct a one-bit error in each 2048 bits
device will cease to work reliably. (256 bytes) using 22 bits of ECC, or a one-bit error in
The specic commands used to lock, unlock, program, each 4096 bits (512 bytes) using 24 bits of ECC.[41] If
or erase NOR memories dier for each manufacturer. the ECC cannot correct the error during read, it may still
To avoid needing unique driver software for every device detect the error. When doing erase or program opera-
made, special Common Flash Memory Interface (CFI) tions, the device can detect blocks that fail to program or
commands allow the device to identify itself and its crit- erase and mark them bad. The data is then written to a
ical operating parameters. dierent, good block, and the bad block map is updated.
Besides its use as random-access ROM, NOR ash can Hamming codes are the most commonly used ECC for
also be used as a storage device, by taking advantage of SLC NAND ash. Reed-Solomon codes and Bose-
random-access programming. Some devices oer read- Chaudhuri-Hocquenghem codes are commonly used
while-write functionality so that code continues to exe- ECC for MLC NAND ash. Some MLC NAND ash
cute even while a program or erase operation is occur- chips internally generate the appropriate BCH error cor-
ring in the background. For sequential data writes, NOR rection codes. [35]
ash chips typically have slow write speeds, compared
Most NAND devices are shipped from the factory with
with NAND ash. some bad blocks. These are typically marked according
Typical NOR ash does not need an error correcting to a specied bad block marking strategy. By allowing
code.[35] some bad blocks, the manufacturers achieve far higher
 7

yields than would be possible if all blocks had to be ver- interfaces for nonvolatile memory subsystems, including
ied good. This signicantly reduces NAND ash costs the ash cache device connected to the PCI Express
and only slightly decreases the storage capacity of the bus.
parts.
When executing software from NAND memories, virtual
memory strategies are often used: memory contents must 5 Distinction between NOR and
rst be paged or copied into memory-mapped RAM and NAND ash
executed there (leading to the common combination of
NAND + RAM). A memory management unit (MMU)
NOR and NAND ash dier in two important ways:
in the system is helpful, but this can also be accomplished
with overlays. For this reason, some systems will use
a combination of NOR and NAND memories, where a the connections of the individual memory cells are
smaller NOR memory is used as software ROM and a dierent
larger NAND memory is partitioned with a le system the interface provided for reading and writing the
for use as a non-volatile data storage area. memory is dierent (NOR allows random-access for
NAND sacrices the random-access and execute-in- reading, NAND allows only page access)
place advantages of NOR. NAND is best suited to sys-
tems requiring high capacity data storage. It oers higher These two are linked by the design choices made in the
densities, larger capacities, and lower cost. It has faster development of NAND ash. A goal of NAND ash de-
erases, sequential writes, and sequential reads. velopment was to reduce the chip area required to imple-
ment a given capacity of ash memory, and thereby to
reduce cost per bit and increase maximum chip capacity
4.3 Standardization so that ash memory could compete with magnetic stor-
age devices like hard disks.
A group called the Open NAND Flash Interface Working
Group (ONFI) has developed a standardized low-level in- NOR and NAND ash get their names from the struc- [46]
terface for NAND ash chips. This allows interoperabil- ture of the interconnections between memory cells.
ity between conforming NAND devices from dierent In NOR ash, cells are connected in parallel to the bit
vendors. The ONFI specication version 1.0[42] was re- lines, allowing cells to be read and programmed individ-
leased on 28 December 2006. It species: ually. The parallel connection of cells resembles the par-
allel connection of transistors in a CMOS NOR gate. In
NAND ash, cells are connected in series, resembling a
a standard physical interface (pinout) for NAND NAND gate. The series connections consume less space
ash in TSOP48, WSOP-48, LGA52, and than parallel ones, reducing the cost of NAND ash. It
BGA63 packages does not, by itself, prevent NAND cells from being read
a standard command set for reading, writing, and and programmed individually.
erasing NAND ash chips Each NOR ash cell is larger than a NAND ash cell
10 F2 vs 4 F2 even when using exactly the same
a mechanism for self-identication (comparable to semiconductor device fabrication and so each transistor,
the serial presence detection feature of SDRAM contact, etc. is exactly the same sizebecause NOR ash
memory modules) cells require a separate metal contact for each cell.[47]
When NOR ash was developed, it was envisioned as a
The ONFI group is supported by major NAND ash
more economical and conveniently rewritable ROM than
manufacturers, including Hynix, Intel, Micron Technol- contemporary EPROM and EEPROM memories. Thus
ogy, and Numonyx, as well as by major manufacturers of random-access reading circuitry was necessary. How-
devices incorporating NAND ash chips.[43] ever, it was expected that NOR ash ROM would be read
Two major ash device manufacturers, Toshiba and much more often than written, so the write circuitry in-
Samsung, have chosen to use an interface of their own cluded was fairly slow and could erase only in a block-
design known as Toggle Mode (and now Toggle V2.0). wise fashion. On the other hand, applications that use
This interface isn't pin-to-pin compatible with the ONFI ash as a replacement for disk drives do not require word-
specication. The result is a product designed for one level write address, which would only add to the complex-
vendors devices may not be able to use another vendors ity and cost unnecessarily.
devices.[44] Because of the series connection and removal of word-
A group of vendors, including Intel, Dell, and Microsoft, line contacts, a large grid of NAND ash memory cells
formed a Non-Volatile Memory Host Controller Interface will occupy perhaps only 60% of the area of equivalent
(NVMHCI) Working Group.[45] The goal of the group is NOR cells[48] (assuming the same CMOS process reso-
to provide standard software and hardware programming lution, for example, 130 nm, 90 nm, or 65 nm). NAND
8 7 CAPACITY

ashs designers realized that the area of a NAND chip, 7 Capacity

and thus the cost, could be further reduced by removing
the external address and data bus circuitry. Instead, ex-
ternal devices could communicate with NAND ash via Multiple chips are often arrayed to achieve higher
sequential-accessed command and data registers, which capacities[51] for use in consumer electronic devices such
would internally retrieve and output the necessary data. as multimedia players or GPSs. The capacity of ash
This design choice made random-access of NAND ash chips generally follows Moores Law because they are
memory impossible, but the goal of NAND ash was to manufactured with many of the same integrated circuits
replace mechanical hard disks, not to replace ROMs. techniques and equipment.
Consumer ash storage devices typically are advertised
with usable sizes expressed as a small integer power of
two (2, 4, 8, etc.) and a designation of megabytes (MB) or
gigabytes (GB); e.g., 512 MB, 8 GB. This includes SSDs
5.1 Write endurance marketed as hard drive replacements, in accordance with
traditional hard drives, which use decimal prexes.[52]
The write endurance of SLC oating-gate NOR ash is Thus, an SSD marked as 64 GB" is at least 64 1,0003
typically equal to or greater than that of NAND ash, bytes (64 GB). Most users will have slightly less capacity
while MLC NOR and NAND ash have similar en- than this available for their les, due to the space taken
durance capabilities. Examples of endurance cycle rat- by le system metadata.
ings listed in datasheets for NAND and NOR ash are
The ash memory chips inside them are sized in strict bi-
provided.
nary multiples, but the actual total capacity of the chips is
However, by applying certain algorithms and design not usable at the drive interface. It is considerably larger
paradigms such as wear leveling and memory over- than the advertised capacity in order to allow for distribu-
provisioning, the endurance of a storage system can be tion of writes (wear leveling), for sparing, for error cor-
tuned to serve specic requirements.[2][49] rection codes, and for other metadata needed by the de-
Computation of NAND ash memory endurance is a vices internal rmware.
challenging subject that depends on SLC/MLC/TLC In 2005, Toshiba and SanDisk developed a NAND ash
memory type as well as the use pattern. In order to com- chip capable of storing 1 GB of data using multi-level
pute the longevity of the NAND ash, one must account cell (MLC) technology, capable of storing two bits of
for the size of the memory chip, the type of memory (e.g. data per cell. In September 2005, Samsung Electronics
SLC/MLC/TLC), and use pattern. announced that it had developed the worlds rst 2 GB
chip.[53]
In March 2006, Samsung announced ash hard drives
with a capacity of 4 GB, essentially the same order of
magnitude as smaller laptop hard drives, and in Septem-
6 Flash le systems ber 2006, Samsung announced an 8 GB chip produced us-
ing a 40 nm manufacturing process.[54] In January 2008,
SanDisk announced availability of their 16 GB MicroS-
Main article: Flash le system DHC and 32 GB SDHC Plus cards.[55][56]
More recent ash drives (as of 2012) have much greater
Because of the particular characteristics of ash memory, capacities, holding 64, 128, and 256 GB.[57]
it is best used with either a controller to perform wear
leveling and error correction or specically designed ash A joint development at Intel and Micron will allow the
le systems, which spread writes over the media and deal production of 32 layer 3.5 terabyte (TB) NAND ash
with the long erase times of NOR ash blocks.[50] The sticks and 10 TB standard-sized SSDs. The device in-
basic concept behind ash le systems is the following: cludes 5 packages of 16 x 48 GB TLC dies, using a oat-
when the ash store is to be updated, the le system will ing gate cell design.[58]
write a new copy of the changed data to a fresh block, Flash chips continue to be manufactured with capacities
remap the le pointers, then erase the old block later when under or around 1 MB, e.g., for BIOS-ROMs and embed-
it has time. ded applications.
In practice, ash le systems are used only for memory In July 2016, Samsung announced the 4TB Samsung 850
technology devices (MTDs), which are embedded ash EVO which utilizes their 256Gb 48-Layer TLC 3D V-
memories that do not have a controller. Removable ash NAND.[59] In August 2016, Samsung announced a 32TB
memory cards and USB ash drives have built-in con- 2.5 SAS SSD based on their 512Gb 64-Layer TLC 3D
trollers to perform wear leveling and error correction so V-NAND. Further, Samsung expects to unveil SSDs with
use of a specic ash le system does not add any benet. up to 100TB of storage by 2020.[60]
9.2 Flash memory as a replacement for hard drives 9

8 Transfer rates The two types are not easily exchangeable, since they do
not have the same pinout, and the command sets are in-
Flash memory devices are typically much faster at reading compatible.
than writing.[61] Performance also depends on the quality
of storage controllers which become more critical when
devices are partially full.[61] Even when the only change 9.1.1 Firmware storage
to manufacturing is die-shrink, the absence of an appro-
priate controller can result in degraded speeds.[62] With the increasing speed of modern CPUs, parallel ash
devices are often much slower than the memory bus of
the computer they are connected to. Conversely, mod-
ern SRAM oers access times below 10 ns, while DDR2
9 Applications SDRAM oers access times below 20 ns. Because of
this, it is often desirable to shadow code stored in ash
9.1 Serial ash into RAM; that is, the code is copied from ash into RAM
before execution, so that the CPU may access it at full
Serial ash is a small, low-power ash memory that uses a speed. Device rmware may be stored in a serial ash de-
serial interface, typically Serial Peripheral Interface Bus vice, and then copied into SDRAM or SRAM when the
(SPI), for sequential data access. When incorporated into device is powered-up.[63] Using an external serial ash
an embedded system, serial ash requires fewer wires on device rather than on-chip ash removes the need for
the PCB than parallel ash memories, since it transmits signicant process compromise (a process that is good
and receives data one bit at a time. This may permit a for high-speed logic is generally not good for ash and
reduction in board space, power consumption, and total vice versa). Once it is decided to read the rmware in
system cost. as one big block it is common to add compression to al-
There are several reasons why a serial device, with fewer low a smaller ash chip to be used. Typical applications
external pins than a parallel device, can signicantly re- for serial ash include storing rmware for hard drives,
duce overall cost: Ethernet controllers, DSL modems, wireless network de-
vices, etc.
Many ASICs are pad-limited, meaning that the size
of the die is constrained by the number of wire
bond pads, rather than the complexity and number 9.2 Flash memory as a replacement for
of gates used for the device logic. Eliminating bond hard drives
pads thus permits a more compact integrated circuit,
on a smaller die; this increases the number of dies Main article: Solid-state drive
that may be fabricated on a wafer, and thus reduces
the cost per die. One more recent application for ash memory is as a re-
Reducing the number of external pins also reduces placement for hard disks. Flash memory does not have
assembly and packaging costs. A serial device may the mechanical limitations and latencies of hard drives,
be packaged in a smaller and simpler package than so a solid-state drive (SSD) is attractive when considering
a parallel device. speed, noise, power consumption, and reliability. Flash
drives are gaining traction as mobile device secondary
Smaller and lower pin-count packages occupy less storage devices; they are also used as substitutes for hard
PCB area. drives in high-performance desktop computers and some
servers with RAID and SAN architectures.
Lower pin-count devices simplify PCB routing.
There remain some aspects of ash-based SSDs that
There are two major SPI ash types. The rst type is make them unattractive. The cost per gigabyte of ash
characterized by small pages and one or more internal memory [64]
remains signicantly higher than that of hard
SRAM page buers allowing a complete page to be read disks. Also ash memory has a nite number of P/E
to the buer, partially modied, and then written back cycles, but this seems to be currently under control since
(for example, the Atmel AT45 DataFlash or the Micron warranties on ash-based SSDs are approaching those of
[65]
Technology Page Erase NOR Flash). The second type current hard drives. In addition, deleted les on SSDs
has larger sectors. The smallest sectors typically found can remain for an indenite period of time before being
in an SPI ash are 4 kB, but they can be as large as 64 overwritten by fresh data; erasure or shred techniques or
kB. Since the SPI ash lacks an internal SRAM buer, software that work well on magnetic hard disk drives have
the complete page must be read out and modied before no eect on SSDs, compromising security and forensic
being written back, making it slow to manage. SPI ash examination.
is cheaper than DataFlash and is therefore a good choice For relational databases or other systems that require
when the application is code shadowing. ACID transactions, even a modest amount of ash storage
10 13 REFERENCES

can oer vast speedups over arrays of disk drives.[66][67]

In June 2006, Samsung Electronics released the rst
ash-memory based PCs, the Q1-SSD and Q30-SSD,
both of which used 32 GB SSDs, and were at least ini-
tially available only in South Korea.[68]
A solid-state drive was oered as an option with the rst
Macbook Air introduced in 2008, and from 2010 on-
wards, all Macbook Air laptops shipped with an SSD.
Starting in late 2011, as part of Intel's Ultrabook initia-
tive, an increasing number of ultra thin laptops are being
shipped with SSDs standard. The aggressive trend of the shrinking process design rule or tech-
There are also hybrid techniques such as hybrid drive and nology node in NAND ash memory technology eectively ac-
celerates Moores Law.
ReadyBoost that attempt to combine the advantages of
both technologies, using ash as a high-speed non-volatile
cache for les on the disk that are often referenced, but 11 Flash scalability
rarely modied, such as application and operating system
executable les. Due to its relatively simple structure and high demand for
higher capacity, NAND ash memory is the most aggres-
sively scaled technology among electronic devices. The
heavy competition among the top few manufacturers only
9.3 Flash memory as RAM adds to the aggressiveness in shrinking the design rule or
process technology node.[30] While the expected shrink
As of 2012, there are attempts to use ash memory as the timeline is a factor of two every three years per original
main computer memory, DRAM.[69] version of Moores law, this has recently been accelerated
in the case of NAND ash to a factor of two every two
years.
As the feature size of ash memory cells reaches the
9.4 Archival or long-term storage minimum limit, further ash density increases will be
driven by greater levels of MLC, possibly 3-D stacking
It is unclear how long ash memory will persist under of transistors, and improvements to the manufacturing
archival conditionsi.e., benign temperature and humid- process. The decrease in endurance and increase in un-
ity with infrequent access with or without prophylactic correctable bit error rates that accompany feature size
rewrite. Anecdotal evidence suggests that the technol- shrinking can be compensated by improved error correc-
ogy is reasonably robust on the scale of years. Datasheets tion mechanisms.[76] Even with these advances, it may
of Atmels ash-based "ATmega" microcontrollers typi- be impossible to economically scale ash to smaller and
cally promise retention times of 20 years at 85 C and smaller dimensions as the number of electron holding ca-
100 years at 25 C.[70] pacity reduces. Many promising new technologies (such
as FeRAM, MRAM, PMC, PCM, ReRAM, and others)
An article from CMU in 2015 writes that Todays ash are under investigation and development as possible more
devices, which do not require ash refresh, have a typical scalable replacements for ash.[77]
retention age of 1 year at room temperature. And that
temperature can lower the retention time exponentially.
The phenomenon can be modeled by Arrhenius law.[71]
12 See also
List of ash le systems

10 Industry microSDXC (up to 2 TB)

Secure USB drive
One source states that, in 2008, the ash memory indus- Open NAND Flash Interface Working Group
try includes about US$9.1 billion in production and sales.
Other sources put the ash memory market at a size of Write amplication
more than US$20 billion in 2006, accounting for more
than eight percent of the overall semiconductor market
and more than 34 percent of the total semiconductor 13 References
memory market.[72] In 2012, the market was estimated
at $26.8 billion.[73] [1] A Flash Storage Technical and Economic Primer. ash-

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[17] Tadashi Yasufuku et al., Inductor and TSV Design of 20-
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[20] Ishida, K. et al., 1.8 V Low-Transient-Energy Adaptive
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Flash Memories. NASA Electronic Parts and Packag-
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for the charge pump and erase/write control have much
thicker oxides because of the requirement for high volt-
age. This causes ash devices to be considerably more
sensitive to total dose damage compared to other ULSI
technologies. It also implies that write and erase functions
will be the rst parameters to fail from total dose. ... Flash
memories will work at much higher radiation levels in the
read mode. ... The charge pumps that are required to gen-
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the most sensitive circuit functions, usually failing below
10 krad(SI).
[22] Zitlaw, Cli. The Future of NOR Flash Memory. Mem-
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[23] Samsung moves into mass production of 3D ash mem-
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[25] Micron Collaborates with Sun Microsystems to Extend
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[26] Taiwan engineers defeat limits of ash memory.
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[27] Flash memory made immortal by ery heat. theregis-
ter.co.uk.
[28] Flash memory breakthrough could lead to even more re-
liable data storage.
[29] TN-29-17 NAND Flash Design and Use Considerations
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[30] Kawamatus, Tatsuya. TECHNOLOGY FOR MAN-
AGING NAND FLASH (PDF). Hagiwara sys-com co.,
LTD. Retrieved 1 August 2011.
[31] Richard Blish. Dose Minimization During X-ray Inspec-
tion of Surface-Mounted Flash ICs. p. 1.
[32] Richard Blish. Impact of X-Ray Inspection on Spansion
Flash Memory.
12
[33] SanDisk Extreme PRO SDHC/SDXC UHS-I Memory
Card. Retrieved 2016-02-03.
[34] Samsung 32GB USB 3.0 Flash Drive FIT MUF-
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[35] Spansion. What Types of ECC Should Be Used on Flash
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[38] TN-29-07: Small-Block vs. Large-Block NAND ash
Devices Explains 512+16 and 2048+64-byte blocks
[39] AN10860 LPC313x NAND ash data and bad block
management Explains 4096+128-byte blocks.
[40] Thatcher, Jonathan (18 August 2009). NAND Flash
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[43] A list of ONFi members is available at http://onfi.org/
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[45] Dell, Intel And Microsoft Join Forces To Increase Adop-
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[46] See pages 57 of Toshibas NAND Applications Design
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[47] NAND Flash 101: An Introduction to NAND Flash and
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[48] Pavan, Paolo; Bez, Roberto; Olivo, Piero; Zanoni, Enrico
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[49] NAND Evolution and its Eects on Solid State Drive
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[50] A survey of address translation technologies for ash
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[52] http://www.convertunits.com/type/computer+data+
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[53] Shilov, Anton (12 September 2005). Samsung Unveils
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[54] Gruener, Wolfgang (11 September 2006). Samsung an-
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[55] SanDisk Media Center. sandisk.com.
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look_out_for_the_256gb_thumb_drive_and_the_
128gb_tablet.html; http://techcrunch.com/2009/07/20/
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[58] Borghino, Dario (March 31, 2015). 3D ash technology
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memory cells. Gizmag. Retrieved March 2015. Check
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[60] Samsung Unveils 32TB SSD Leveraging 4th Gen 64-
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[61] Master, Neal; Andrews, Mathew; Hick, Jason; Canon,
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[62] DailyTech - Samsung Conrms 32nm Flash Problems,
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[63] Many serial ash devices implement a bulk read mode and
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to congure them to transfer their entire contents to RAM
on power-up. When clocked at 50 MHz, for example, a
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[64] Lyth0s (17 March 2011). SSD vs. HDD. elitepcbuild-
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 13

[70] 8-Bit AVR Microcontroller ATmega32A Datasheet

Complete (PDF). 2016-02-19. p. 18. Retrieved 2016-
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[71] Data Retention in MLC NAND Flash Memory: Char-

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[72] Yinug, Christopher Falan (July 2007). The Rise of the

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[73] NAND memory market rockets, April 17, 2013, Nermin

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[76] Lal Shimpi, Anand (2 December 2010). Microns Clear-

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[77] Kim, Kinam; Koh, Gwan-Hyeob (16 May 2004). Future

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14 External links
New Pulse Measurement System For Semiconduc-
tor Device Characterization
Semiconductor Characterization System has diverse
functions
NAND Flash Applications Design Guide by
Toshiba, April 2003 v. 1.0
Understanding and selecting higher performance
NAND architectures
How ash storage works presentation by David
Woodhouse from Intel
Flash endurance testing
http://www.spansion.com/Support/Application%
20Notes/EnduranceRetention_AN.pdf
http://www.cse.scu.edu/~{}tschwarz/coen180/LN/
flash.html
NAND Flash Data Recovery Cookbook
14 15 TEXT AND IMAGE SOURCES, CONTRIBUTORS, AND LICENSES

15 Text and image sources, contributors, and licenses

15.1 Text
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Bebbington, Christian List, Aldie, Matusz, Maury Markowitz, LapoLuchini, Heron, Olivier, Edward, Patrick, Michael Hardy, Willsmith,
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Julesd, Salsa Shark, Glenn, Smack, Ronaldo Guevara, Technopilgrim, JidGom, RodC, Rainer Wasserfuhr~enwiki, Dcoetzee, Andrew-
man327, Colin Marquardt, Itai, Lkesteloot, ZeWrestler, Wernher, Thue, David.Monniaux, BenRG, Robbot, Sander123, RedWolf, Nurg,
Lowellian, Jondel, Wereon, Tea2min, Giftlite, Desplesda, DavidCary, Kenny sh, Panu-Kristian Poiksalo, Joconnor, Moogle10000, Ferdi-
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Sfoskett, Adrian Sampson, Neutrality, Qdr, Moxfyre, Corti, Grstain, PhotoBox, NightMonkey, Imroy, Discospinster, Brandon.irwin,
Alistair1978, Ailanto, ESkog, Ben Standeven, Plugwash, Evice, Marcok, Nrbelex, Bobo192, Collinong, Shenme, .:Ajvol:., Matt Britt,
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Morcheeba, DardanAeneas, E Wing, Pietdesomere, Dspradau, GraemeL, Dennisrd587~enwiki, Donhalcon, Pdraic MacUidhir, TuukkaH,
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