EE660: Computer Architecture Spring, 2017

Assignments 1 (Due: January 26, 2017)

Score: /100
Student: Kyle Yu, yu99@hawaii.eduDate: January 12, 2017

1-1 (20/100). [PH11], page 65, problem 1.9-a,b.

A.

Executing at current speed, you can save 50% of the energy.

B.

In accordance to the following:

Executing the task at the voltage should yield the dynamic energy, assuming no changes in the capacitive load.
Frequency is not proportional to the dynamic energy and should not have an effect.
 1-2 (40/100). [PH11], page C-82, problem C.1-a,b,c,d,e,f,g.

A.

Reg.

R1 LD DADDI

R1 DADDI SD

R2 LD DADDI

R2 SD DADDI

R2 DSUB DADDI

R4 BNEZ DSUB

B.

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8

LD F D X M W

DADDI F s s D X M W

SD F s s D X M W

DADDI F D X M W

DSUB F s s D X M W

BNEZ F s s D X M W

LD2 s s F D

End of iteration 1: R3 = R2 + 392

End of iteration 99: R3 = R2 + 0

99*16 + 2 = 1586 cycles

C.

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8

LD F D X M W

DADDI F D s X M W

SD F s D X M W

DADDI F D X M W

DSUB F D X M W

BNEZ F s D X M W

F s

LD2 F D X M W
 End of iteration 1: R3 = R2 + 392

End of iteration 99: R3 = R2 + 0

99*9 + 3 = 894 cycles

D.

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8

LD F D X M W

DADDI F D s X M W

SD F s D X M W

DADDI F D X M W

DSUB F D X M W

BNEZ F s D X M W

LD2 F D X M W

End of iteration 1: R3 = R2 + 392

End of iteration 99: R3 = R2 + 0

99*8 + 4 = 796 cycles

E.

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8

LD F1 F2 D1 D2 X1 X2 M1 M2 W1 W2

DADDI F1 F2 D1 D2 s s s X1 X2 M1 M2 W1 W2

SD F1 F2 D1 s s s D2 X1 X2 M1 M2 W1 W2

DADDI F1 F2 s s s D1 D2 X1 X2 M1 M2 W1 W2

DSUB F1 s s s F2 D1 D2 s X1 X2 M1 M2 W1 W2

BNEZ F1 F2 D1 s D2 X1 X2 M1 M2 W1

LD2 F1 F2 s D1 D2 X1 X2 M1 M2

End of iteration 1: R3 = R2 + 392

End of iteration 99: R3 = R2 + 0

9 + 98*10 + 10 = 999 cycles

F.

0.8+0.1 = 0.9, for 5 stage

0.8/2+0.1 = 0.5, for 10 stage

G.

796/ (99*6) = 1.34, CPI 5 stage

999 / (99*6) = 1.68, CPI 10 stage

1.34 0.9 = 1.21

1.68 0.5 = 0.84

1-3 (40/100). [PH11], page C-85, problem C.6-a,b,c,d,e.

A.
F D X M W >>
FDMXW

B.

Source Destination

MEM MEM

EX MEM

EX EX

MEM >> MEM

Data is Load to Store

EX >> EX
ALU to load or store

EX >> EX
ALU operations

C.
ADD R1, R2, R3
LD R4, 0 (R1)

ADD R1, R2, R3

SD 0 (R1), R4

D.

Original New

LD R2, 5(R1) ADD R3, R1, 5

LD R2, 0(R3)

This adds one more instruction to ADD the offset then LD in the
register.

Original New

LD R2, 5(R1) ADD R2, R1, 5

ADD R4, R3, R2 ADD R4, R3, 0(R2)

This is the same instruction count.
Original New

LD R2, 0(R1) ADD R4, R3, 0(R1)

ADD R4, R3, R2

This reduces the instruction count.

E.
If a load produces a value used for the next instruction, this causes a stall for the original pipeline, but not the new pipeline.
Therefore, we see a change in the CPI.

If an offset is required to be executed, MEM may get stalled. This causes a stall for the new pipeline, but not the original pipeline.
Therefore, we see a change in the CPI.