Beruflich Dokumente
Kultur Dokumente
MC 602
Circuitos Lgicos e Organizao de Computadores
IC/Unicamp
Captulo 3
Tecnologia de Implementao
MC602 Mario Crtes IC / Unicamp 1
IC-UNICAMP
Tpicos
Transistores
Portas NMOS
Portas CMOS
Lgica e positiva negativa
Circuitos comerciais
Atraso
Margem de rudo
Potncia
Buffer tri-state
valor lgico 0
VSS(Gnd)
Source Drain
(a) chave simples controlada por entrada x Substrate (Body)
VG
VS VD
x = "high" x = "low"
Drain Source
VDD
Substrate (Body)
(a) chave com comportamento
oposto ao slide anterior
(b) transistor PMOS
VG
VS VD
VS = 0 V chave aberta
chave fechada
quando VG = 0 V
quando VG = VDD
VDD VDD
VS = VDD
VD VD = VDD
VD
chave aberta chave fechada
quando VG = VDD quando VG = 0 V
R
R
+
5V Vf
- Vf
Vx
Vx
x f
x f
Vf 0 0 1
0 1 1
Vx
1
1 0 1
1 1 0
Vx
2
(a) Circuito
x1 x1
f f
x2 x2
x1 x2 f
Vf
0 0 1
Vx Vx 0 1 0
1 2
1 0 0
1 1 0
x1 x1
x2 f x2 f
Vx2
x1 x1
f f
x2 x2
(a) Circuito
VDD
entradas definem ou no
caminho entre Vf e terra
se Vf = 0, ento h potncia
esttica sendo dissipada
(VddGnd) Vf
Vx
1
Pull-down network
(PDN)
Vx
n
VDD
T1
Vx Vf
x T1 T2 f
T2
0 on off 1
1 off on 0
T1 T2
Vf
Vx T3 x1 x2 T1 T2 T3 T4 f
1
0 0 on on off off 1
0 1 on off off on 1
Vx T4 off on on off
2 1 0 1
1 1 off off on on 0
Vx T1
1
Vx T2
2
x1 x2 T1 T2 T3 T4 f
Vf
0 0 on on off off 1
T3 T4 0 1 on off off on 0
1 0 off on on off 0
1 1 off off on on 0
Vf
Vx
1
Vx
2
f = x1 + x2 . x3
como variveis esto
complementadas mapeamento
direto com PUN
f = x1 + x2 . x3
Vx
1
Vx
3
x1
x2 f
x3
MC602 Mario Crtes IC / Unicamp 17
IC-UNICAMP
Outra porta complexa CMOS V DD
Vx
1
x1 Vx
x4 f 2
x2
x3 Vx
3
Vx
4
x1 x2 f = x1 x2
0 0 0 x1
0 1 1 f = x1 x 2
x2
1 0 1
1 1 0
(b) Smbolo
x1
x2
f = x1 x2
x1 x2 f = x1 x2
0 0 1 x1
0 1 0 f = x1 x 2
x2
1 0 0
1 1 1
(b) Smbolo
x1
x2
f = x1 x2
H=high
lgica positiva
L 0 Vf Vx Vx Vf
1 2
H 1
Vx L L H
1
L H H
lgica negativa H L H
H H L
L 1 Vx
2
H 0
Lgica Positiva
MC602 Mario Crtes IC / Unicamp 21
Duas interpretaes para
IC-UNICAMP
um mesmo circuito
x1 x2 f
Vx Vx Vf 0 0 1 x1
1 2
0 1 1 f
x2
L L H 1 0 1
L H H 1 1 0
H L H
H H L
(b) Tabela verdade com lgica positiva e smbolo lgico
1 1 0 x1
1 0 0 f
x2
0 1 0
0 0 1
VDD
Gnd
7404
7408 7432
x1
x2
x3
f
Logic gates
Entradas and Sadas
(variveis lgicas) programmable (funes lgicas)
switches
x1 x2 xn
Baseada em SOP
Todas entradas
disponveis (verdadeiro
buffers de
e complementado) entrada e
inversores
Sadas do plano AND:
Produtos P1 a Pk x1 x1 xn xn
Sadas do plano OR:
somas de Produtos = P1
f1 fm
MC602 Mario Crtes IC / Unicamp 27
IC-UNICAMP
PLA: viso no nvel de gate
x1 x2 x3
Programmable
connections
OR plane
P1
P2
P3
P4
AND plane
f1 f2
plano OR
P1
P2
P3
P4
plano AND
f1 f2
MC602 Mario Crtes IC / Unicamp 29
IC-UNICAMP
Estrutura de uma CPLD tpica
I/O block
I/O block
PAL-like PAL-like
block block
Interconnection wires
I/O block
I/O block
PAL-like PAL-like
block block
se Vx = 5V Vf = VOL
R
Vx RDS
RDS
VOL = VDD.
RDS + R
(a) inversor NMOS (b) Vx = 5 V
VDD
valor lgico 1
V1,min
Indefinido
V0,max
valor lgico 0
VSS(Gnd)
Forbidden VIH
Zone VIL
VO L NML
Logic Low
Logic Low Input Range
Output Range
GND
A Y
V(Y)
V
Output Characteristics Input Characteristics
DD VDD
V
OH
VO H NMH
Forbidden VIH
Zone VIL
Unity Gain
Points
VO L NML
V Slope = 1
OL
V (A )
0
V V V GND
IL IH DD
V OH = V DD Slope = 1
V OL = 0 V
VT V IL V IH ( V DD V T ) V DD
Vx
V DD
2
MC602 Mario Crtes IC / Unicamp 36
Margem de rudo para
IC-UNICAMP
algumas tecnologias
Outra vantagem do CMOS
ID Vx ID
Vf
Vf
Vx
VDD VDD
VA
Vx
Vf
Vx
50% 50%
Gnd
VDD
90% 90%
VA 50% 50%
tr tf
VDD
Vx Vf
(a) implementao
x f
(b) smbolo
MC602 Mario Crtes IC / Unicamp 42
IC-UNICAMP
Buffer tri-state
e e= 0
x f
x f
e= 1
(a) Buffer tri-state x f
e x f
0 0 Z e
0 1 Z
1 0 0
x f
1 1 1