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SystemVerilog Assertions
Introduction to SVA
Harry Foster
info@verificationacademy.com | www.verificationacademy.com
Lecture Overview
2 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
LINEAR FORMALISM
Brief Review of LTL and Introduction of Regular Expressions
SystemVerilog Assertions
4 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
Xp p
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Fp p
Gp p p p p p p
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pUq p p p p q
pWq p p p p p p
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Weak operators X, G, W
Used to express safety properties,
i.e. something bad never happens
Strong operators F, U
Used to express liveness properties,
i.e. something good eventually happens
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For example.
G ( request F grant )
request grant
p p p p p p
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For example.
G ( request F grant )
FG p
p p p
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Counting example:
p is asserted in every even cycle
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Regular Expressions
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Regular Expressions
(1`b1 ## p)[*]
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Linear Formalisms
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Directives
(assert, cover) assert, assume, cover
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Assertion clk
Units
Directives
(assert, cover) rst_n
Properties
!(grant0 & grant1)
Sequences
(Sequential Expressions)
error
Boolean Expressions
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nexttime p p
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eventually p p
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always p p p p p p p
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p s_until q p p p p q
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25 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
SEQUENCES
Sequences
So far we have examined LTL-based
assertions
We now we introduce SVA sequences
Multiple Boolean expressions are evaluated
Assertion
Directives
(assert, cover)
Properties
Sequences
(Sequential Expressions)
Boolean Expressions
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Sequence
Temporal delay ##n with an integer n.
clk
start
transfer
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Sequence
Temporal delay ##n with an integer n.
clk
start
transfer
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Sequence
Temporal delay ##[m:n] with range [m:n]
clk
start
transfer
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Sequence
Consecutive repetition [*m] or range [*m:n]
- Use $ to represent infinity
clk
start
transfer
31 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
Sequence
Consecutive repetition [*m] or range [*m:n]
- Use $ to represent infinity
clk
start
transfer
32 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
Sequence
Consecutive repetition [*m] or range [*m:n]
- Use $ to represent infinity
clk
start
transfer
33 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
Sequence
Consecutive repetition [*m] or range [*m:n]
- Use $ to represent infinity
clk
start
transfer
Sequence
Non-consecutive repetition [=m] or [=m:n]
clk
start
[*] represents
zero to infinity
transfer
start[=2] !start[*] ##1 start ##1 !start[*] ##1 start ##1 !start[*]
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Sequence
Goto non-consecutive repetition [->m] or [->m:n]
clk
start
[*] represents
zero to infinity
transfer
36 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
Properties
Assertion
Units
Directives
(assert, cover)
Properties
Sequences
(Sequential Expressions)
Boolean Expressions
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Properties
Overlapping sequence implication operator |->
clk
ready
start
go
done
assertion property ( @(posedge clk) ready ##1 start |-> go ##1 done );
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Properties
Non-overlapping sequence implication operator |=>
clk
ready
start
go
done
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req[0] gnt[0]
req[1]
Arbiter gnt[1]
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a_0_fair:
assert property (@(posedge clk) disable iff (reset_n)
$rose(req[0]) |-> not (!gnt[0] throughout (gnt[1])[->2]));
clk
req[0]
req[0] gnt[0]
req[1]
Arbiter gnt[1]
gnt[0]
gnt[1]
41 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
a_0_fair:
assert property (@(posedge clk) disable iff (reset_n)
req[0] |-> not (!gnt[0] throughout (gnt[1])[->2]));
clk
req[0]
req[0] gnt[0]
req[1]
Arbiter gnt[1]
gnt[0]
gnt[1]
42 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
a_0_fair:
assert property (@(posedge clk) disable iff (reset_n)
$rose(req[0]) |-> not (!gnt[0] throughout (gnt[1])[->2]));
clk
req[0]
req[0] gnt[0]
req[1]
Arbiter gnt[1]
gnt[0]
gnt[1]
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a_1_fair:
assert property (@(posedge clk) disable iff (reset_n)
$rose(req[1] |-> not (!gnt[1] throughout (gnt[0])[->2]));
clk
req[0]
req[0] gnt[0]
req[1]
Arbiter gnt[1]
gnt[0]
gnt[1]
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sequence s_op_retry;
(req ##1 retry);
endsequence
sequence s_cache_fill(req, done, fill);
(req ##1 done [=1] ##1 fill);
endsequence
45 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
sequence s_op_retry;
(req ##1 retry);
endsequence
sequence s_cache_fill(rdy, done, fill);
(rdy ##1 done [=1] ##1 fill);
endsequence
assert property ( @(posedge clk) disable iff (!reset_n)
s_op_retry |=> s_cache_fill (my_rdy,my_done,my_fill));
46 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
47 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
Action blocks
An SVA action block specifies the actions that are
taken upon success or failure of the assertion
The action block, if specified, is executed
immediately after the evaluation of the assert
expression
assert property ( @(posedge clk) disable iff (reset)
!(grant0 & grant1) )
else begin // action block fail statement
$error(Mutex violation with grants.);
end
48 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
System functions
$onehot (<expression>)
- Returns true if only one bit of the expression is high
$onehot0 (<expression>)
- Returns true if at most one bit of the expression is high
$isunknown (<expression>)
- Returns true if any bit of the expression is X or Z
- This is equivalent to ^<expression> === bx
49 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
System functions
$rose( expression )
$fell( expression )
$stable( expression )
$past( expression [, number_of_ticks] )
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clk
start
transfer
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clk
start
transfer
52 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
Introduction to SVA
FIFO
clk clk
rst_n rst_n A
Controller data_in data_out
put full
get empty
A
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Introduction to SVA
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This says every clock we see req, followed by gnt, followed by done
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Control
Bridge
CPU 1 CPU 2 Datapath UART
FIFO
Bus A Bus B
Arbiter I/F I/F
Datapath
Memory Graphics
FIFO Timer
Controller Controller
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clk
rst_n
sel[0]
en
I/F addr
I/F
write
rdata
wdata
Master Slave 0
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0 1 2 3 4
addr Addr 1
write
sel[0]
en
wdata Data 1
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0 1 2 3 4
addr Addr 1
write
sel[0]
en
rdata Data 1
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no transfer
INACTIVE
sel[0] == 0
en == 0
setup
no transfer START
sel[0] == 1
en == 0
transfer setup
ACTIVE
sel[0] == 1
en == 1
61 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
Interface Requirements
p_no_error_state Bus state must be valid: !(se==0 & en==1) no transfer START
sel[0] == 1
en == 0
p_sel_stable Slave select signals remain stable from START to ACTIVEACTIVE sel[0] == 1
en == 1
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bus_reset = 0; START
no transfer
bus_inactive = ~sel & ~en; sel[0] == 1
en == 0
end
`endif
63 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
SVA Examples
property p_valid_inactive_transition;
@(posedge clk) disable iff (bus_reset)
( bus_inactive) |=>
((bus_inactive) || (bus_start));
endproperty
a_valid_inactive_transition:
assert property (p_valid_inactive_transition); INACTIVE
sel[0] == 0
en == 0
endproperty transfer
setup
a_valid_start_transition:
ACTIVE
assert property (p_valid_start_transition); sel[0] == 1
en == 1
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65 H Foster, EE 382M, Verification of Digital Systems, Spring 2017 Mentor Graphics Corporation, all rights reserved.
CHECKER PACKAGING
Directives
(assert, cover) assert, assume, cover
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SVA Checker
Binding Checkers
SUMMARY
Lecture Recap
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SystemVerilog Assertions
Introduction to SVA
Harry Foster
Chief Scientist Verification
info@verificationacademy.com | www.verificationacademy.com