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D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Opcode w 1 1 REG R/M
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Opcode w MOD=00 REG R/M
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Opcode MOD REG R/M
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Lower byte Higher byte
displacement
MOD=01 for 8 bit displacement
MOD=10 for 16 bit displacement
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Opcode MOD=11 Opcode R/M
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Lower byte Higher byte
Immediate data
Displacement
(see next page)
Immediate data
REG Codes:
Register
Code w=0 w=1
---------------------------------------------------
000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI
Segment Register Codes:
Code Segment register
------------------------------------------------
00 ES
01 CS
10 SS
11 DS
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 1 0 d w 1 1 REG R/M
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 1 0 d=1 w=0 1 1 0 1 1 0 0 1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 0 1 0 d=0 w=0 1 1 0 0 1 0 1 1
8 bit operand
Therefore, MOV BL, CL = 88CBH
2) ADD AX, BX
Opcode for ADD = 000000dw MOD REG R/M
d will be 1 since destination is a register
w will be 1 for 16 bit operands (AX and BX)
REG gives destination, destination is AX, therefore REG = code of AX = 000
R/M gives source, source is BX, therefore R/M = code of BX = 011
Register to Register type of operation, therefore MOD = 11
ADD AX, BX = 00000011 11000011 = 03C3H
Same instruction can be coded as follows:
d will be 0 since source is a register
w will be 1 for 16 bit operands (AX and BX)
REG gives source, source is BX, therefore REG = code of BX = 011
R/M gives destination, destination is AX, therefore R/M = code of AX = 000
Register to Register type of operation, therefore MOD = 11
ADD AX, BX = 00000001 11011000 = 01D8H
3) MOV [SI], DL
Opcode = 100010dw MOD REG R/M
d = 0, REG field gives source. Source is DL register and its code is 010, therefore, REG = 010
w = 0, 8 bit operands
MOD = 00, the instruction is not having any displacement
R/M gives destination. Destination is [SI] and its code is 100, therefore, R/M = 100
MOV [SI], DL = 10001000 00010100 = 8814H
to some another location e.g. CALL, RET, JMP instructions. The addressing modes for the sequential
and control transfer instructions are as follows:
1) Immediate:
In this type of addressing mode, data is available in the instruction itself e.g.
MOV AX, 5000H
ADD BX, 1020H
2) Direct:
In this addressing mode a 16 bit offset address is directly specified in the instruction e.g.
MOV AX, [5000H]
3) Register:
In this mode, data is stored in registers and it is referred using registers e.g.
MOV AX, BX
ADD AL, CL
4) Register Indirect:
In this mode, the operand is specified indirectly using some register. The contents of register point to
some memory location in Data Segment or Extra Segment. The registers used to specify memory
location are BX, SI, DI, BP e.g.
MOV AX, [BX]
In the above instruction, the contents of register BX will be used as offset in data segment. From that
offset two bytes will be transferred to AX.
INC BYTE PTR [SI]
In the above instruction, the contents of memory location pointed by SI in data segment will be
incremented by 1.
Suppose SI = 1000H
5) Indexed:
In this mode offset of operand is stored in either SI or DI register. This is a form of register indirect
addressing mode e.g.
MOV AX, [SI]
6) Register relative:
In this addressing mode, effective address of data is formed by adding 8 bit or 16 bit displacement
with the contents of BX, BP, SI, or DI registers e.g.
MOV AX, 50H [BX]
7) Based Indexed:
In this addressing mode, the effective address of data is formed by adding contents of base register
(BX or BP) to the contents of an index register (SI, DI) e.g.
MOV AX, [BX] [SI]
8) Relative Based Indexed:
The effective address of data, in this mode, is formed by adding an 8 bit / 16 bit displacement to the
sum of contents of any one base register(BX or BP) and any one index register (SI or DI) e.g.
MOV AX, 1000H [BX] [SI]
These instructions transfer execution control to specified address. Cal, jump, return and
interrupt instructions belong to this category.
4) Loop instructions:
These instructions are used to implement conditional or unconditional loops. The loop count is
stored in CX register e.g. LOOP, LOOPZ, LOOPNZ instructions.
5) Machine control instructions:
These instructions are used to control 8086 microprocessor itself e.g. NOP, HLT, WAIT and
LOCK instructions.
6) Flag manipulation instructions:
These instructions are used to set or reset flags of 8086 e.g. STC, CLC, CMC, STI, CLI, CLD,
STD instructions.
7) Shift and Rotate instructions:
These instructions are used to shift or rotate the bits of operand in either right or left direction.
CL register can be used to store the count of shift/rotate operation.
8) String instructions:
These instructions are used to perform string manipulation operations such as load, move,
store, scan, compare etc.
PUSH DS
PUSH [2000H]
PUSH AL ; Not allowed since AL is 8 bit register, ALWAYS a WORD
POP DS
POP CS ; This is not allowed
POP [5000H]
4) XCHG: Exchange
General form: XCHG destination, source
This instruction exchanges contents of source and destination.
Source and destination both cannot be memory locations.
Source and destination must be of same size (i.e. both must be bytes or both must be words).
Segment register cannot be used with this instruction.
No flags are affected by this instruction.
Examples:
XCHG AX, DX
XCHG BL, CL
XCHG [5000H], AX
This instruction is used to translate a byte from one code to another code.
It replaces a byte in AL register with a byte pointed by BX in a lookup table in memory.
Before using this instruction lookup table must be present in memory. Starting address of table
is loaded in BX register. The byte to be translated is loaded in AL.
AL DS : [ BX + AL ]
The value in AL is added to BX. This new value will be used as pointer in data segment.
From the location, pointed by [BX+AL], data will be transferred to AL.
No flags are affected by this instruction.
Following example shows how to find ASCII value of a decimal digit (0 9) present in AL.
DATA SEGMENT
ASCII_CODES DB 30H,31H,32H,33H,34H,35H,36H,37H,38H,39H
DIGIT DB 05 ; Find ASCII code of 5
RES DB ? ; To store the result i.e. ASCII code
DATA ENDS
CODE SEGMENT
MAIN:
MOV AX, DATA ; Initialize data segment
MOV DS, AX
END MAIN
Example:
PUSHF
Example:
POPF
Arithmetic instructions:
1) ADD: Add
General form: ADD destination, source
This instruction adds a number from source to destination. The result is available in
destination.
The source may be an immediate number, a register or a memory location.
The destination may be a register or a memory location.
Both source and destination cannot be memory locations.
The size of source and destination must be same i.e. both must be bytes or both must be words.
Segment registers cannot be used.
Flags affected: All condition flags (A, C, O, P, S, Z).
Examples:
ADD AL, 67H
ADD DX, BX
ADD AX, [SI]
ADD BX, [5000H]
ADD [BX], 79H
ADC AX, BX
ADC AH, 67H
ADC BX, [SI]
ADC CX, [5000H]
ADC [BX], 23H
3) SUB: Subtract
4) SBB: Subtract with Borrow
General form: SUB destination, source
SBB destination, source
These instructions subtract a number in source from number in destination.
The source may be an immediate number, a register or a memory location.
The destination can be a register or a memory location.
Both source and destination can not be memory locations.
The size of source and destination must be same i.e. both must be bytes or both must be words.
In case of SBB, borrow flag (i.e. Carry flag) and source will be subtracted from destination and
result is placed in destination.
In case of SUB, only source will be subtracted from destination and result is placed in
destination.
destination = destination - source
All condition flags are affected by these instructions.
Examples:
SUB AX, BX
SUB AH, 67H
SUB BX, [SI]
SUB CX, [5000H]
SUB [BX], 23H
5) INC: Increment
General form: INC destination
This instruction increments the destination by 1.
The destination may be a register or a memory location.
Immediate operand is not allowed.
Flags affected: A, O, P, S and Z. Carry flag is not affected by this instruction.
Examples:
INC BL
INC CX
INC BYTE PTR [BX]
INC WORD PTR [BX]
6) DEC: Decrement
General form: DEC destination
This instruction subtracts 1 from destination.
The destination may be a register or a memory location.
Immediate operand cannot be used.
Flags affected: A, O, P, S and Z. Carry flag is not affected by this instruction.
Examples:
DEC CL
DEC BP
DEC BYTE PTR [SI]
DEC WORD PTR [BX]
DEC COUNT ; COUNT is a variable
7) CMP: Compare
General form: CMP destination, source
This instruction compares destination and source.
Both can be byte operands or both can be word operands.
The source can be an immediate number, a register or a memory locatin.
The destination can be a register or a memory location.
Both operands cannot be memory operands.
Comparison is done by subtracting the source from destination (destination source). Source
and destination remain unchanged.
All condition flags are affected to indicate the result of operation.
For example,
CMP CX, BX
i) If CX = BX CF = 0, ZF = 1, SF = 0
ii) If CX > BX CF = 0, ZF = 0, SF = 0
iii) If CX < BX CF = 1, ZF = 0, SF = 1
CMP AL, 01H
CMP BH, CL
CMP DX, NUM1
DAA ; C>9
7C + 06 = 82
ii) Let AL = 73, CL = 29
ADD AL, CL ; AL 73 + 29 = 9C
DAA ; C>9
9C + 06 = A2
A>9
A2 + 60 = 02 in AL and CF = 1
Examples:
IMUL BX
IMUL AX
IMUL WORD PTR [SI]
2) OR: Logical OR
AL after execution:
AL before execution:
AL after execution:
2) SHR DX, CL
For multiple byte/multiple word moves, the number of elements to be moved is put in CX
register. It acts as counter.
After a byte/word move, SI and DI are automatically adjusted to point to next source and
destination byte/word.
If Direction Flag (DF) = 0, SI and DI will be automatically incremented by 1 for byte move
(MOVSB) and incremented by 2 for word move (MOVSW).
If DF = 1, then SI and DI will be automatically decremented.
No flags are affected.
DS : SI ES : DI
2) HLT: Halt the processor. To make it come out of halt, state reset it or interrupt it.
3) NOP: No operation, microprocessor will not perform any operation for 4 clock cycles. IP will be
incremented by 1. This instruction can be used in delay loops.
4) ESC: Escape to external device like 8087
5) LOCK: Lock the bus
It is a prefix, when used with some instruction, the buses are locked till the instruction is
executed completely. No other bus master can gain the access of buses.