1) Based & Relative addressing modes are suitable for program relocation at runt

ime.
2) Vectored Interrupts are not possible but multiple Interrupting devices are po
ssible in a CPU having a single
Interrupt request line & grant line.
3) Swap space in the disc used for saving process data.
4) Increasing the RAM of a computer typically Improves performance because fewer
page faults occur.
5) For a magnetic disk with concentric circular tracks, the latency is not linea
rly proportional to the seek distance
due to higher capacity of tracks on the periphery of the platter.
6) The amount of Increment depends on the size of the data Item accessed.
7) Return from Exception (RFE) on a general purpose processor= It must be a trap
& privileged Instruction & an exception cannot be allowed to occur during e
xecution of an RFE Instruction.
8) To hold between two cache level L1 & L2 in a multilevel cache hierarchy, the
L2 cache must be atleast as large
as the L1 cache.
9) Pipelined processor= Bypassing cannot handle all raw hazards. Register renami
ng cannot eliminate all register
carrier WAR hazards. Control hazard penalties cannot be eliminated by dynami
c branch prediction.
10) The use of multiple register windows with overlap cause a reduction in the n
o of memory accesses for
Instruction fetches.
11) In an Instruction execution pipeline, the earliest that the data translation
lookaside buffer (TLB) can be
accessed is during effective address calculation.
12) A CPU generally handles an Interrupt by executing an Interrupt service routi
ne by checking the Interrupt
register after finishing the execution of the current Instruction.
13) The decimal value 0.5 in IEEE single precision floating point representation
has fraction bits of 100...000 and
exponent value of 0.
14) The amount of ROM needed to Implement at 4-bit multiplier is 2 Kbits.
15) Register renaming is done in pipelined processors to handle certain kinds of
hazards.