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I2C slave method 1
Information

TherearetwowaystocreateanI2CslaveinanFPGAorCPLD.
FPGA projects Basic
1.UsingdirectlytheSCLlineasaclocksignalinsideyourFPGA/CPLD
Musicbox 2.UsingafastclocktooversampletheSDAandSCLsignals
LEDdisplays
Thefirstmethodallowscreatingacompactdesign.Butitisnotasreliableasthesecondmethod.
Ponggame
Example of I2C slave: IO extender, using method 1 SCL as a clock in the FPGA/CPLD
R/Cservos

TextLCDmodule Here'saviewofourIOextender.

Quadraturedecoder

PWMandonebitDAC

Debouncer

Crossingclockdomains

Theartofcounting
TheI2Cslavemoduleisconnectedtoasmall8bitsmemorythatcanbereadandwrittenfromtheI2Cbus.The
Externalcontributions 8bitsarealsoexportedoutsidetheFPGA/CPLD.ThatcreatesanI2CIOextender.

Firstthemoduledeclaration.
FPGA projects
Interfaces moduleI2CslaveWith8bitsIO(SDA,SCL,IOout);
inoutSDA;
RS232 inputSCL;
output[7:0]IOout;
JTAG
Thenthe7bitsaddressthatwewantforourI2Cslave.
I2C
parameterI2C_ADR=7'h27;
EPP
Thenthestartandstopconditionsdetectionlogic.
SPI
That'sthe"blackmagic"partofthisdesign...
SDcard
//Weusetwowireswithacombinatoriallooptodetectthestartandstopconditions
PCI //...makingsurethesetwowiresdon'tgetoptimizedaway
PCIExpress wireSDA_shadow/*synthesiskeep=1*/;
wirestart_or_stop/*synthesiskeep=1*/;
Ethernet
assignSDA_shadow=(~SCL|start_or_stop)?SDA:SDA_shadow;
HDMI assignstart_or_stop=~SCL?1'b0:(SDA^SDA_shadow);

SDRAM
regincycle;
always@(negedgeSCLorposedgestart_or_stop)
FPGA projects if(start_or_stop)incycle<=1'b0;elseif(~SDA)incycle<=1'b1;
Advanced NowwearereadytocounttheI2Cbitscomingin

Digitaloscilloscope reg[3:0]bitcnt;//countstheI2Cbitsfrom7downto0,plusanACKbit
wirebit_DATA=~bitcnt[3];//theDATAbitsarethefirst8bitssent
GraphicLCDpanel
wirebit_ACK=bitcnt[3];//theACKbitisthe9thbitsent
DirectDigitalSynthesis regdata_phase;
CNCsteppers
always@(negedgeSCLornegedgeincycle)
SpocCPUcore if(~incycle)
begin
Handson bitcnt<=4'h7;//thebit7isreceivedfirst
data_phase<=0;
Asimpleoscilloscope end
else

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3/31/2017 fpga4fun.comI2Cslave(method1)
begin
FPGA introduction if(bit_ACK)
Close begin
bitcnt<=4'h7;
data_phase<=1;
end
else
Home bitcnt<=bitcnt4'h1;
end
Welcome
anddetectiftheI2Caddressmatchesourown
Information
wireadr_phase=~data_phase;
FPGA projects Basic regadr_match,op_read,got_ACK;
//sampleSDAonposedgesincetheI2Cspecspecifiesaslowas0sholdtimeonnegedge
Musicbox regSDAr;always@(posedgeSCL)SDAr<=SDA;
reg[7:0]mem;
LEDdisplays
wireop_write=~op_read;
Ponggame
always@(negedgeSCLornegedgeincycle)
R/Cservos
if(~incycle)
TextLCDmodule begin
Quadraturedecoder got_ACK<=0;
adr_match<=1;
PWMandonebitDAC op_read<=0;
Debouncer end
else
Crossingclockdomains
begin
Theartofcounting if(adr_phase&bitcnt==7&SDAr!=I2C_ADR[6])adr_match<=0;
if(adr_phase&bitcnt==6&SDAr!=I2C_ADR[5])adr_match<=0;
Externalcontributions
if(adr_phase&bitcnt==5&SDAr!=I2C_ADR[4])adr_match<=0;
if(adr_phase&bitcnt==4&SDAr!=I2C_ADR[3])adr_match<=0;
FPGA projects if(adr_phase&bitcnt==3&SDAr!=I2C_ADR[2])adr_match<=0;
Interfaces if(adr_phase&bitcnt==2&SDAr!=I2C_ADR[1])adr_match<=0;
if(adr_phase&bitcnt==1&SDAr!=I2C_ADR[0])adr_match<=0;
RS232 if(adr_phase&bitcnt==0)op_read<=SDAr;
//wemonitortheACKtobeabletofreethebuswhenthemasterdoesn'tACKduringareadoperation
JTAG
if(bit_ACK)got_ACK<=~SDAr;
I2C
if(adr_match&bit_DATA&data_phase&op_write)mem[bitcnt]<=SDAr;//memorywrite
EPP
end
SPI
anddrivetheSDAlinewhennecessary.
SDcard
wiremem_bit_low=~mem[bitcnt[2:0]];
PCI
wireSDA_assert_low=adr_match&bit_DATA&data_phase&op_read&mem_bit_low&got_ACK;
PCIExpress wireSDA_assert_ACK=adr_match&bit_ACK&(adr_phase|op_write);
wireSDA_low=SDA_assert_low|SDA_assert_ACK;
Ethernet
assignSDA=SDA_low?1'b0:1'bz;
HDMI
assignIOout=mem;
SDRAM
endmodule

FPGA projects
What's the result?
Advanced
Thecodehasbeentestedinmultipledevices(XilinxFPGA,AlteraFPGA/CPLD),withanhardmacroI2Cmaster
Digitaloscilloscope (Dragonboard).
Thecompletecodeisavailablehere.
GraphicLCDpanel

DirectDigitalSynthesis Thiscodehastwodrawbacks:

CNCsteppers TheSCLsignalisusedasaclockintheFPGA/CPLD.TheuseofaSchmitttriggerontheSCLinputpinis
stronglyrecommendedtoavoiderraticbehavior(withoutSchmitttrigger,anynoiseorringingontheSCL
SpocCPUcore
linemayintroduceextraclockcycles,whichwouldbreakthefunctionality).
Thestartandstopconditionsdetectionlogicusesacombinatorialfeedbackloop,whichisnota
Handson recommendedpractice.Samethingonthe"incycle"signalthatisusedasasynchronousresetbytherest
ofthelogic.Thesearethepricetopaytoavoidusinganoversamplingclock.
Asimpleoscilloscope

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3/31/2017 fpga4fun.comI2Cslave(method1)
Ifyoucanlivewiththesedrawbacks,yougetaverycompactI2Cslavedesign.
FPGA introduction Otherwise,useanexternalclocktooversampleSDAandSCL(method2).Thisway,glitchescanbefilteredout
Close usingdigitalfilters,andthestartandstopconditiondetectedeasily(atthepriceofamorecomplexdesign).

External contributions
Contributedbyanfpga4funreaders...

Home I2CsimulationinVerilog
I2CslaveinVHDL
Welcome

Information

FPGA projects Basic


Musicbox

LEDdisplays

Ponggame

R/Cservos

TextLCDmodule

Quadraturedecoder

PWMandonebitDAC

Debouncer

Crossingclockdomains

Theartofcounting

Externalcontributions

FPGA projects
Interfaces
RS232

JTAG

I2C

EPP

SPI

SDcard

PCI

PCIExpress

Ethernet

HDMI

SDRAM

FPGA projects
Advanced
Digitaloscilloscope

GraphicLCDpanel

DirectDigitalSynthesis

CNCsteppers

SpocCPUcore

Handson
Asimpleoscilloscope

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