Trka 64d84br Datasheet D

Power System Sequencer
TRKA-64D84BR
January 13, 2014 Bel Power Inc., a subsidiary of Bel Fuse Inc.
On Board Power System Controller RoHS Compliant Rev. D
Features
Digital Signal Processor (DSP) Based with Bel Firmware
Provides Power Up and Power Down Sequencing Logic
Stand Alone or Command Based Feature Set
Fault Detection and Reporting
64-Pin 10mm x 10mm TQFP package
I2C, SMBus, or PMBus compatible serial interface options
Configurable through serial interface, Customizable through software
3V3 logic levels
Voltage Margining via Closed Loop Trim
Analog Input Monitoring
Programmed parameters saved in non-volatile memory
Intelligent configuration capability
Power-down data log for identifying fault conditions
Boot loader for in-system upgrading
Applications
Data Storage Servers
Networking
Telecommunications
Description
This on board power system controller provides a cost effective high performance solution for controlling,
monitoring, and sequencing multiple Point of Load (POL) converters on a system board. A functional block
diagram is shown in Figure 1. The sequencer uses a digital signal processor (DSP) engine and Bels firmware
to implement a portfolio of board level control features typically required in a multiple voltage power system.
This device can control and monitor up to eight PoL converters and monitor up to four analog inputs and
supports two independent zones. See the Theory of Operation section for additional details.
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 Tel 201-432-0463 Fax 201-432-9542 www.belfuse.com
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TRKA-64D84BR
Digital I/Os
Enable, Margin Up/Down, Reset In,
Power Good Out, Reset Out, etc.
Power System External Reference

Controller
Analog Vin Monitor
Voltage
Monitoring Other voltages to monitor
(analog inputs)
PoL Vout Monitors (1-8)
Digital I/O
Control
Vin
Main Active Trim PoL Trim PWM (1-8)

Engine Control Trim
(PWM outputs)
I2C PoL Converters

1 of 8 Vout
Clock I2C Engine
Data
Enable
GND
Sequence
Up/Down
Control
Internal (digital outputs) PIF Enables
Flash
(board
configuration
data,
fault log)
Figure 1
Functional Block Diagram
I/O Assignment Summary

I/O Type Quantity Signals
Analog Input 14 Vin, PoL 1-8, Analog x-y, Analog A-B, Board Inserted
Digital Input 12 External Event, Reset, Enable, Mfg Mode, Margin (2), Board ID (6)
Digital Output 13 PoL Enables 1-8, PIF Enable (2), Power Good (2), Reset Out
PWM Output 8 PoL 1-8
External Reference 2 VREF-, VREF+
I2C Communication 2 I2C Data, I2C Clock
Power 10 VDD, VSS, AVDD, AVSS, VCAP/VDDCORE
Programming 3 MCLR, PGD, PGC
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TRKA-64D84BR
I/O Definitions
Pin Function I/O Type 5V Tolerant
1 PoL 7 Enable Digital Output
3 External Event Digital Input
4 PIF Enable Zone A Digital Output Y
5 Margin Lo Digital Input Y
6 Margin Hi Digital Input Y
7 MCLR Programming Y
8 Enable Zone B Digital Input Y
9 VSS Power
10 VDD Power
11 PoL Monitor 4 Analog Input
15 Reference Return External Reference
16 3.0V Reference Input External Reference
19 AVDD Power
20 AVSS Power
23 Board Inserted Analog Input
24 Analog A Monitor Analog Input
25 VSS Power
26 VDD Power
27 Analog B Monitor Analog Input
28 Vin Monitor Analog Input
29 Analog x Monitor Analog Input
30 Analog y Monitor Analog Input
31 Board ID4 Digital Input Y
36 I2C Data I2C Communication Y
37 I2C Clock I2C Communication Y
38 VDD Power
39 Power Good Zone A Digital Output
41 VSS Power
42 Power Good Zone B Digital Output Y
43 Mfg Mode Digital Input Y
44 Reset Out Digital Output Y
45 Reset In Digital Input Y
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TRKA-64D84BR
Pin Function I/O Type 5V Tolerant
46 PoL 1 Margin PWM PWM Output Y
47 PGD Programming
48 PGC Programming
56 VDD Core Cap Power
57 VDD Power
58 PIF Enable Zone B Digital Output Y
The voltage on 5V tolerant digital input pins can exceed VDD as indicated in the Absolute Maximum Ratings
section. 5V tolerant digital output pins can be configured with the open-drain feature which allows the
generation of outputs higher than VDD by using external pull-up resistors. The maximum open-drain voltage
allowed is the same as the maximum VIH specification defined in the Electrical Specifications.
Signal Definitions
Signal Type Definition
VDD Power Positive supply (3.3V) for peripheral logic and I/O pins. See
Powering the Sequencer below.
VSS Power Ground reference for logic and I/O pins. See Powering the
Sequencer below.
AVDD Power Positive supply (filtered VDD) for analog modules. See
Powering the Sequencer below.
AVSS Power Analog ground reference. See Powering the Sequencer
below.
VCAP/VDDCORE Power Core decoupling capacitor. See Powering the Sequencer
below.
MCLR Programming Master Clear (Reset) input. This pin is an active-low reset to
the part. In application it must be pulled up to VDD,
typically with a 10k resistor1.
PGD Programming Data I/O pin for programming communication1.
PGC Programming Clock input pin for programming communication1.
I2C Clock I2C Synchronous serial clock input/output for I2C
communication. Since this is a slave device, the master
drives the clock. Clock stretching may occur if necessary
according to the I2C specification.
1
These pins can be brought out to a programming/debugging header for the purpose of reprogramming the part using an in-circuit serial
programmer if necessary.
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TRKA-64D84BR
I2C Data I2C Synchronous serial bi-directional data line for I2C
communication.
VREF+ External Reference Analog voltage reference (high) input.
VREF- External Reference Analog voltage reference (low) input.
Board ID (1-6) Digital Input These six digital inputs define a board identification number
for controlling which board specific configuration data is
loaded.
Board Inserted Analog Input When asserted, this is a gating signal for allowing the board
to power up. When de-asserted, the board is sequenced
down. Applies to both zones. Although this signal is an
analog input, it behaves as a digital input. Voltages greater
than 0.8V are considered logic high while voltages less than
this are considered logic low.
Enable Zone B Digital Input When asserted, Zone B is sequenced up if the Board
Seated input is also asserted and the monitored input
voltage is valid. When de-asserted, Zone B is sequenced
down.
Manufacturing Mode Digital Input Enable signal for the hardware margin signals. When this
input is asserted and a margin high or low input is asserted,
the analog PoLs are margined to their configured high or
low margin values.
Margin High Digital Input See Manufacturing mode above.
Margin Low Digital Input See Manufacturing mode above.
Reset In Digital Input When asserted causes Reset Out to assert.
PIF Enable Zone A Digital Output Asserted during zone sequence up and de-asserted during
PIF Enable Zone B zone sequence down. If an OVP fault is detected (any
monitored output voltage is greater than the power good
upper limit), the PIF Enable is de-asserted first at power
down. If no OVP fault occurs, the PIF Enable is de-
asserted last at power down.
PoL Enables (8) Digital Output Enable signal for the PoL converters. Asserted during
sequence up and de-asserted during sequence down as
defined by the configured sequence masks.
Power Good Zone A Digital Output Asserted after the configured power good delay after all of
Power Good Zone B the outputs in the zone have been sequenced up and are
operating within their configured power good limits. De-
asserted prior to sequencing down the zone due to a power
fault within the zone or if the zone is commanded down.
Reset Out Digital Output Asserted when Reset In is asserted. De-asserted when any
outputs in the configured reset masks are outside of the
power good limits. Can also be controlled by a PMBus
command.
PoL Trim (1-8) PWM Output PWM outputs for actively trimming the PoLs to their desired
set points. See Using the PWM Trim Outputs below.
These PWMs outputs are hardware based. The PWM
output duty cycle will remain fixed even when the controller
is performing long operations (such as flash memory erases
and writes).
Vin Monitor Analog Input Input voltage monitor2.
Analog x Monitor Analog Input Analog x monitor2.
2
These inputs must be scaled using attenuating resistors if the voltage exceeds the reference voltage.
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TRKA-64D84BR
Analog y Monitor Analog Input Analog y monitor2.
Analog A Monitor Analog Input Analog A monitor2.
Analog B Monitor Analog Input Analog B monitor2.
PoL Monitors (1-8) Analog Input PoL monitors2.
External Event Digital Input Fault status input used only for reporting purposes.
Theory of Operation
This version of the Sequencer supports dual zones which allows for two sets of PoLs to be independently
enabled and monitored. The zone assignment is configurable along with the standard board specific
configurable parameters.
The two zones are sequenced up or down independent of each other (except for the Board Inserted input). A
fault on one zone does not cause the other zone to power down.
If desired, it is possible to include the Analog x input in each zones power good mask so that a power good fault
on that input causes each zone to fault off.
Zone A
The PoLs included in the Zone A sequence mask are sequenced up if Board Inserted is asserted AND the Zone
A input monitor (Analog A) is valid. They are sequenced down if Board Inserted is de-asserted OR the Zone A
input monitor (Analog A) is invalid. The Zone A PoLs are also sequenced down if any of the monitored PoLs or
Analog Input voltages in the Zone A power good mask are outside of the power good limits. This will result in a
latching fault that can be cleared by issuing PMBus commands.
Zone A power up logic:

Signal State Logic
Board Inserted Asserted AND
Zone A input monitor (Analog A3) Valid (>Vin Start)
After the enable delay, PIF Enable Zone A is asserted and ramp of the Zone A PIF output (Analog B3) is
checked. Next, the PoLs listed in the Zone A sequence masks are sequenced up in the specified order with the
specified delays. If the PoLs voltages specified in the Zone A power good mask are within the power good limits
the Power Good Zone A output is asserted after the specified delay.
Zone A power down logic:

Signal State Logic
Board Inserted De-asserted OR
Zone A input monitor (Analog A3) Invalid (< Vin Off) OR
Zone A Power Good Mask any monitored voltage outside of
power good limits
Zone B
The PoLs included in the Zone B sequence mask are sequenced up if Board Inserted is asserted AND Enable
Zone B is asserted AND Zone B input monitor (Vin) is valid. They are sequenced down if Board Inserted is de-
asserted OR Enable Zone B is de-asserted OR Zone B input monitor (Vin) is invalid. The Zone B PoLs are also
sequenced down if any of the monitored PoLs or Analog Input voltages in the Zone B power good mask are
outside of the power good limits. This will result in a latching fault that can be cleared by toggling the Enable
Zone B input or issuing PMBus commands.
3
The actual analog input used for this monitor function is configurable.
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TRKA-64D84BR
Zone B power up logic:
Signal State Logic
Board Inserted Asserted AND
Enable Zone B Asserted AND
Zone B input monitor (Vin3) Valid (>Vin Start)
After the enable delay, PIF Enable Zone B is asserted and ramp of the Zone B PIF output (Analog y3) is
checked. Next, the PoLs listed in the Zone B sequence masks are sequenced up in the specified order with the
specified delays. If the PoLs voltages specified in the Zone B power good mask are within the power good limits
the Power Good Zone B output is asserted after the specified delay.
Zone B power down logic:

Signal State Logic
Board Inserted De-asserted OR
Enable Zone B De-asserted OR
Zone B input monitor (Vin3) Invalid (< Vin Off) OR
Zone B Power Good Mask any monitored voltage outside of
power good limits
Note that a sequence up operation for a zone will complete before starting the sequence up operation of the
other zone if the enables occur simultaneously or if the enabling condition of the other zone occurs while the first
zone is still sequencing up. Zone A is sequenced up first if the enabling conditions occur simultaneously.
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TRKA-64D84BR
Powering the Sequencer
VDD Core
C8
4.7 uF
10v
X5R
Microchip P/N
D1 MCP1702T-3302I/MB
BAT54
+12Vin or Equivalent
In Out VDD
R1
20 Ohm
C1
C2
3V3 Output LDO C4 C5 C6
1206 C7
1000uF
1uF 1uF 1uF 1uF 1uF
+12Vin Return 25V GND
16v 16v 16v 16v 16v VSS
X5R R2
X5R X5R X5R X5R
4.64 Ohm
AVDD
C3
2.2 uF
10v
X5R
AVSS
R3
1 Ohm
Figure 2
VDD Interface
Figure 2 is a schematic of the typical VDD interface to the sequencer IC. A Microchip LDO, P/N MCP1702T-
3302I/MB, is used to produce the 3.3V VDD supply to the DSP. This device is in a SOT89 package and in most
applications will be sufficient in size to handle the power dissipation when powering the circuit from a 12V
source. Capacitors C4, C5, C6, and C7 are the decoupling capacitors for the DSP and they should be located
directly across each pair of VDD and VSS pins on the DSP IC. A VDD core pin is used to decouple the internally
generated core voltage and requires a decoupling capacitor (C8). This decoupling capacitor should be a low
ESR ceramic capacitor and can be as large as 10uF. Capacitor C3 is the decoupling capacitor for the analog
VDD (AVDD) and it should be located directly across the AVDD and AVSS pins on the DSP IC. Resistor R2 in
combination with C3 provides a filter for the analog VDD. Resistor R3 is intended to separate AVSS from VSS.
Capacitor C2 is the input decoupling capacitor for the LDO and it should be connected directly across the LDOs
input and ground pins. Capacitor C1 is used as a hold up capacitor. Its purpose is to hold up the supply voltage
to the LDO and maintain a stable VDD for the DSP for a short period after the +12Vin source is removed. The
Schottky diode D1 prevents C1 from being discharged after +12Vin is removed. Resistor R1 is used to protect
D1 during the inrush event associated with the application of the +12Vin. The single pulse peak current rating for
a typical BAT54 diode is approximately 600mA. If the rise time of the +12V source is slow enough to limit the
peak charging current into C1 it is possible to eliminate R1. Assuming a 40mA current draw by the DSP C1 will
provide approximately 188us of hold up time per uF of capacitance.
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TRKA-64D84BR
Using the PWM Trim Outputs
+Sense
+Vin
Ry Zf
TRIM Zi -
Rx +Vout
Rz E/A PWM
Reference
Figure 3A
+Sense
+Vin
Zf
Zi -
+Vout
E/A PWM
TRIM
Rx Ry
Reference
Figure 3B
+Sense
+Vin
Zf
Zi -
+Vout
E/A PWM
Reference
+
uController
TRIM
or Equivalent
Figure 3C
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TRKA-64D84BR
The drawings in Figure 3 show the three most common trim methods used in PoL converters. In all of these
schemes a power conversion stage contains a PWM device that receives a control voltage from an error
amplifier. The error amplifier (E/A) compares a scaled version of the output voltage to a reference. The output
voltage of the converter module is simply the reciprocal of the scaling factor multiplied by the reference value.
The output voltage can be adjusted by changing this scaling factor (Figure 3A) or by modifying the reference
(Figures 3B, C).
The most common trim method is shown in Figure 3A. The popularity of this method stems from the fact that
most highly integrated PWM control ICs have an internal reference that is not accessible and cannot be
controlled externally. In this scheme the output is scaled by adding a resistor from the trim pin to ground. This
modifies the feedback divider and moves the output voltage to a higher value. The output can also be modified
by superimposing an offset voltage on the feedback divider by connecting a voltage source to the trim pin
through a resistor. Either of these two approaches will move the output voltage to a new value. The common
characteristic of modules with this trim scheme is that a lower value trim resistor to ground will cause a higher
output voltage or a larger voltage superimposed on the trim pin will cause Vout to decrease.
Some PoL converters incorporate the trim scheme shown in Figure 3B. With this method the feedback ratio is
kept constant and the reference value is modified to move the output voltage. The common characteristic of
modules with this trim scheme is that a lower value trim resistor to ground will cause a lower output voltage and
a larger voltage superimposed on the trim pin will cause Vout to increase.
The method shown in Figure 3C is occasionally used. This is similar to the method in Figure 3B except the
modification of the reference is mapped through a device such as a microcontroller. This is the least common of
the 3 methods and requires the vendors data sheet to determine the trim characteristic because the micro
controller can map the reference in many different ways.
VTrim Ripple PoL Vout

or
VTrim Average VDD
Margin PWM PoL Trim Pin

Ca
Ra Rb
3V3
Ca
0 Margin PWM PoL Trim Pin
Ra Rb
3V3
VTrim Average
0
VTrim Ripple
Figure 4A Figure 4B
The power sequencer has the ability to do independent closed loop trim and closed loop margining of the output
voltage for each PoL controlled by the device. Each PoLs output voltage is monitored and by an analog to
digital converter (ADC) in a continuous loop. In firmware the most recent measured output voltage is compared
against the desired value and the PoLs output is adjusted by delivering a trim value to the corresponding PoLs
trim pin. This trim voltage is created from a digital PWM output and an external low pass filter. Each digital
PWM is labeled <PoL n Margin PWM> where n indicates a specific converter which corresponds to the
monitoring channel labeled with the same n value. The external low pass filter creates a DC value from the
PWM signal which is then delivered to each PoL converter through a range limiting resistor.
Figure 4 shows the typical circuits used to interface the sequencers Margin PWM signals to PoL converters. In
each of the circuits shown Ra and Ca construct a low pass filter while Rb is used to limit the trim range. The
effective trim voltage is equal to the Margin PWM duty cycle multiplied by VDD and is controllable in 1024 steps
from 0 to VDD. The effective trim resistor value is equal to Ra + Rb. Ra and Ca are chosen to reduce the trim
voltage ripple. Typical values for Ra and Ca are 1K for Ra and 0.22uF to 1uF for Ca. Rb is used to limit the
control range and should be selected based on the desired control range and the trim equation for the PoL.
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TRKA-64D84BR
This trim equation is usually available from the PoL manufactures data sheet. The sequencer learns the trim
direction by making a minor adjustment to the Margin PWM and then determining the direction that Vout moves
based on this stimulus. Once the trim direction is known it knows whether increment or decrement the TRIM
PWM value until the desired Vout is achieved. The accuracy of the active trim is a function of the ADC accuracy
which is mostly controlled by accuracy of the applied reference to the sequencers Vref pins.
Either circuit in Figure 4 will work with any of the trim methods shown in Figure 3. When interfacing to PoL
modules that use the trim method in Figure 3A the circuit in Figure 4B is the optimum interface configuration. By
connecting the filter capacitor Ca to the PoLs Vout or to a positive voltage reference the effective of filtering the
Margin PWM signal remains intact. With this method there will not be a discharged capacitor connected to
ground that could cause the PoLs output to overshoot during power up as this capacitor becomes charged. In
the case that the circuit in Figure 4A is used with the trim configuration in Figure 3B the sequencer will pre-
charge the capacitor before enabling the PoL converter and then decrement the Margin PWM to achieve the
desired Vout. This requires additional start up time during system initialization. When interfacing to PoL
converters of the type shown in Figure 3B the interface circuit in Figure 4A is optimum.
Monitoring Via ADC Channels
The imbedded ADC channels are converted as 10 or 12 bit results with full scale equal to a chosen reference.
The device is intended to be powered from a 3V3 source and can be configured to use this source as the ADC
reference or to use an externally provided reference. Closed loop margining and set point adjustments always
use the entire 10 or 12 bit result to trim the output voltages to specified values. Monitored voltages are reported
via I2C communication using PMBus data formats as defined in the separate communication manual. The
voltage range reported is determined by the entered set points. Any monitored output that is greater than the
ADC reference or that can be margined above this reference should have a voltage divider to limit the maximum
input to the corresponding ADC channel to a value equal or less than the ADC reference. Monitored voltages
below the chosen ADC reference do not require this voltage divider. A four sample moving average is used to
filter the ADC results. In most cases this will eliminate the need for external filtering.
The input voltage (Vin) monitoring channel requires a voltage divider so that Vin maximum is scaled to a value
less than the maximum value of the ADC reference.
Connecting the Control and Monitoring

The three primary control interface signals to the attached PoL converters are an enable signal, a voltage
monitoring signal, and trim control signal. The enable signals are labeled <PoL n Enable>. The Monitoring
signals are labeled <PoL Monitor n>. The trim signals are labeled <PoL n Margin PWM>. Each nth PoL
converter is required to share the corresponding enable, monitor, and trim signals. The installed firmware
assumes that the connections are made this way when controlling system.
Communicating with the Device

Serial communication is achieved via an I2C bus. The communication protocol is derived from the PMBus
command set and is defined in a separate communications manual. The communications manual (TRKA-
64D84BR Protocol) also defines the protocol for device programming via embedded boot loader software.
The parameters and voltage readings for each PoL converter or analog input can be accessed using PMBus
page mode. Figure 5 shows the page assignments.
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TRKA-64D84BR
Figure 5
I2C Communication Page Assignment
12
TRKA-64D84BR
Absolute Maximum Ratings
Ambient temperature under bias ............................................................................................................. -40C to +85C
Storage temperature .............................................................................................................................. -65C to +150C
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS ...................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V..................................................... -0.3V to +5.6V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V.......................................... -0.3V to (VDD + 0.3V)
Voltage on VDDCORE with respect to VSS ................................................................................................ 2.25V to 2.75V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ............................................................................................................................. 250 mA
Maximum output current sunk by any I/O pin ...........................................................................................................4 mA
Maximum output current sourced by any I/O pin ......................................................................................................4 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports ..................................................................................................................200 mA
Electrical Specifications
Parameter Symbol Min Typ Max Units Notes
Input Voltage Range VDD 3.0 3.30 3.6 VDC
Typical is at 3.3V, 25C, 20 MIPS.
Input Current IDD 46 55 mA
Max is at 3.3V, 85C, 20 MIPS
Logic Low Input Level VIL VSS 0.2*VDD VDC
0.7*VDD VDD Non 5V tolerant pins
Logic High Input Level VIH VDC
0.7*VDD 5.5 5V tolerant pins
Logic Low Output Level VOL 0.4 VDC VDD = 3.3V
Logic High Output Level VOH 2.4 VDC VDD = 3.3V, IOH = -3.0mA
VDD Rise Rate SVDD 0.03 V/mS 0 to 3.0V in 100mS
Capacitance I/O Pin to
CIO 50 pF
GND
I2C Bus Capacitance CB 400 pF SCL and SDA
PWM Series Resistor RPWM 1 k External Series Resistor
Margin PWM Frequency FPWM 15 kHz
Reference Input Vref AVSS + 1.7 AVDD VDC
Program Flash Memory E/W
EP 10,000
Cell Endurance cycles
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TRKA-64D84BR
Mechanical Outline
Bel 64-pin 10x10x1mm TQFP Sequencer

Figure 6A
64-Lead Plastic Thin-Quad Flatpack, 10 x 10 x 1mm Body

Units Millimeters
Dimension Units Min Nom Max
Number of Leads N 64
Lead Pitch e 0.50 BSC
Leads per side n1 16
Overall Height A - - 1.20
Molded Package Thickness A2 0.95 1.00 1.05
Standoff A1 0.05 - 0.15
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle 0 3.5 7
Overall Width E 12.00 BSC
Overall Length D 12.00 BSC
Molded Package Width E1 10.00 BSC
Molded Package Length D1 10.00 BSC
Lead Thickness c 0.09 - 0.20
Lead Width b 0.17 0.22 0.27
Mold Draft Angle Top 11 12 13
Mold Draft Angle Bottom 11 12 13
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Champers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Figure 6B
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TRKA-64D84BR
Revision History
Date Revision Changes Detail Approval
2013-11-22 A First preliminary draft. S. Moore
Renamed External Fault pin name and zone assignments.
2013-11-27 B S. Moore
Added clarification based on customer review.
2014-01-07 C Added information about 5V tolerant pins. S. Moore
2014-01-13 D Corrected page assignments. S. Moore
Errata
Refer to TRKA-64D84BR Errata document for additional information specific to each code release.
RoHS Compliance
Complies with the European Directive 2002/95/EC, calling for the elimination of lead and
other hazardous substances from electronic products.
2014 Bel Fuse Inc. Specifications subject to change without notice.
15
CORPORATE FAR EAST EUROPE
Bel Fuse Inc. Bel Fuse Ltd. Bel Fuse Europe Ltd.
206 Van Vorst Street 8F/ 8 Luk Hop Street Preston Technology Management Centre
Jersey City, NJ 07302 San Po Kong Marsh Lane, Suite G7, Preston
Tel 201-432-0463 Kowloon, Hong Kong Lancashire, PR1 8UD, U.K.
Fax 201-432-9542 Tel 852-2328-5515 Tel 44-1772-556601
www.belfuse.com Fax 852-2352-3706 Fax 44-1772-888366
www.belfuse.com www.belfuse.com

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Power System Sequencer

Power System External Reference

PoL Vout Monitors (1-8)

Main Active Trim PoL Trim PWM (1-8)

I2C PoL Converters

I/O Assignment Summary

Zone A power up logic:

Zone A power down logic:

Zone B power down logic:

VTrim Ripple PoL Vout

Margin PWM PoL Trim Pin

Monitoring Via ADC Channels

Connecting the Control and Monitoring

Communicating with the Device

Bel 64-pin 10x10x1mm TQFP Sequencer

64-Lead Plastic Thin-Quad Flatpack, 10 x 10 x 1mm Body

2014 Bel Fuse Inc. Specifications subject to change without notice.

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