ADVANCED PROCESSOR

ARCHITECTURES AND MEMORY

ORGANISATION –
Lesson-16: Processor organisation and
Performance Metrics

Chapter-2 L16: "Embedded Systems - " , Raj Kamal,

2008 1
Publs.: McGraw-Hill Education
 1. Processor Organisation

Chapter-2 L16: "Embedded Systems - " , Raj Kamal,

2008 2
Publs.: McGraw-Hill Education
 Processor, Memory and buses
RAM ROM
Address bus
Processor Data bus
Control bus

Input-Output
Devices

Chapter-2 L16: "Embedded Systems - " , Raj Kamal,

2008 3
Publs.: McGraw-Hill Education
 Processor

ALU.

Processor circuit does sequential operations
and a clock guides these.

Program counter and stack pointer, which
points to the instruction to be fetched and
top of the data pushed into the stack.

Certain processor have on-chip memory
management unit (MMU).

Chapter-2 L16: "Embedded Systems - " , Raj Kamal,

2008 4
Publs.: McGraw-Hill Education
 Registers

General-purpose registers.

Registers organize onto a common internal
bus of the processor. A register is of 32, 16
or 8 bits depending on whether the ALU
performs at an instance a 32- or 16- or 8-bit
operation

Chapter-2 L16: "Embedded Systems - " , Raj Kamal,

2008 5
Publs.: McGraw-Hill Education
 CISC

Processor may have CISC (Complex

Instruction Set Computer) or RISC
(Reduced Instruction Set Computer)
architecture may affect the system design.

CISC has ability to process complex
instructions and complex data sets with
fewer registers as it provides for a large
number of addressing modes.

Chapter-2 L16: "Embedded Systems - " , Raj Kamal,

2008 6
Publs.: McGraw-Hill Education
 RISC
• Simpler instructions and all in a single cycle
per instruction.
• New RISC processors, such as ARM 7 and
ARM9 also provide for a few most useful
CISC instructions also.
• CISC converges to a RISC implementation
because the most instructions are hardwired
and implement in single clock cycle

Chapter-2 L16: "Embedded Systems - " , Raj Kamal,

2008 7
Publs.: McGraw-Hill Education
 Interrupts

Processor provides for the inputs for

external interrupts so that the external
circuits can send the interrupt signals

May possess an internal interrupt controller
(handler) to program the service routine
priorities and to allocate vector addresses.

Chapter-2 L16: "Embedded Systems - " , Raj Kamal,

2008 8
Publs.: McGraw-Hill Education
DMA (Direct Memory Access) Controller

External Devices can directly write and

read into the blocks of RAM using the
DMA controller, when the buses are not
in use of the processor

Chapter-2 L16: "Embedded Systems - " , Raj Kamal,

2008 9
Publs.: McGraw-Hill Education
Direct memory access (DMA) Controller

Multiple DMA channels on chip.

When there are number of I/O devices and
an I/O device needs to access a multi byte
data set fast, the system memory on-chip
DMA controller help greatly

Chapter-2 L16: "Embedded Systems - " , Raj Kamal,

2008 10
Publs.: McGraw-Hill Education
2. INSTRUCTION LEVEL PARALLELISM

Chapter-2 L16: "Embedded Systems - " , Raj Kamal,

2008 11
Publs.: McGraw-Hill Education
 Instruction level parallelism (ILP)

Execute several instructions is parallel. Two

or more instructions execute in parallel as
well as in pipeline.

During the in which two parallel pipelines
in a processor and two instructions In and
In+1 executing in parallel at the separate
execution units

Chapter-2 L16: "Embedded Systems - " , Raj Kamal,

2008 12
Publs.: McGraw-Hill Education
 One
Super scaling clock
Latch
cycle
Stages Pipeline1 Pipeline 2
One
I9 I10 clock
Fetch cycle

Decode I7 I8 One
clock
cycle
Read I5 I6
Operands One
clock
Execute I3 I4 cycle

Write One
I1 I2 clock
back
cycle
Chapter-2 L16: "Embedded Systems - " , Raj Kamal,
2008 13
Publs.: McGraw-Hill Education
 3. Processor Performance Metrics

Chapter-2 L16: "Embedded Systems - " , Raj Kamal,

2008 14
Publs.: McGraw-Hill Education
 Metrics

1) MIPS – Million Instructions Per Second

2) MFLOPS – Million Floating Point
Operations Per Second
3) Dhrystone/s – Number of times a
benchmark program called Dhrystone
program can run per second.[1MIPS =
1757 Dhrystone/s]

Chapter-2 L16: "Embedded Systems - " , Raj Kamal,

2008 15
Publs.: McGraw-Hill Education
 Embedded Benchmark Consortium (EEMBC) five-
benchmark program suites

Telecommunications

Consumer Electronics

Automotive and Industrial Electronics

Consumer Electronics

Office Automation.

Chapter-2 L16: "Embedded Systems - " , Raj Kamal,

2008 16
Publs.: McGraw-Hill Education
 Summary
We learnt
• Processor, address, data and control buses
and Memory
• CISC and RISC
• Instruction Level Parallelism
• Performance Metrics

Chapter-2 L16: "Embedded Systems - " , Raj Kamal,

2008 17
Publs.: McGraw-Hill Education
 End of Lesson 16 of Chapter 2

Chapter-2 L16: "Embedded Systems - " , Raj Kamal,

2008 18
Publs.: McGraw-Hill Education