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DESIGN FLOW FOR FLIP FLOP GROUPING IN DATA DRIVEN CLOCK GATING 2014

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Clock gating is a predominant technique used for power saving. It is observed

that the commonly used synthesisbased gating still leaves a large amount of
redundantclockpulses.Datadrivengatingaimstodisablethese.Toreducethe Subject

hardware overhead involved, flipflops (FFs) are grouped so that they share a Re: Design Flow for Flip Flop Grouping in Data Driven Clock Gating 2014
commonclockenablingsignal.Thequestionofwhatisthegroupsizemaximizing
thepowersavingsisansweredinapreviouspaper.Hereweanswerthequestion Message

ofwhichFFsshouldbeplacedinagrouptomaximizethepowerreduction.We
propose a practical solution based on the toggling activity correlations of FFs and their physical position proximity constraints in the
layout. Our datadriven clock gating is integrated into an Electronic Design Automation (EDA) commercial backend design flow,
achievingtotalpowerreductionof15%20%forvarioustypesoflargescalestateoftheartindustrialandacademicdesignsin40and
65 manometer process technologies. These savings are achieved on top of the sClock gating is a predominant technique used for
power saving. It is observed that the commonly used synthesisbased gating still leaves a large amount of redundant clock pulses.
Datadrivengatingaimstodisablethese.Toreducethehardwareoverheadinvolved,flipflops(FFs)aregroupedsothattheysharea
commonclockenablingsignal.Thequestionofwhatisthegroupsizemaximizingthepowersavingsisansweredinapreviouspaper.
Here we answer the question of which FFs should be placed in a group to maximize the power reduction. We propose a practical
solutionbasedonthetogglingactivitycorrelationsofFFsandtheirphysicalpositionproximityconstraintsinthelayout.Ourdatadriven
clockgatingisintegratedintoanElectronicDesignAutomation(EDA)commercialbackenddesignflow,achievingtotalpowerreduction I'm not a robot
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of 15%20% for various types of largescale stateoftheart industrial and academic designs in 40 and 65 manometer process Privacy - Terms
technologies. These savings are achieved on top of the savings obtained by clock gating synthesis performed by commercial EDA
tools, and gating manually inserted into the register transfer level design.avings obtained by clock gating synthesis performed by SEND INQUIRY
commercialEDAtools,andgatingmanuallyinsertedintotheregistertransferleveldesign.

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