Strategic Factor-Driven Supply Chain Design for

Semiconductors
Yang Sun
California State University, Sacramento, CA

Dan L. Shunk John W. Fowler Esma S. Gel

Arizona State University, Tempe, AZ

A fundamental issue in designing a supply chain for a semiconductor product is to identify the
strategy under which it will operate. In this research, designed simulation experiments are conducted
to screen important factors that affect supply chain performance under different strategies. While the
lead time customers require and the perceived importance of on-time delivery are the primary
driving factors for choosing the strategy, simulation results indicate that demand pattern and process
variability need to be considered under some circumstances. The analysis leads to a hierarchical
decision support framework that guides the selection of make-to-stock, assemble-to-order, and
make-to-order semiconductor supply chain strategies for lower supply chain cost and better on-time
delivery service.

I. INTRODUCTION supply chain system can be considered a hybrid

This research is driven by the problem of
identifying appropriate operational strategies in
semiconductor supply chains. As supply chain
concerns are now at the top of the executives
list, such a problem has become a fundamental
issue in the $200B+ semiconductor
manufacturing industry, which provides building
blocks for todays global information economy.
Integrated supply chain strategies can
generally be categorized as make-to-stock and
make-to-order. A make-to-stock supply chain
makes production and distribution decisions
based on forecasts and a make-to-order supply
chain drives production and distribution by
customer consumption (Simchi-Levi et al.,
2003). The assemble-to-order supply chain
strategy makes the parts through some initial
stages into a strategic inventory buffer, the
inventory/order (I/O) interface (Hopp and
Spearman, 2004), and employs a make-to-order
strategy awaiting customer orders to drive the
remaining assembly stages. Ultimately, any
of make-to-stock and make-to-order; it just
depends on where the I/O interface is located. If
the interface is at the beginning of the total
process, it is a make-to-order system; if at the
end, a make-to-stock system.
In spite of the material and equipment
acquisition processes, the core production-
distribution supply chain of a typical
semiconductor manufacturer consists of three
major stages: wafer fabrication and probe,
assembly and test, and product delivery (Figure
1). In todays global manufacturing environment,
these stages (or sub-stages) are often
geographically distributed and sometimes
outsourced. The wafer fabrication and probe
stage, in which integrated-circuit dies are
produced on silicon wafers and initially tested, is
often referred to as the front-end
manufacturing. In the assembly and test stage,
the back-end, dies are sawed out of the wafers
and put into a package; packaged semiconductor
devices are fully tested. Functional devices are
then delivered to customers.

Volume 8, Number 1, pp 31-43

California Journal of Operations Management 2010 CSU-POM
 Sun, Shunk, Fowler and Gel
Strategic Factor-Driven Supply Chain Design for Semiconductors

FIGURE 1: THE MAKE-TO-STOCK, ASSEMBLE-TO-ORDER, AND MAKE-TO-

ORDER SEMICONDUCTOR SUPPLY CHAINS

Die-bank, a typical I/O interface in a
semiconductor supply chain, sits between the
front-end and the back-end to store fabricated
wafers. Under a pure make-to-stock strategy,
semiconductors are made to final products and
stored in finished goods inventory. Under a pure
make-to-order strategy, production is not started
until real demand occurs. An assemble-to-order
strategy produces wafers with generic parent dies
in the front-end and the wafers are made-to-stock
into die-bank inventory. When demand occurs,
the parent dies are taken from the die-bank and
assembled-to-order in the back-end to create
different final products.
Todays semiconductor executives have
realized the importance of putting more
intelligent control into supply chains. Some firms
are restructuring their inventory and capacity
buffers to accelerate their transition from make-
to-stock to make-to-order (Kempf, 2003).
Without a doubt, determining an appropriate
strategy under which the semiconductor supply
chain will operate is a fundamental decision to
make in order to ensure a solid first-step for
operational excellence.
The challenge is to establish a generic
framework, transferable across semiconductor
California Journal of Operations Management, Volume 8, Number 1, February 2010
businesses, for identifying the appropriate supply
chain strategy. For this purpose, it is of critical
importance to understand how the framework
works with a suitable, well-understood model
(Aitken et al., 2003). In this research, we present
a set of discrete event simulation models to
systematically capture the fundamental
operational issues in a stylized semiconductor
supply chain and to compare the three generic
supply chain strategies under different
conditions. While the lead time customers
require, as well as the perceived importance of
on-time delivery, are the primary driving factors
for choosing the strategy, simulation based
experimental results also indicate that demand
pattern and process variability need to be
considered as secondary factors under certain
circumstances. The results are summarized into a
hierarchical decision support framework, with
which we attempt to guide the thinking at the
conceptual level (rather than to provide a
definitive answer) when selecting semiconductor
supply chain strategies with the goal of achieving
lower overall supply chain cost and better on-
time delivery service.
The rest of the paper is organized as
follows. Section II locates this research with

32
 Sun, Shunk, Fowler and Gel
Strategic Factor-Driven Supply Chain Design for Semiconductors
respect to the literature. A few classical
conceptual frameworks for choosing the strategy
are discussed in a semiconductor business
context, and an overview of supply chain
initiatives in todays semiconductor
manufacturing industry is provided. In Section
III, we present models of a representative
semiconductor supply chain. Structured
simulation experiments are analyzed. In Section
IV, we introduce the conceptual decision support
framework based on the analysis in Section III.
Conclusions and future research are presented in
Section V.
II. BACKGROUND AND LITERATURE
REVIEW
The semiconductor manufacturing
industry is highly capital intensive and is
characterized by high customer expectations,
short product life cycles, proliferating product
varieties, unpredictable demands, long and
variable manufacturing cycle times, globally
distributed logistics, and considerable supply
chain complexities. However, this industry has
been driven by technological innovations rather
than supply chain efficiency since its inception,
while the dilemma executives face today is that
markets have become more competitive as the
semiconductor industry itself has become more
commoditized (Cullen, 2004).
Semiconductor firms compete on
developing cutting edge technologies. Today,
however, further advancing the technology has
become more difficult as the physical limits of
silicon transistors and circuits are being
approached. Moores Law says that the number
of transistors that can be inexpensively placed on
an integrated circuit doubles approximately every
18 months (Moore, 1965), whereas many
scientists and engineers have predicted that this
law is not going to keep being applicable for long
(Tummala, 2006). Meanwhile, having the most
advanced (e.g., fastest) chip is not the only key to
competition. In general, manufacturers must also
compete on cost, quality, and speed. Note that
California Journal of Operations Management, Volume 8, Number 1, February 2010
33
quality is always taken as a given in modern
supply chain thinking (Hausman, 2002). The
firms supply chain-wide performance therefore
must be managed in the following two
dimensions: improved customer service and
reduced cost. Todays semiconductor customers
are insisting on better service, especially on-time
delivery (Maltz et al., 2001). While the
specifications (function, quality, price, etc.) of
the commoditized semiconductor products are set
by the market, cost and service are the key
competitive issues. In our analysis (Section III),
cost and service are the major concerns for
determining the supply chain strategy.
Fisher (1997) provides a concise
framework for identifying the right supply chain
strategy for a given product. The nature of the
product, generally categorized as being either
primarily functional or primarily innovative,
drives the decision. Functional products are often
available in retail outlets to satisfy peoples
basic needs, while innovative products give
customers an additional reason to buy with
fashion or technology features. Traditionally,
semiconductors are examples of innovative
products with unpredictable demand and short
product life cycles. Thus, a market-responsive
supply chain, primarily a make-to-order system,
is suggested to be generally more appropriate
than a physically efficient supply chain, primarily
a make-to-stock system (Maltz et al., 2001).
However, this knowledge does not appear
to be common in the boardrooms of
semiconductor firms. The seeming protection of
large WIP has not been easily overcome in this
industry, even in firms purporting to adopt just-
in-time philosophies (Fowler et al., 2002). Most
semiconductor manufacturers adopt primarily a
make-to-stock approach in order to maximize the
utilization of their facilities that are under multi-
million-dollar weekly depreciation and to
eliminate or reduce the part of the production
cycle time seen by customers. Today, most
semiconductor devices are standard electronic
components and should be considered primarily
functional. (All high-tech products eventually
 Sun, Shunk, Fowler and Gel
Strategic Factor-Driven Supply Chain Design for Semiconductors
evolve into commodities (Greenstein, 2004).)
Thus, make-to-stock predominantly remains as
the most widely employed strategy by
semiconductor manufacturers.
Lee (2002) adds the nature of the process
to that of the product in Fishers framework.
Semiconductors are known to have not only
highly uncertain product demands but also highly
unstable production processes. Thus, Lees
framework recommends a postponement strategy
for running the complex semiconductor supply
network. Manufacturers such as Xilinx (Brown et
al., 2000) and solution providers such as i2
Technology (i2 Technology, 2002) have initiated
the transition from make-to-stock to assemble-to-
order for the next-generation production of high-
margin, high-volume products. The assemble-to-
order system that takes the advantage of both
make-to-stock and make-to-order characteristics
may outperform pure make-to-stock and pure
make-to-order systems (Spearman and Zazanis,
1992). Brown et al. (2000) provide a case study
to demonstrate that moving from a traditional
pure make-to-stock strategy to an assemble-to-
order strategy can help the firm improve financial
performance by holding less finished goods, yet
still be responsive to customers. Lee (2001)
discusses the development and implementation
issues of a die-bank-based assemble-to-order
system.
The literature lacks of studies on make-
to-stock/make-to-order supply chains in the
semiconductor industry from a strategic decision
perspective. This research analyzes
semiconductor supply chain strategies with a
comparative approach. Designed simulation
experiments are used to analyze the make-to-
stock, make-to-order and assemble-to-order
strategies with respect to the dynamics of the
semiconductor supply chain while basic demand
and supply characteristics are captured in a
structured manner. While it if often difficult to
capture the complexity and uncertainty of the
supply chain with analytical methods, simulation
modeling facilitates the description of the overall
supply chain process, captures system dynamics
California Journal of Operations Management, Volume 8, Number 1, February 2010
34
with probability distributions, and helps compare
alternatives with what-if games in a cost-
effective way (Chang and Makatsoris, 2001).
Design of Experiments methodologies, on the
other hand, provides a systematic way to play
such what-if games. A clear framework is
provided based on the analysis to help drive the
decision of choosing the appropriate supply chain
strategy in the semiconductor manufacturing
industry.
III. METHODOLOGY
In order to understand how different
supply chain strategies work under different
demand and supply situations, we consider a
simple, yet representative semiconductor supply
chain. We assume that the mix of products is
given as follows. Two types of final products
(Type A and Type B) of the same product family
are made from the same parent dies produced in
the front-end, and are packaged differently in the
back-end. For example, Type A products are put
into a cheaper package (commodity); Type B,
more expensive package (military usage). It is
common for manufacturers to assemble parent
dies in different packages to fit different
environmental requirements such as temperature,
humidity, and pressure. As a simplified
assumption, the demands of the final products are
independent, whereas the production of parent
dies can be planned in an aggregate fashion.
We build a set of discrete event
simulation models, coded in MATLAB
(Mathworks Inc., 2003), to represent such a
supply chain. The essential difference among the
make-to-stock, assemble-to-order, and make-to-
order supply chain strategies is where the
strategic inventory is held, i.e., where the I/O
interface is located (see Figure 1). In the make-
to-stock portion of the system, the simulation
model simply releases jobs to the front-end
facilities based on given forecasts. Factory output
events are generated based on stochastic delays
(manufacturing cycle times) to build inventory
(die-bank inventory under the assemble-to-order
 Sun, Shunk, Fowler and Gel
Strategic Factor-Driven Supply Chain Design for Semiconductors
strategy, or finished goods inventory under the
pure make-to-stock strategy). A nearly perfect
yield rate is assumed in this study. Thus, 95% of
the devices from a wafer are functional with a
small variance.
In the simulation models, forecasts are
based on a typical 18-month product lifecycle in
which the demand ramps up in the first 6 months,
keeps (relatively) stable in the next 6 months, and
drops down in the last 6 months. The delays, i.e.,
manufacturing cycle times, follow triangular
distributions based on the study of Duarte et al.
(2007). Such a distribution represented by the
minimum, maximum, and most-likely values can
be easily assessed from a managerial perspective.
The pure make-to-order strategy does not
have a make-to-stock portion. Inventory at the
I/O interface is checked when an order, generated
stochastically, is placed. In the simulation model,
daily demand follows a Poisson distribution
while the average demand has an 18-month
lifecycle pattern. According to different settings
of the model, the average demand may run below
the forecast, upon which the factory capacity is
reserved, in a lack-of-sales situation, or run
above the forecast (lack-of-capacity).
If inventory is available, the simulation
model will run the make-to-order processes to
fulfill the order. (For the pure make-to-stock
strategy, the make-to-order portion is the final
product delivery process.) If current inventory is
not sufficient, the order will be held in queue
awaiting available inventory. See Sun (2004) for
a more detailed description of the simulation
models as well as the MATLAB codes.
Each simulation replication runs for an
entire product lifecycle. At the end of the cycle,
the overall supply chain performance is
calculated and recorded. In our model, supply
chain performance is measured as a combination
of production costs, inventory costs, and service
related costs. The total production cost C P can
be estimated for given products (based on either
a per wafer price charged by the third party
foundry or a per wafer cost estimated for the
wafers produced in the firms own factory).
California Journal of Operations Management, Volume 8, Number 1, February 2010
35
Inventory holding costs are collected for die-
bank (assemble-to-order) or finished goods
inventory (make-to-stock). (Raw material
inventory costs are considered sunk.) The total
inventory holding cost is
C I = hI (t )dt ,
t
where I(t) is the inventory level at time t and h is
the per unit per time unit holding cost. The
overall inventory costs, which include the
obsolescence costs for unsold goods at the end of
the product lifecycle (part of C P ), are shared by
all sold products.
On-time delivery is a key service measure
in todays semiconductor supply chains. In our
model, on-time delivery performance is
expressed by a penalty cost. The total service
penalty is
C S = pqi ( Di d i ) + ,
iF
where F is the set of orders that are fulfilled in
the product life cycle; Di the delivery date for
order i; d i the required due-date of order i; p
the per unit per time unit delay penalty (in
monetary value); qi the required quantity of
order i. Thus, it incurs a positive penalty cost if
the delivery of an order is tardy and zero
otherwise. A reasonable example for this penalty
is a rebate given back to the customer when the
order is delayed (e.g., 1% of the sales price are
deducted for each day late). Moreover, customers
may have different preferences on service. If the
customers are very sensitive to on-time delivery,
a heavier p is placed; less sensitive to on-time
delivery, a lighter p . Stock-out penalties due to
unfilled orders ( i F ), if any, at the end of the
cycle are sunk costs associated with given
forecasts, which have underestimated demands,
and are therefore not included in the performance
measure.
The overall performance measure is a
cost per wafer of products sold as follows:
(C p + C I + C S )
iF
qi
 Sun, Shunk, Fowler and Gel
Strategic Factor-Driven Supply Chain Design for Semiconductors
In order to evaluate the three supply chain
strategies under different supply/demand
circumstances, the following fundamental supply
chain issues are considered.
1) Process characteristic: process variability
The semiconductor industry is very much
driven by cycle time of front-end manufacturing
(Fowler et al., 1992). In this research, we
consider the three semiconductor supply chain
stages (front-end, back-end, and delivery) as
three black-box processes. Process
characteristics of each box are represented by a
cycle time distribution (without modeling factory
details). Note that the in-house logistics spent on
transporting the goods from one facility to
another is included in the manufacturing cycle
time, while the final logistics process delivering
finished goods to customers is represented by a
final delivery cycle time. By means of a
simplified model, built with a modular approach,
the intention is to foster a basic understanding of
the behavior of manufacturing units. If the simple
modeling approach mimics the full factory
accurately, then these models can be used to
model complex supply networks. Evidences have
been put forth to prove its credibility by Duarte et
al. (2007). Simple, fast models can produce good
fidelity with an integrative approach to capturing
the inherent complexities that exist in a supply
chain.
Another important process characteristic
is capacity. Capacity is often reserved based on
forecasts. However, true capacity for a given
semiconductor product is often unstable in real
life. There are a lot of different products
competing with each other for factory resources,
while undesired events, such as reworks and
unpredictable machine breakdowns, are not rare
events in semiconductor factories. (A detailed
simulation model capturing all these possible
events will require a much longer running time
compared with the integrative model.) In fact, the
system throughput can never reach the maximum
capacity as the cycle time goes to infinity at that
point. From a systems perspective, capacity can
California Journal of Operations Management, Volume 8, Number 1, February 2010
36
be described as the throughput rate at a given
cycle time level (cycle-time-constrained
capacity). According to Duarte et al. (2007),
semiconductor manufacturing cycle time roughly
follows a Triangular distribution. For the same
level of average cycle time, the process may have
different levels (i.e., low or high) of cycle time
variability that lead to different levels of cycle-
time-constrained capacity. The variable true
capacity of the process is therefore represented
by cycle time characteristics. Performances of
different supply chain strategies need to be
evaluated under different process cycle time
variability levels.
2) Process characteristic: process cost
Wafer fabrication is very costly. The 300-
mm (12-inch) raw wafer purchasing price is
approximately $400 per wafer; this contributes
about 12% to the $3200 front-end processing cost
(Seligson, 1998). Back-end process can cost as
much as front-end. For instance, the back-end
cost for Intels Socket 487 Pentium 4
microprocessor is about $8 per chip (IC
Knowledge Inc., 2005). A 300mm wafer can
generate about 400 such chips. Thus, total back-
end cost per wafer is approximately $3200.
Shipping costs for small semiconductor devices
are neglected in our model.
These costs vary considerably for
different IC designs and process technologies.
Nevertheless, they can be estimated for a given
product (therefore are set as constants in the
simulation model). Such costs, in essence,
contribute in a major way to the inventory
holding costs (as capital opportunity costs).
3) Demand characteristic: average demand
quantity (demand versus capacity)
It is observed that the semiconductor
industry is always under stress: in either a lack
of capacity or a lack of sales situation (Shunk
et al., 2007). Meanwhile, demands of
semiconductor products are well known to be
highly uncertain. In the simulation model,
customer orders are generated stochastically,
 Sun, Shunk, Fowler and Gel
Strategic Factor-Driven Supply Chain Design for Semiconductors

while the long-term average demand either
exceeds the capacity or runs below the capacity.
It is of crucial importance to evaluate supply
chain performance under different demand
patterns.
4) Demand characteristic: the lead time
customers require
Customers may require a very short lead
time or a very long lead time. Making a
semiconductor integrated-circuit is an extremely
complex process, and typically takes six to ten
weeks. A one-week required lead time is
obviously very tight, while a two-month lead
time requirement is quite loose (since it is
possible to deliver the goods on time even if the
production is started after the order is received).
5) Demand characteristic: customers perceived
importance on service
On-time delivery has become the most
important service issue in the semiconductor
industry (Maltz et al., 2001). Customers of
different products often have different
sensitivities to on-time delivery. Since on-time
delivery is modeled as a penalty cost in this
research, we use various levels of penalty (p) for
delayed orders to represent these differences.
We use the Design of Experiment (DOE)
method to study the impact of the above issues
(factors) on supply chain performance in a
systematic manner. DOE is a structured and
organized method for statistically analyzing the
relationships among factors affecting process
outputs. See Montgomery (2001) for details on
the DOE methodology. Table I summarizes the
factors included in the DOE analysis and their
corresponding factor levels. Note that the
strategy (make-to-stock, assemble-to-order, or
make-to-order) itself is set as a DOE factor (with
three levels) so that the relationship between the
strategy and other factors can be analyzed. All
other factor levels are set representatively. See
Sun (2004) for details on these parameter
settings.
Following such a design of experiments,
simulation is run under different settings, i.e.,
different combinations of factor levels, and the
overall cost performance is collected. Following
a standard statistical screening procedure, built
upon the foundation of the analysis of variance

TABLE 1: THE DOE FACTORS

Factors Level 1 Level 2 Level 3
Strategy Make-to-order Assemble-to-order Make-to-stock
Quoted Lead Time Short -- 5 days Medium 30 days Long-- 55 days
Penalty Weight Light (See Table III) Heavy (See Table III)
Demand of Product A Low (Demand<Capacity) High (Demand>Capacity)
Demand of Product B Low (Demand<Capacity) High (Demand>Capacity)
Front-end Cycle Time Variability Zero Variability (45 days) High Variability (Table IV)
Back-end Cycle Time Variability Zero Variability (8 days) High Variability (Table IV)
Delivery Time Variability Zero Variability (4 days) High Variability (Table IV)
Front-end Mfg Cost Low -- $2400/wafer High -- $4000/wafer
Back-end Mfg Cost, Product A Low -- $2400/wafer High -- $4000/wafer
Back-end Mfg Cost, Product B Low -- $4800/wafer High -- $8000/wafer
Note: Product A and Product B are the two final products packaged from the same parent die.

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 Sun, Shunk, Fowler and Gel
Strategic Factor-Driven Supply Chain Design for Semiconductors

FIGURE 2: PRIMARY RESULTS FROM SIMULATION EXPERIMENTS

(ANOVA), important factors and factor
interactions are identified and are summarized as
follows. In other words, these factors/factor
interactions have significant effects that the
differences of system performance at different
factor (interaction) levels are of statistical
evidence:
Primary factors:
o The interactions of (1) strategy, (2)
penalty weight on delayed delivery
(perceived importance of on-time
delivery), and (3) customers required
lead time have significant effects on
supply chain performance.
Secondary factors:
o Fixing penalty weight at light and
quoted lead time at Level 2, or fixing
penalty weight at heavy and quoted
lead time at Level 3, the following factors
have significant effects:
Demand pattern of both final products
(Type A and Type B).
Cycle time variability of front-end
and back-end processes.
(Final product delivery process has no
significant effect on the overall supply
chain performance.)
A two-step analysis, instead of a single
step global analysis, is used to screen the factors
since a single-step analysis does not provide a
clear view on all the factors that have

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 Sun, Shunk, Fowler and Gel
Strategic Factor-Driven Supply Chain Design for Semiconductors

FIGURE 3: SECONDARY RESULTS FROM SIMULATION EXPERIMENT

Under Medium Quoted Lead time and Heavy Service Penalty

significant effects in our experiments (In
simulation experiments, most likely most factors
will have some effects on the response variable
(Wan et al., 2003).) A sequential bifurcation
procedure is implemented to group the factors
(and factor interactions) as primarily important
factors and primarily unimportant ones. (See
Wan et al. (2003) for details on the sequential
bifurcation procedure for factor screening in
designed simulation experiments.) Further
analysis focusing on the unimportant group,
resulting from the primary analysis, is conducted
by fixing some of the primary factors. This leads
to a clearer view of the secondary factors. From
our analysis, primary results are shown in Figure
2; secondary results, Figure 3. See Sun (2004) for
detailed statistical analysis. Conclusions drawn
from this analysis are summarized as a
hierarchical decision support framework in
Section IV.

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 Sun, Shunk, Fowler and Gel
Strategic Factor-Driven Supply Chain Design for Semiconductors

IV. A CONCEPTUAL DECISION
FRAMEWORK
The analysis of designed simulation
experiments for a stylized semiconductor supply
chain in the last section has clearly shown that
with enough understanding of the nature of the
demand (average quantity, customers required
lead time, and customers perceived importance
on delivery service), as well as the stochastic
characteristics of the manufacturing/supply
processes, an appropriate supply chain strategy
can be identified. The same strategy can be
applied to both final products (from the same
product family) as their demands can be
considered in an aggregate fashion.
In this section, we present a hierarchical decision
support framework as a summary of the analysis
above to guide the thinking when selecting from
make-to-stock, assemble-to-order, and make-to-
order strategies for designing a semiconductor
supply chain with the goal of reducing supply
chain cost and improving on-time delivery
service. Figure 4 shows the primary level of this
decision framework. The lead time customers
require and the perceived importance of on-time
delivery service are the primary driving factors.
Further considerations on supply and demand
are desired under certain situations, namely,
when customers require medium lead times and
on-time delivery service is less important, or
when required lead times are long but on-time
delivery is highly important. Table 2 shows the
secondary level of the decision framework.

FIGURE 4: THE PRIMARY LEVEL OF THE DECISION SUPPORT FRAMEWORK

TABLE 2: THE SECONDARY LEVEL OF THE DECISION SUPPORT FRAMEWORK

Low Demand** High Demand**
Secondary Level Medium Demand**
(Lack-of-demand) (Lack-of-capacity)
Low Mfg*
Make-to-order Make-to-stock Make-to-stock
Variability
High Mfg*
Assemble-to-order Assemble-to-order Make-to-stock
Variability
* Manufacturing variability combines the front-end and back-end variability
** Aggregate demand of the two final products (Type A and Type B from the same family)

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 Sun, Shunk, Fowler and Gel
Strategic Factor-Driven Supply Chain Design for Semiconductors
The framework matches with the fact that
make-to-stock is, to some extent, the de facto
standard in the semiconductor industry since
todays customers tend to require shorter lead
times and have greater concern about on-time
delivery in a competitive, commoditized
marketplace. Intuitively, assemble-to-order
should work better at the secondary level of the
framework. However, make-to-stock remains as
the better choice at this level under some
circumstances, particularly when average
demand exceeds reserved capacity, whereas
make-to-order works better when demand is low
and manufacturing variability is low. The benefit
of adopting an assemble-to-order strategy
appears when the high variability in front-end
manufacturing is smoothed out by holding die-
bank inventory. Brown et al. (2000) illustrated a
dramatic saving in inventory cost by
implementing a die-bank assemble-to-order
strategy under such conditions in a real-world
case study.
V. CONCLUSIONS AND FUTURE
RESEARCH
In this research, a stylized semiconductor
supply chain is represented by a set of simulation
models, while a DOE method is used to conduct
and analyze simulation experiments in order to
identify important factors. The analytical results
lead to a hierarchical decision support framework
that guides the selection from make-to-stock,
assemble-to-order, and make-to-order strategies
for designing semiconductor supply chains.
Primarily, two customer-oriented factors,
required lead time and degree of importance of
on-time delivery, drive the decision. This
emphasizes a recent empirical research result that
time and availability are the No.1 driving issues
in todays semiconductor industry (Shunk et al.,
2007). While the primary factors sound intuitive,
demand pattern and process variability are also of
great importance under certain circumstances.
The seeming trend of assemble-to-order works
well with relatively low demand and high
California Journal of Operations Management, Volume 8, Number 1, February 2010
41
manufacturing variability at the secondary level
when customers have less concern about on-time
delivery with a relatively tight due-date or more
concern about on-time delivery with a loose due-
date.
Such a decision framework is based on a
stylized supply chain model with simplified
assumptions. Data generation in the simulation is
conducted upon representative distributions.
Thus, the framework attempts to guide the
thinking conceptually at the strategic level rather
than to provide a definitive answer. Future
research is recommended to develop more
accurate models for better decision support
especially at the second level. Further, it is
necessary to implement a more sophisticated
validation procedure when pursuing real-world
applications. A tactical transition from one
strategy to another also requires more detailed
modeling to reflect real situations. Designed
simulation experiments can still be of usefulness
while more details on supply chain dynamics and
complexities such as order modifications and
cancellations, capacity changes, cost variations,
yield losses, etc. can be captured. However, how
much benefit can be gained from spending a
longer simulation time is unknown and needs
further investigation. Methodologies used in this
research can be generalized to support factor-
driven supply chain design in other industrial
environments.
The use of a die-bank has become popular
today. However, it is not the only solution for
locating the I/O interface in the semiconductor
supply chain. For example, strategic inventory
can be held before the interconnection process in
the wafer fab. Integrated-circuit dies can be
interconnected differently to produce different
products when a real order comes in to indicate
which final product is demanded. Such a choice
typically involves technical complications. In this
example, semiconductors designed for multi-
interconnection typically require a larger die-area
leading to fewer dies per wafer (higher cost per
product). A transition from one strategy to
another requires a lot of work in technology
 Sun, Shunk, Fowler and Gel
Strategic Factor-Driven Supply Chain Design for Semiconductors
alternation and business process reengineering as
well as tremendous organizational support and
cultural transformation (Kempf, 2003). While
this research is conducted primarily from an
operational perspective, future research can be
conducted to help determine optimal I/O
interface locations involving technological and
organizational issues.
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