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Wednesday,November19,2008 Followers
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PostedbyVLSI_Rulesat6:05PM4comments:
Labels:backend,chip,cmos,Companies,design,fabless,
frontend,hyderabad,india,List,logic,of,physical,
semiconductor,verilog,vhdl,vlsi,world
Monday,November17,2008
CMOSInterviewQuestions
1.Explainwhy&howaMOSFETworks
2.DrawVdsIdscurveforaMOSFET.Now,showhowthiscurve
changes(a)withincreasingVgs(b)withincreasingtransistorwidth
(c)consideringChannelLengthModulation
3.ExplainthevariousMOSFETCapacitances&theirsignificance
4.DrawaCMOSInverter.Explainitstransfercharacteristics
5.Explainsizingoftheinverter
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28/03/2017 VLSIInterviewQuestions

6.HowdoyousizeNMOSandPMOStransistorstoincreasethe
thresholdvoltage?
7.WhatisNoiseMargin?ExplaintheproceduretodetermineNoise
Margin
8.GivetheexpressionforCMOSswitchingpowerdissipation
9.WhatisBodyEffect?
10.Describethevariouseffectsofscaling
11.GivetheexpressionforcalculatingDelayinCMOScircuit
12.Whathappenstodelayifyouincreaseloadcapacitance?
13.Whathappenstodelayifweincludearesistanceattheoutputof
aCMOScircuit?
14.Whatarethelimitationsinincreasingthepowersupplytoreduce
delay?
15.HowdoesResistanceofthemetallinesvarywithincreasing
thicknessandincreasinglength?
16.Youhavethreeadjacentparallelmetallines.Twooutofphase
signalspassthroughtheoutertwometallines.Drawthewaveforms
inthecentermetallineduetointerference.Now,drawthesignalsif
thesignalsinoutermetallinesareinphasewitheachother
17.Whathappensifweincreasethenumberofcontactsorviafrom
onemetallayertothenext?
18.DrawatransistorleveltwoinputNANDgate.Explainitssizing(a)
consideringVth(b)forequalriseandfalltimes
19.LetA&BbetwoinputsoftheNANDgate.SaysignalAarrivesat
theNANDgatelaterthansignalB.Tooptimizedelay,ofthetwo
seriesNMOSinputsA&B,whichonewouldyouplacenearthe
output?
20.DrawthestickdiagramofaNORgate.Optimizeit
21.ForCMOSlogic,givethevarioustechniquesyouknowtominimize
powerconsumption
22.WhatisChargeSharing?ExplaintheChargeSharingproblem
whilesamplingdatafromaBus
23.Whydowegraduallyincreasethesizeofinvertersinbuffer
design?Whynotgivetheoutputofacircuittoonelargeinverter?
24.Inthedesignofalargeinverter,whydoweprefertoconnect
smalltransistorsinparallel(thusincreasingeffectivewidth)rather
thanlayoutonetransistorwithlargewidth?
25.Givenalayout,drawitstransistorlevelcircuit.(Iwasgivena3
inputANDgateanda2inputMultiplexer.Youcanexpectanysimple
2or3inputgates)
26.GivethelogicexpressionforanAOIgate.Drawitstransistor
levelequivalent.Drawitsstickdiagram
27.WhydontweusejustoneNMOSorPMOStransistorasa
transmissiongate?
28.ForaNMOStransistoractingasapasstransistor,saythegateis
connectedtoVDD,givetheoutputforasquarepulseinputgoing
from0toVDD
29.Drawa6TSRAMCellandexplaintheReadandWriteoperations
30.DrawtheDifferentialSenseAmplifierandexplainitsworking.Any
ideahowtosizethiscircuit?(ConsiderChannelLengthModulation)
31.WhathappensifweuseanInverterinsteadoftheDifferential
SenseAmplifier?
32.DrawtheSRAMWriteCircuitry
33.Approximately,whatwerethesizesofyourtransistorsinthe
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28/03/2017 VLSIInterviewQuestions

SRAMcell?Howdidyouarriveatthosesizes?
34.HowdoesthesizeofPMOSPullUptransistors(forbit&bit
lines)affectSRAMsperformance?
35.WhatsthecriticalpathinaSRAM?
36.DrawthetimingdiagramforaSRAMRead.Whathappensifwe
delaytheenablingofClocksignal?
37.GiveabigpictureoftheentireSRAMLayoutshowingyour
placementsofSRAMCells,RowDecoders,ColumnDecoders,Read
Circuit,WriteCircuitandBuffers
38.InaSRAMlayout,whichmetallayerswouldyoupreferforWord
LinesandBitLines?Why?
39.HowcanyoumodelaSRAMatRTLLevel?
40.WhatsthedifferencebetweenTesting&Verification?
41.ForanANDORimplementationofatwoinputMux,howdoyou
testforStuckAt0andStuckAt1faultsattheinternalnodes?(You
canexpectacircuitwithsomeredundantlogic)
42.WhatisLatchUp?ExplainLatchUpwithcrosssectionofaCMOS
Inverter.HowdoyouavoidLatchUp?
============================================
===================
1.GivetwowaysofconvertingatwoinputNANDgatetoaninverter
2.Givenacircuit,drawitsexacttimingresponse.(Iwasgivena
PseudoRandomSignalGeneratoryoucanexpectanysequentialckt)
3.Whataresetuptime&holdtimeconstraints?Whatdothey
signify?Whichoneiscriticalforestimatingmaximumclockfrequency
ofacircuit?
4.Giveacircuittodividefrequencyofclockcyclebytwo
5.Designadivideby3sequentialcircuitwith50%dutycircle.(Hint:
DoubletheClock)
6.Supposeyouhaveacombinationalcircuitbetweentworegisters
drivenbyaclock.Whatwillyoudoifthedelayofthecombinational
circuitisgreaterthanyourclocksignal?(Youcantresizethe
combinationalcircuittransistors)
7.Theanswertotheabovequestionisbreakingthecombinational
circuitandpipeliningit.Whatwillbeaffectedifyoudothis?
8.WhatarethedifferentAddercircuitsyoustudied?
9.GivethetruthtableforaHalfAdder.Giveagatelevel
implementationofthesame.
10.DrawaTransmissionGatebasedDLatch.
11.DesignaTransmissionGatebasedXOR.Now,howdoyou
convertittoXNOR?(Withoutinvertingtheoutput)
12.Howdoyoudetectiftwo8bitsignalsaresame?
13.Howdoyoudetectasequenceof"1101"arrivingseriallyfroma
signalline?
14.DesignanyFSMinVHDLorVerilog.
15.ExplainRCcircuitscharginganddischarging.
16.Explaintheworkingofabinarycounter.
17.Describehowyouwouldreverseasinglylinkedlist.

PostedbyVLSI_Rulesat10:43AMNocomments:
Labels:analysis,asic,backend,buffer,chip,clock,cmos,
delay,design,layout,physical,routing,sta,synthesis,timing,
vlsi
FPGAInterviewQuestions

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28/03/2017 VLSIInterviewQuestions

1)Whatisminimumandmaximumfrequencyofdcminspartan3
seriesfpga?

Spartanseriesdcmshaveaminimumfrequencyof24MHZanda
maximumof248

2)Tellmesomeofconstraintsyouusedandtheirpurposeduringyour
design?

Therearelotofconstraintsandwillvaryfortooltotool,Iamlisting
someofXilinxconstraints
a)TranslateonandTranslateoff:theVerilogcodebetween
TranslateonandTranslateoffisignoredforsynthesis.
b)CLOCK_SIGNAL:isasynthesisconstraint.Inthecasewherea
clocksignalgoesthroughcombinatoriallogicbeforebeingconnected
totheclockinputofaflipflop,XSTcannotidentifywhatinputpinor
internalnetistherealclocksignal.Thisconstraintallowsyouto
definetheclocknet.
c)XOR_COLLAPSE:issynthesisconstraint.Itcontrolswhether
cascadedXORsshouldbecollapsedintoasingleXOR.
Formoreconstraintsdetaileddescriptionrefertoconstraintguide.

3)Supposeforapieceofcodeequivalentgatecountis600andfor
anothercodeequivalentgatecountis50,000willthesizeofbitmap
change?inotherwordswillsizeofbitmapchangeitgatecount
change?

Thesizeofbitmapisirrespectiveofresourceutilization,itisalways
thesame,forSpartanxc3s5000itis1.56MBandwillneverchange.

4)WhataredifferenttypesofFPGAprogrammingmodes?whatare
youcurrentlyusing?howtochangefromonetoanother?

BeforepoweringontheFPGA,configurationdataisstoredexternally
inaPROMorsomeothernonvolatilemediumeitheronoroffthe
board.Afterapplyingpower,theconfigurationdataiswrittentothe
FPGAusinganyoffivedifferentmodes:MasterParallel,Slave
Parallel,MasterSerial,SlaveSerial,andBoundaryScan(JTAG).The
MasterandSlaveParallelmodes
Modeselectingpinscanbesettoselectthemode,referdatasheet
forfurtherdetails.

5)TellmesomeoffeaturesofFPGAyouarecurrentlyusing?

Iamtakingexampleofxc3s5000toansweringthequestion.

Verylowcost,highperformancelogicsolutionfor
highvolume,consumerorientedapplications
Densitiesashighas74,880logiccells
Upto784I/Opins
622Mb/sdatatransferrateperI/O
18singleendedsignalstandards
6differentialI/OstandardsincludingLVDS,RSDS
TerminationbyDigitallyControlledImpedance
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Signalswingrangingfrom1.14Vto3.45V
DoubleDataRate(DDR)support
Logicresources
Abundantlogiccellswithshiftregistercapability
Widemultiplexers
Fastlookaheadcarrylogic
Dedicated18x18multipliers
Upto1,872KbitsoftotalblockRAM
Upto520KbitsoftotaldistributedRAM
DigitalClockManager(uptofourDCMs)
Clockskewelimination
Eightglobalclocklinesandabundantrouting

6)Whatisgatecountofyourproject?

Wellminewas3.2million,Idontknowyours.!

7)Canyoulistoutsomeofsynthesizableandnonsynthesizable
constructs?

notsynthesizable>>>>
initial
ignoredforsynthesis.
delays
ignoredforsynthesis.
events
notsupported.
real
Realdatatypenotsupported.
time
Timedatatypenotsupported.
forceandrelease
Forceandreleaseofdatatypesnotsupported.
forkjoin
Usenonblockingassignmentstogetsameeffect.
userdefinedprimitives
Onlygatelevelprimitivesaresupported.

synthesizableconstructs>>
assign,forloop,GateLevelPrimitives,repeatwithconstantvalue...

8)Canyouexplainwhatstruckatzeromeans?

ThesestuckatproblemswillappearinASIC.Sometimes,thenodes
willpermanentlytieto1or0becauseofsomefault.Toavoidthat,
weneedtoprovidetestabilityinRTL.Ifitispermanently1itiscalled
stuckat1Ifitispermanently0itiscalledstuckat0.

9)Canyoudrawgeneralstructureoffpga?

10)DifferencebetweenFPGAandCPLD?

FPGA:
a)SRAMbasedtechnology.
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28/03/2017 VLSIInterviewQuestions

b)Segmentedconnectionbetweenelements.
c)Usuallyusedforcomplexlogiccircuits.
d)Mustbereprogrammedoncethepowerisoff.
e)Costly

CPLD:
a)FlashorEPROMbasedtechnology.
b)Continuousconnectionbetweenelements.
c)Usuallyusedforsimplerormoderatelycomplexlogiccircuits.
d)Neednotbereprogrammedoncethepowerisoff.
e)Cheaper

11)Whataredcm's?whytheyareused?

Digitalclockmanager(DCM)isafullydigitalcontrolsystemthat
usesfeedbacktomaintainclocksignalcharacteristicswitha
highdegreeofprecisiondespitenormalvariationsinoperating
temperatureandvoltage.
ThatisclockoutputofDCMisstableoverwiderangeoftemperature
andvoltage,andalsoskewassociatedwithDCMisminimalandall
phasesofinputclockcanbeobtained.TheoutputofDCMcoming
formglobalbuffercanhandlemoreload.


12)FPGAdesignflow?

13)whatisslice,clb,lut?

Iamtakingexampleofxc3s500toanswerthisquestion

TheConfigurableLogicBlocks(CLBs)constitutethemainlogic
resourceforimplementingsynchronousaswellascombinatorial
circuits.
CLBareconfigurablelogicblocksandcanbeconfiguredto
combo,ramorromdependingoncodingstyle
CLBconsistof4slicesandeachsliceconsistoftwo4inputLUT(look
uptable)FLUTandGLUT.

14)Canaclbconfiguredasram?

YES.

Thememoryassignmentisaclockedbehavioralassignment,Reads
fromthememoryareasynchronous,Andalltheaddresslinesare
sharedbythereadandwritestatements.

15)Whatispurposeofaconstraintfilewhatisitsextension?

TheUCFfileisanASCIIfilespecifyingconstraintsonthelogical
design.Youcreatethisfileandenteryourconstraintsinthefilewith
atexteditor.YoucanalsousetheXilinxConstraintsEditortocreate
constraintswithinaUCF(extention)file.Theseconstraintsaffecthow
thelogicaldesignisimplementedinthetargetdevice.Youcanuse
thefiletooverrideconstraintsspecifiedduringdesignentry.
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16)WhatisFPGAyouarecurrentlyusingandsomeofmainreasons
forchoosingit?

17)DrawaroughdiagramofhowclockisroutedthroughoutFPGA?



18)Howmanyglobalbuffersarethereinyourcurrentfpga,whatis
theirsignificance?

Thereare8oftheminxc3s5000
AnexternalclocksourceenterstheFPGAusingaGlobalClockInput
Buffer(IBUFG),whichdirectlyaccessestheglobalclocknetworkor
anInputBuffer(IBUF).ClocksignalswithintheFPGAdriveaglobal
clocknetusingaGlobalClockMultiplexerBuffer(BUFGMUX).The
globalclocknetconnectsdirectlytotheCLKINinput.

19)Whatisfrequencyofoperationandequivalentgatecountofur
project?

20)Tellmesomeoftimingconstraintsyouhaveused?

21)Whyismaptimingoptionused?

Timingdrivenpackingandplacementisrecommendedtoimprove
designperformance,timing,andpackingforhighlyutilizeddesigns.

22)Whataredifferenttypesoftimingverifications?

Dynamictiming:
a.Thedesignissimulatedinfulltimingmode.
b.Notallpossibilitiestestedasitisdependentontheinputtest
vectors.
c.Simulationsinfulltimingmodeareslowandrequirealotof
memory.
d.Bestmethodtocheckasynchronousinterfacesorinterfaces
betweendifferenttimingdomains.
Statictiming:
a.Thedelaysoverallpathsareaddedup.
b.Allpossibilities,includingfalsepaths,verifiedwithouttheneedfor
testvectors.
c.Muchfasterthansimulations,hoursasopposedtodays.
d.Notgoodwithasynchronousinterfacesorinterfacesbetween
differenttimingdomains.

23)ComparePLL&DLL?

PLL:
PLLshavedisadvantagesthatmaketheiruseinhighspeeddesigns
problematic,particularlywhenbothhighperformanceandhigh
reliabilityarerequired.
ThePLLvoltagecontrolledoscillator(VCO)isthegreatestsourceof
problems.Variationsintemperature,supplyvoltage,and
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28/03/2017 VLSIInterviewQuestions

manufacturingprocessaffectthestabilityandoperatingperformance
ofPLLs.

DLLs,however,areimmunetotheseproblems.ADLLinitssimplest
forminsertsavariabledelaylinebetweentheexternalclockandthe
internalclock.Theclocktreedistributestheclocktoallregistersand
thenbacktothefeedbackpinoftheDLL.
ThecontrolcircuitoftheDLLadjuststhedelayssothattherising
edgesofthefeedbackclockalignwiththeinputclock.Oncetheedges
oftheclocksarealigned,theDLLislocked,andboththeinputbuffer
delayandtheclockskewarereducedtozero.
Advantages:
precision
stability
powermanagement
noisesensitivity
jitterperformance.


24)GiventwoASICs.onehassetupviolationandtheotherhashold
violation.howcantheybemadetoworktogetherwithoutmodifying
thedesign?

Slowtheclockdownontheonewithsetupviolations..
Andaddredundantlogicinthepathwhereyouhaveholdviolations.

25)Suggestsomewaystoincreaseclockfrequency?

Checkcriticalpathandoptimizeit.
Addmoretimingconstraints(overconstrain).
pipelinethearchitecturetothemaxpossibleextentkeepinginmind
latencyreq's.

26)WhatisthepurposeofDRC?

DRCisusedtocheckwhethertheparticularschematicand
correspondinglayout(especiallythemasksetsinvolved)catertoa
predefinedrulesetdependingonthetechnologyusedtodesign.
Theyareparameterssetasidebytheconcernedsemiconductor
manufacturerwithrespecttohowthemasksshouldbeplaced,
connected,routedkeepinginmindthatvariationsinthefabprocess
doesnoteffectnormalfunctionality.Itusuallydenotestheminimum
allowableconfiguration.

27)WhatisLVsandwhydowedothat.Whatisthedifference
betweenLVSandDRC?

Thelayoutmustbedrawnaccordingtocertainstrictdesignrules.
DRChelpsinlayoutofthedesignsbycheckingifthelayoutisabide
bythoserules.
Afterthelayoutiscompleteweextractthenetlist.LVScomparesthe
netlistextractedfromthelayoutwiththeschematictoensurethatthe
layoutisanidenticalmatchtothecellschematic.

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28)WhatisDFT?

DFTmeansdesignfortestability.'DesignforTestorTestability'a
methodologythatensuresadesignworksproperlyafter
manufacturing,whichlaterfacilitatesthefailureanalysisandfalse
product/piecedetection
Otherthanthefunctionallogic,youneedtoaddsomeDFTlogicin
yourdesign.Thiswillhelpyouintestingthechipformanufacturing
defectsafteritcomefromfab.Scan,MBIST,LBIST,IDDQtestingetc
areallpartofthis.(thisisahotfieldandwithlotsofopportunities)

29)TherearetwomajorFPGAcompanies:XilinxandAltera.Xilinx
tendstopromoteitshardprocessorcoresandAlteratendsto
promoteitssoftprocessorcores.Whatisthedifferencebetweena
hardprocessorcoreandasoftprocessorcore?

Ahardprocessorcoreisapredesignedblockthatisembeddedonto
thedevice.IntheXilinxVirtexIIPro,someofthelogicblockshave
beenremoved,andthespacethatwasusedfortheselogicblocksis
usedtoimplementaprocessor.TheAlteraNios,ontheotherhand,
isadesignthatcanbecompiledtothenormalFPGAlogic.

30)Whatisthesignificanceofcontaminationdelayinsequential
circuittiming?


31)WhenareDFTandFormalverificationused?

DFT:
manufacturingdefectslikestuckat"0"or"1".
testforsetofrulesfollowedduringtheinitialdesignstage.

Formalverification:
Verificationoftheoperationofthedesign,i.e,toseeifthedesign
followsspec.
gatenetlist==RTL?
usingmathematicsandstatisticalanalysistocheckforequivalence.

32)WhatisSynthesis?

Synthesisisthestageinthedesignflowwhichisconcernedwith
translatingyourVerilogcodeintogatesandthat'sputtingitvery
simply!Firstofall,theVerilogmustbewritteninaparticularwayfor
thesynthesistoolthatyouareusing.Ofcourse,asynthesistool
doesn'tactuallyproducegatesitwilloutputanetlistofthedesign
thatyouhavesynthesisedthatrepresentsthechipwhichcanbe
fabricatedthroughanASICorFPGAvendor.

33)Weneedtosampleaninputoroutputsomethingatdifferent
rates,butIneedtovarytherate?What'sacleanwaytodothis?

Many,manyproblemshavethissortofvariableraterequirement,yet
weareusuallyconstrainedwithaconstantclockfrequency.Onetrick
istoimplementadigitalNCO(NumericallyControlledOscillator).An
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28/03/2017 VLSIInterviewQuestions

NCOisactuallyverysimpleand,whileitismostnaturallyunderstood
ashardware,italsocanbeconstructedinsoftware.TheNCO,quite
simply,isanaccumulatorwhereyoukeepaddingafixedvalueon
everyclock(e.g.ataconstantclockfrequency).WhentheNCO
"wraps",yousampleyourinputordoyouraction.Byadjustingthe
valueaddedtotheaccumulatoreachclock,youfinelytunethe
AVERAGEfrequencyofthatwrapevent.Nowyoumayhaverealized
thatthewrappingeventmayhavelotsofjitteronit.True,butyou
mayusethewraptoincrementyetanothercounterwhereeach
additionalDivideby2bitreducesthisjitter.TheDDSisarelated
technique.IhavetwoexamplesshowingbothanNCOsandaDDSin
myFileArchive.Thisistrickytograspatfirst,buttremendously
powerfulonceyouhaveitinyourbagoftricks.NCOsalsorelateto
digitalPLLs,TimingRecovery,TDMAandother"variablerate"
phenomena.

PostedbyVLSI_Rulesat10:42AM2comments:
Labels:asic,chip,cmos,combinational,design,digital,fifo,
flip,flop,fpga,fsm,interview,latch,questions,RTL,
sequential,synchronous,verilog,vhdl,vlsi
VHDLInterviewQuestions
Whatisthedifferencebetweenusingdirectinstntiationsand
componentonesexceptthatyouneedtodeclarethecomponent?

WhatistheuseofBLOCKS?

WhatistheuseofPROCEDURES?

Whatistheusageofusingmorethenonearchitectureinanentity?

WhatisaDlatch?WritetheVHDLCodeforit?

ImplementDflipflopwithacoupleoflatches?WriteaVHDLCode
foraDflipflop?

DifferencesbetweenSignalsandVariablesinVHDL?Ifthesame
codeiswrittenusingSignalsandVariableswhatdoesitsynthesize
to?

DifferencesbetweenfunctionsandProceduresinVHDL?

ExplaintheconceptofaClockDividerCircuit?WriteaVHDLcodefor
thesame?

WhatyouwoulduseinRTLa'boolean'typeora'std_logic'typeand
why.

Whatare/maybetheimplicationsofusingan'integer'typeinRTL.

Atimingpathfails:whatareyouroptions?

WhatareVHDLstructures,giveanexampletoexploitthem

Whatisgreycoding,anyexamplewheretheyareused

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28/03/2017 VLSIInterviewQuestions

DiscussAsyncinterfaces

Metastability

Synopsysunwantedlatch

Verilogblockingvsnonblocking

VHDLvariables:examplewhereyouhavetousethem

Whatispipeliningandhowitmayimprovetheperformance

Whataremulticyclepaths.

Whatarefalsepaths

WhatareAsynccounters,whatareadvantagesofusingtheseover
synccounters.andwhatarethedisadvantages

SensitivityList:
Howdoesitmatter.Whatwillhappen
ifyoudontincludeasignalinthesensitivitylist
anduse/readitinsidetheprocess

HowyouwillimplementaClanguagepointerinVHDL

WhatisDesignForTestandwhyitisdone.

Whatisclockgating?Howandwhyitisdone.
LowPower:discusshowitmaybedone

Discussdisadvantages/challengesofshrinkingtechnology

Whatispipelining,howmayitaffecttheperformanceofadesign
Whatisthedifferencebetweentransportdelaysandinertialdelaysin
VHDL
Whatdeterminesthemaxfrequencyadigitaldesignmayworkon
Whythold(holdtime)isnotincludedinthecalculationfortheabove.
Whatwillhappenifoutputofaninverterisshortedtoitsinput
Whatisnoisemargin.
WhyarepmoslargerthannmosinCMOSdesign.
DrawDCcurveofinverterandReDrawitifpmosandnmosare
equal.
WhatisLatchup
HowcananInverterworkasanamplifier
Designastatemachinewhichdividestheinputfrequencyofaclock
by3.

Whydoesapassgaterequirestwotransistors(1Nand1Ptype)Can
weusea
singletransistorNorPtypeinapassgate?Ifnotwhy?andifyes
theninwhatconditions?

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28/03/2017 VLSIInterviewQuestions

WhyCMOSwhynotNMOSorPMOSlogic,whenweknowthatthe
number
ofgatesrequiredinCMOSaregraterthaninnmosorpmoslogic.

HowmuchisthemaxfanoutofatypicalCMOSgate.Oralternatively,

discussthelimitingfactors.

Whataredynamiclogicgates?Whataretheiradvantagesover
conventionallogicgates

Designadigitalcircuittodelaythenegativeedgeoftheinputsignal
by2clockcycles

Whatistherelationbetweenbinaryencodingandgrey(orgray)
encoding.

Writeavhdlfunctiontoimplementalengthindependentgreycode
counter.
alternatively,discussthelogictodothat.

Howyouwillconstraintacombinationallogicpaththroughyour
design
indc_shell.

MakeaTFlipFlopusingaDFlipFlop

HowyouwillmakeaNandGatefunctionlikeaninverter.

Designastatemachinetodetecta'1101'patterninastream.
Detectboth,overlappingandnonoverlappingpatterns.

WhatareMISRs,exampleusage?

PostedbyVLSI_Rulesat10:41AMNocomments:
Labels:asic,chip,cmos,combinational,design,digital,fifo,
flip,flop,fsm,interview,latch,questions,RTL,sequential,
skew,synchronous,verilog,vhdl,vlsi
VerilogInterviewQuestions
1.WhatisthedifferencebetweenBehaviormodelingandRTL
modeling?
2.WhatisthebenefitofusingBehaviormodelingstyleoverRTL
modeling?
3.Whatisthedifferencebetweenblockingassignmentsandnon
blockingassignments?
4.HowdoyouimplementthebidirectionalportsinVerilogHDL
5.HowtomodelinertialandtransportdelayusingVerilog?
6.Howtosynchronizecontrolsignalsanddatabetweentwodifferent
clockdomains?
7.Create4bitmultiplierusingaROMandwhatwillbethesizeofthe
ROM.Howcanyourealizeitwhentheoutputsarespecified.
8.Howcanyouswap2integersaandb,withoutusinga3rdvariable
9.Whichoneispreferred?1'scomplementor2'scomplementand
why?

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28/03/2017 VLSIInterviewQuestions

10.WhichoneispreferredinFSMdesign?MealyorMoore?Why?
11.Whichoneispreferredindesignentry?RTLcodingorSchematic?
Why?
12.Designa2inputORgateusinga2:1mux.
13.Designa2inputANDgateusinga2inputXORgate.
14.Designahardwaretoimplementfollowingequationswithout
usingmultipliersordividers.
a.out=7x+8y
b.out=.78x+.17y
15.DesignGraycountertocount6.
16.DesignXORgateusingjustNANDgates.
17.Create"AND"gateusinga2:1multiplexer.(Createallother
gatestoo.)
18.Howareblockingandnonblockingstatementsexecuted?
19.Howdoyoumodelasynchronousandasynchronousresetin
Verilog?
20.Whathappensifthereisconnectingwireswidthmismatch?
21.Whataredifferentoptionsthatcanbeusedwith$display
statementinVerilog?
22.GivetheprecedenceorderoftheoperatorsinVerilog.
23.Shouldweincludealltheinputsofacombinationalcircuitinthe
sensitivitylist?Givereason.
24.Give10commonlyusedVerilogkeywords.
25.IsitpossibletooptimizeaVerilogcodesuchthatwecanachieve
lowpowerdesign?
26.Whichisupdatedfirst:signalorvariable?

PostedbyVLSI_Rulesat10:40AMNocomments:
Labels:asic,chip,cmos,combinational,design,digital,fifo,
flip,flop,fsm,interview,latch,questions,RTL,sequential,
skew,synchronous,verilog,vhdl,vlsi
BasicDigitalInterviewQuestions
WhatisthefunctionofaDflipflop,whoseinvertedoutputis
connectedtoitsinput?


Designacircuittodivideinputfrequencyby2.


Designadivideby3sequentialcircuitwith50%dutycycle.


Designadivideby5sequentialcircuitwith50%dutycycle.


Whatarethedifferenttypesofadderimplementations?


DrawaTransmissionGatebasedDLatch.


GivethetruthtableforaHalfAdder.Giveagatelevel
implementationofit.

http://vlsichip.blogspot.in/ 17/50
28/03/2017 VLSIInterviewQuestions

DesignanXORgatefrom2:1MUXandaNOTgate


WhatisthedifferencebetweenaLATCHandaFLIPFLOP?


*Latchisalevelsensitivedevicewhileflipflopisanedgesensitive
device.
*Latchissensitivetoglitchesonenablepin,whereasflipflopis
immunetoglitches.
*Latchestakelessgates(alsolesspower)toimplementthanflip
flops.
*Latchesarefasterthanflipflops.

DesignaDFlipFlopfromtwolatches.

Designa2bitcounterusingDFlipFlop.

Whatarethetwotypesofdelaysinanydigitalsystem?

DesignaTransparentLatchusinga2:1Mux.

Designa4:1Muxusing2:1Muxesandsomecombologic.

Whatismetastablestate?Howdoesitoccur?


Whatismetastability?


Designa3:8decoder


DesignaFSMtodetectsequence"101"ininputsequence.


ConvertNANDgateintoInverter,intwodifferentways.


DesignaDandTflipflopusing2:1muxuseofothercomponents
notallowed,justthemux.


DesignadividebytwocounterusingDLatch.


DesignDLatchfromSRflipflop.


DefineClockSkew,NegativeClockSkew,PositiveClockSkew.


WhatisRaceCondition?

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28/03/2017 VLSIInterviewQuestions

Designa4bitGrayCounter.


Design4bitSynchronouscounter,Asynchronouscounter.


Designa16byteAsynchronousFIFO.


WhatisthedifferencebetweenanEEPROMandaFLASH?


WhatisthedifferencebetweenaNANDbasedFlashandaNOR
basedFlash?


Youaregivena100MHzclock.Designa33.3MHzclockwithand
without50&37dutycycle.


DesignaReadonResetSystem?


Whichoneissuperior:AsynchronousResetorSynchronousReset?
Explain.


DesignaStatemachineforTrafficControlataFourpointJunction.


WhatareFIFO's?CanyoudrawtheblockdiagramofFIFO?Could
youmodifyittomakeitasynchronousFIFO?


Howcanyougeneraterandomsequencesindigitalcircuits?

PostedbyVLSI_Rulesat10:39AM1comment:
Labels:asic,chip,cmos,combinational,design,digital,fifo,
flip,flop,fsm,interview,latch,questions,RTL,sequential,
skew,synchronous,verilog,vhdl,vlsi
PhysicalDesignInterviewQuestions
CompanywiseASIC/VLSIInterviewQuestions

BelowquestionsareaskedforseniorpositioninPhysicalDesign
domain.ThequestionsarealsorelatedtoStaticTimingAnalysisand
Synthesis.Answerstosomequestionsaregivenaslink.Remaining
questionswillbeansweredincomingblogs.


Commonintroductoryquestionseveryinterviewerasksare:


*Discussabouttheprojectsworkedinthepreviouscompany.

http://vlsichip.blogspot.in/ 19/50
28/03/2017 VLSIInterviewQuestions

*Whatarephysicaldesignflows,variousactivitiesyouareinvolved?
*Designcomplexity,capacity,frequency,processtechnologies,block
sizeyouhandled.


Intel

*Whypowerstripesroutedinthetopmetallayers?

TheresistivityoftopmetallayersarelessandhencelessIRdropis
seeninpowerdistributionnetwork.Ifpowerstripesareroutedin
lowermetallayersthiswillusegoodamountoflowerrouting
resourcesandthereforeitcancreateroutingcongestion.

*WhydoyouusealternateroutingapproachHVH/VHV(Horizontal
VerticalHorizontal/VerticalHorizontalVertical)?

Answer:

Thisapproachallowsroutabilityofthedesignandbetterusageof
routingresources.


*Whatareseveralfactorstoimprovepropagationdelayofstandard
cell?

Answer:

Improvetheinputtransitiontothecellunderconsiderationbyup
sizingthedriver.
Reducetheloadseenbythecellunderconsideration,eitherby
placementrefinementorbuffering.
IfallowedincreasethedrivestrengthorreplacewithLVT(low
thresholdvoltage)cell.

*Howdoyoucomputenetdelay(interconnectdelay)/decodeRC
valuespresentintechfile?
*Whatarevariouswaysoftimingoptimizationinsynthesistools?

Answer:

Logicoptimization:buffersizing,cellsizing,leveladjustment,dummy
bufferingetc.

LessnumberoflogicsbetweenFlipFlopsspeedupthedesign.

Optimizedrivestrengthofthecell,soitiscapableofdrivingmore
loadandhencereducingthecelldelay.

Betterselectionofdesignwarecomponent(selecttimingoptimized
designwarecomponents).

UseLVT(Lowthresholdvoltage)andSVT(standardthreshold
voltage)cellsifallowed.
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28/03/2017 VLSIInterviewQuestions

*Whatwouldyoudoinordertonotusecertaincellsfromthe
library?

Answer:

Setdontuseattributeonthoselibrarycells.

*HowdelaysarecharacterizedusingWLM(WireLoadModel)?

Answer:

Foragivenwireloadmodelthedelayareestimatedbasedonthe
numberoffanoutofthecelldrivingthenet.

FanoutvsnetlengthistabulatedinWLMs.

ValuesofunitresistanceRandunitcapacitanceCaregivenin
technologyfile.

Netlengthvariesbasedonthefanoutnumber.

OncethenetlengthisknowndelaycanbecalculatedSometimesitis
againtabulated.

*Whatarevarioustechniquestoresolvecongestion/noise?

Answer:

Routingandplacementcongestionalldependupontheconnectivityin
thenetlist,abetterfloorplancanreducethecongestion.

Noisecanbereducedbyoptimizingtheoverlapofnetsinthedesign.

*Letssaythereenoughroutingresourcesavailable,timingisfine,
canyouincreaseclockbuffersinclocknetwork?Ifsowilltherebe
anyimpactonotherparameters?

Answer:

No.Youshouldnotincreaseclockbuffersintheclocknetwork.
Increaseinclockbufferscausemorearea,morepower.When
everythingisfinewhyyouwanttotouchclocktree??

*Howdoyouoptimizeskew/insertiondelaysinCTS(ClockTree
Synthesis)?

Answer:

Betterskewtargetsandinsertiondelayvaluesprovidedwhilebuilding
theclocks.

Chooseappropriatetreestructureeitherbasedonclockbuffersor
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28/03/2017 VLSIInterviewQuestions

clockinvertersormixofclockbuffersorclockinverters.

Formulticlockdomain,grouptheclockswhilebuildingtheclocktree
sothatskewisbalancedacrosstheclocks.(Interclockskew
analysis).

*Whatarepros/consoflatch/FF(FlipFlop)?


*Howyougoaboutfixingtimingviolationsforlatchlatchpaths?
*Asanengineer,letssayyourmanagercomestoyouandasksfor
nextprojectdiesizeestimation/projection,givingdataonRTLsize,
performancerequirements.Howdoyougoaboutthefiguringoutand
comeupwithdiesizeconsideringphysicalaspects?
*Howwillyoudesigninsertingvoltageislandschemebetween
macropinscrossingcoreandareatdifferentpowerwells?Whatis
theoptimalresourcesolution?
*Whatarevariousformalverificationissuesyoufacedandhowdid
youresolve?
*Howdoyoucalculatemaximumfrequencygivensetup,hold,clock
andclockskew?
*Whatareeffectsofmetastability?


*Consideratimingpathcrossingfromfastclockdomaintoslow
clockdomain.Howdoyoudesignsynchronizercircuitwithout
knowingthesourceclockfrequency?
*Howtosolvecrossclocktimingpath?
*HowtodeterminethedepthofFIFO/sizeoftheFIFO?



STmicroelectronics

*Whatarethechallengesyoufacedinplaceandroute,FV(Formal
Verification),ECO(EngineeringChangeOrder)areas?
*Howlongthedesigncycleforyourdesigns?
*Whatpartareyourareasofinterestinphysicaldesign?
*ExplainECO(EngineeringChangeOrder)methodology.
*ExplainCTS(ClockTreeSynthesis)flow.


*Whatkindofroutingissuesyoufaced?
*HowdoesSTA(StaticTimingAnalysis)inOCV(OnChipVariation)
conditionsdone?HowdoyousetOCV(OnChipVariation)inIC
compiler?Howistimingcorrelationdonebeforeandafterplaceand
route?


*Iftherearetoomanypinsofthelogiccellsinoneplacewithin
core,whatkindofissueswouldyoufaceandhowwillyouresolve?
*Definehash/@arrayinperl.
*UsingTCL(ToolCommandLanguage,Tickle)howdoyouset
variables?
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28/03/2017 VLSIInterviewQuestions

*WhatisICC(ICCompiler)commandforsettingderatefactor/
commandtoperformphysicalsynthesis?
*Whatarenanorouteoptionsforsearchandrepair?
*Whatwereyourdesignskew/insertiondelaytargets?
*HowisIRdropanalysisdone?Whatarevariousstatisticsavailable
inreports?
*Explainpindensity/celldensityissues,hotspots?
*Howwillyourelateroutinggridwithmanufacturinggridandjudge
iftheroutinggridissetcorrectly?
*Whatisthecommandforsettingmulticyclepath?
*Ifholdviolationexistsindesign,isitOKtosignoffdesign?Ifnot,
why?


TexasInstruments(TI)

*Howaretimingconstraintsdeveloped?
*Explaintimingclosureflow/methodology/issues/fixes.
*ExplainSDF(StandardDelayFormat)backannotation/SPEF
(StandardParasiticExchangeFormat)timingcorrelationflow.
*Givenatimingpathinmultimodemulticorner,howisSTA(Static
TimingAnalysis)performedinordertomeettiminginbothmodes
andcorners,howarePVT(ProcessVoltageTemperature)/derate
factorsdecidedandsetinthePrimetimeflow?
*Withrespecttoclockgate,whatarevariousissuesyoufacedat
variousstagesinthephysicaldesignflow?
*Whataresynthesisstrategiestooptimizetiming?
*ExplainECO(EngineeringChangeOrder)implementationflow.
Givenpostrouteddatabaseandfunctionalfixes,howwillyoutakeit
toimplementECO(EngineeringChangeOrder)andwhatphysicaland
functionalchecksyouneedtoperform?


Qualcomm

*Inbuildingthetimingconstraints,doyouneedtoconstrainallIO
(InputOutput)ports?
*Canasingleporthavemulticlocked?Howdoyousetdelaysfor
suchports?
*HowisscanDEF(DesignExchangeFormat)generated?
*Whatispurposeoflockuplatchinscanchain?
*Explainshortcircuitcurrent.

*Whatarepros/consofusinglowVt,highVtcells?

*Howdoyousetinterclockuncertainty?

Answer:

set_clock_uncertaintyfromclock1toclock2

*InDC(DesignCompiler),howdoyouconstrainclocks,IO(Input
Output)ports,maxcap,maxtran?
*WhataredifferencesinclockconstraintsfrompreCTS(ClockTree
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28/03/2017 VLSIInterviewQuestions

Synthesis)topostCTS(ClockTreeSynthesis)?

Answer:

DifferenceinclockuncertaintyvaluesClocksarepropagatedinpost
CTS.

InpostCTSclocklatencyconstraintismodifiedtomodelclockjitter.

*Howisclockgatingdone?

*WhatconstraintsyouaddinCTS(ClockTreeSynthesis)forclock
gates?

Answer:

Maketheclockgatingcellsasthroughpins.

*Whatistradeoffbetweendynamicpower(current)andleakage
power(current)?

Answer:

*Howdoyoureducestandby(leakage)power?

*Explaintoplevelpinplacementflow?Whatareparametersto
decide?
*Givenblocklevelnetlists,timingconstraints,libraries,macroLEFs
(LayoutExchangeFormat/LibraryExchangeFormat),howwillyou
startfloorplanning?
*Withnetlengthof1000umhowwillyoucomputeRCvalues,using
equations/techfileinfo?
*Whatdonoisereportsrepresent?
*Whatdoesglitchreportscontain?
*WhatareCTS(ClockTreeSynthesis)stepsinICcompiler?
*Whatdoclockconstraintsfilecontain?
*Howtoanalyzeclocktreereports?
*WhatdoIRdropVoltagestormreportsrepresent?
*Where/whendoyouuseDCAP(DecouplingCapacitor)cells?
*Whatarevariouspowerreductiontechniques?


HughesNetworks

*Whatissetup/hold?Whataresetupandholdtimeimpactson
timing?Howwillyoufixsetupandholdviolations?
*ExplainfunctionofMuxedFF(MultiplexedFlipFlop)/scanFF(Scal
FlipFlop).
*WhataretestedinDFT(DesignforTestability)?
*Inequivalencechecking,howdoyouhandlescanensignal?
*IntermsofCMOS(ComplimentaryMetalOxideSemiconductor),
explainphysicalparametersthataffectthepropagationdelay?
*Whatarepowerdissipationcomponents?Howdoyoureduce
them?
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28/03/2017 VLSIInterviewQuestions

*HowdelayaffectedbyPVT(ProcessVoltageTemperature)?

*Whyispowersignalroutedintopmetallayers?


AvagoTechnologies(formerHPgroup)

*Howdoyouminimizeclockskew/balanceclocktree?
*Given11mintermsandaskedtoderivethelogicfunction.
*GivenC1=10pf,C2=1pfconnectedinserieswithaswitchin
between,att=0switchisopenandoneendhaving5vandotherend
zerovoltagecomputethevoltageacrossC2whentheswitchis
closed?
*ExplainthemodesofoperationofCMOS(ComplimentaryMetal
OxideSemiconductor)inverter?ShowIO(InputOutput)
characteristicscurve.
*Implementaringoscillator.
*Howtoslowdownringoscillator?


HynixSemiconductor

*Howdoyouoptimizepoweratvariousstagesinthephysicaldesign
flow?
*Whattimingoptimizationstrategiesyouemployinprelayout/post
layoutstages?
*Whatareprocesstechnologychallengesinphysicaldesign?
*Designdivideby2,divideby3,anddivideby1.5counters.Draw
timingdiagrams.
*Whataremulticyclepaths,falsepaths?Howtoresolvemulticycle
andfalsepaths?
*Givenafloptofloppathwithcombodelayinbetweenandoutputof
thesecondflopfedbacktocombologic.Whichpathisfastestpathto
haveholdviolationandhowwillyouresolve?
*WhatareRTL(RegisterTransferLevel)codingstylestoadaptto
yieldoptimalbackenddesign?
*Drawtimingdiagramstorepresentthepropagationdelay,setup,
hold,recovery,removal,minimumpulsewidth.


AboutContributor

ASIC_diehardhasmorethan5yearsofexperienceinphysicaldesign,
timing,netlisttoGDSflowsofIntegratedCircuitdevelopment.
ASIC_diehard'sfieldsofinterestarebackenddesign,placeandroute,
timingclosure,processtechnologies.


Readersareencouragedtodiscussanswerstothesequestions.Just
clickonthe'postacomment'optionbelowandputyourcomments
there.Alternativelyyoucansendyouranswers/discussionstomy
mailid:shavakmm@gmail.com
PhysicalDesignObjectiveTypeofQuestionsandAnswers
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28/03/2017 VLSIInterviewQuestions

*1)Chiputilizationdependson___.

a.Onlyonstandardcells
b.Standardcellsandmacros
c.Onlyonmacros
d.StandardcellsmacrosandIOpads

*2)InSoftblockages____cellsareplaced.

a.Onlysequentialcells
b.Nocells
c.OnlyBuffersandInverters
d.Anycells

*3)Whywehavetoremovescanchainsbeforeplacement?

a.Becausescanchainsaregroupofflipflop
b.Itdoesnothavetimingcriticalpath
c.ItisseriesofflipflopconnectedinFIFO
d.None

*4)Delaybetweenshortestpathandlongestpathintheclockis
called____.

a.Usefulskew
b.Localskew
c.Globalskew
d.Slack

*5)Crosstalkcanbeavoidedby___.

a.Decreasingthespacingbetweenthemetallayers
b.Shieldingthenets
c.Usinglowermetallayers
d.Usinglongnets

*6)Preroutingmeansroutingof_____.

a.Clocknets
b.Signalnets
c.IOnets
d.PGnets

*7)WhichofthefollowingmetallayerhasMaximumresistance?

a.Metal1
b.Metal2
c.Metal3
d.Metal4

*8)WhatisthegoalofCTS?

a.MinimumIRDrop
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28/03/2017 VLSIInterviewQuestions

b.MinimumEM
c.MinimumSkew
d.MinimumSlack

*9)UsuallyHoldisfixed___.

a.BeforePlacement
b.AfterPlacement
c.BeforeCTS
d.AfterCTS

*10)Toachievebettertiming____cellsareplacedinthecritical
path.

a.HVT
b.LVT
c.RVT
d.SVT

*11)Leakagepowerisinverselyproportionalto___.

a.Frequency
b.LoadCapacitance
c.Supplyvoltage
d.ThresholdVoltage

*12)Fillercellsareadded___.

a.BeforePlacementofstdcells
b.AfterPlacementofStdCells
c.BeforeFloorplanning
d.BeforeDetailRouting

*13)SearchandRepairisusedfor___.

a.ReducingIRDrop
b.ReducingDRC
c.ReducingEMviolations
d.None

*14)Maximumcurrentdensityofametalisavailablein___.

a..lib
b..v
c..tf
d..sdc

*15)MoreIRdropisdueto___.

a.Increaseinmetalwidth
b.Increaseinmetallength
c.Decreaseinmetallength
d.Lotofmetallayers

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28/03/2017 VLSIInterviewQuestions

*16)Theminimumheightandwidthacellcanoccupyinthedesign
iscalledas___.

a.UnitTilecell
b.Multiheightencell
c.LVTcell
d.HVTcell

*17)CRPRstandsfor___.

a.CellConvergencePessimismRemoval
b.CellConvergencePresetRemoval
c.ClockConvergencePessimismRemoval
d.ClockConvergencePresetRemoval

*18)InOCVtimingcheck,forsetuptime,___.

a.MaxdelayisusedforlaunchpathandMindelayforcapturepath
b.MindelayisusedforlaunchpathandMaxdelayforcapturepath
c.BothMaxdelayisusedforlaunchandCapturepath
d.BothMindelayisusedforbothCaptureandLaunchpaths

*19)"Totalmetalareaand(or)perimeterofconductinglayer/gate
togatearea"iscalled___.

a.Utilization
b.AspectRatio
c.OCV
d.AntennaRatio

*20)TheSolutionforAntennaeffectis___.

a.Diodeinsertion
b.Shielding
c.Bufferinsertion
d.Doublespacing

*21)Toavoidcrosstalk,theshieldednetisusuallyconnectedto
___.

a.VDD
b.VSS
c.BothVDDandVSS
d.Clock

*22)IfthedataisfasterthantheclockinRegtoRegpath___
violationmaycome.

a.Setup
b.Hold
c.Both
d.None

*23)Holdviolationsarepreferredtofix___.
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28/03/2017 VLSIInterviewQuestions

a.Beforeplacement
b.Afterplacement
c.BeforeCTS
d.AfterCTS


*24)WhichofthefollowingisnotpresentinSDC___?

a.Maxtran
b.Maxcap
c.Maxfanout
d.Maxcurrentdensity

*25)Timingsanitycheckmeans(withrespecttoPD)___.

a.Checkingtimingofrouteddesignwithoutnetdelays
b.CheckingTimingofplaceddesignwithnetdelays
c.CheckingTimingofunplaceddesignwithoutnetdelays
d.CheckingTimingofrouteddesignwithnetdelays

*26)Whichofthefollowingishavinghighestpriorityatfinalstage
(postrouted)ofthedesign___?

a.Setupviolation
b.Holdviolation
c.Skew
d.None

*27)WhichofthefollowingisbestsuitedforCTS?

a.CLKBUF
b.BUF
c.INV
d.CLKINV

*28)Maxvoltagedropwillbethereat(withoutmacros)___.

a.LeftandRightsides
b.BottomandTopsides
c.Middle
d.None

*29)Whichofthefollowingispreferredwhileplacingmacros___?

a.Macrosplacedcenterofthedie
b.Macrosplacedleftandrightsideofdie
c.Macrosplacedbottomandtopsidesofdie
d.MacrosplacedbasedonconnectivityoftheI/O

*30)Routingcongestioncanbeavoidedby___.

a.placingcellscloser
b.Placingcellsatcorners
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28/03/2017 VLSIInterviewQuestions

c.Distributingcells
d.None

*31)Pitchofthewireis___.

a.Minwidth
b.Minspacing
c.Minwidthminspacing
d.Minwidth+minspacing

*32)InPhysicalDesignfollowingstepisnotthere___.

a.Floorplaning
b.Placement
c.DesignSynthesis
d.CTS

*33)Intechnologyfileif7metalsaretherethenwhichmetalsyou
willuseforpower?

a.Metal1andmetal2
b.Metal3andmetal4
c.Metal5andmetal6
d.Metal6andmetal7

*34)Ifmetal6andmetal7areusedforthepowerin7metallayer
processdesignthenwhichmetalsyouwilluseforclock?

a.Metal1andmetal2
b.Metal3andmetal4
c.Metal4andmetal5
d.Metal6andmetal7

*35)InaregtoregtimingpathTclocktoqdelayis0.5nsand
TCombodelayis5nsandTsetupis0.5nsthentheclockperiodshould
be___.

a.1ns
b.3ns
c.5ns
d.6ns

*36)DifferencebetweenClockbuff/invertersandnormal
buff/invertersis__.

a.Clockbuff/invertersarefasterthannormalbuff/inverters
b.Clockbuff/invertersareslowerthannormalbuff/inverters
c.Clockbuff/invertersarehavingequalriseandfalltimeswithhigh
drivestrengthscomparetonormalbuff/inverters
d.Normalbuff/invertersarehavingequalriseandfalltimeswithhigh
drivestrengthscomparetoClockbuff/inverters.

*37)Whichconfigurationismorepreferredduringfloorplaning?

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28/03/2017 VLSIInterviewQuestions

a.Doublebackwithflippedrows
b.Doublebackwithnonflippedrows
c.Withchannelspacingbetweenrowsandnodoubleback
d.Withchannelspacingbetweenrowsanddoubleback

*38)Whatistheeffectofhighdrivestrengthbufferwhenaddedin
longnet?

a.Delayonthenetincreases
b.Capacitanceonthenetincreases
c.Delayonthenetdecreases
d.Resistanceonthenetincreases.

*39)Delayofacelldependsonwhichfactors?

a.Outputtransitionandinputload
b.InputtransitionandOutputload
c.InputtransitionandOutputtransition
d.InputloadandOutputLoad.

*40)Afterthefinalroutingtheviolationsinthedesign___.

a.Therecanbenosetup,noholdviolations
b.Therecanbeonlysetupviolationbutnohold
c.TherecanbeonlyholdviolationnotSetupviolation
d.Therecanbebothviolations.

*41)Utilisationofthechipafterplacementoptimisationwillbe___.

a.Constant
b.Decrease
c.Increase
d.Noneoftheabove

*42)Whatisroutingcongestioninthedesign?

a.Ratioofrequiredroutingtrackstoavailableroutingtracks
b.Ratioofavailableroutingtrackstorequiredroutingtracks
c.Dependsontheroutinglayersavailable
d.Noneoftheabove

*43)Whatarepreroutesinyourdesign?

a.Powerrouting
b.Signalrouting
c.PowerandSignalrouting
d.Noneoftheabove.

*44)Clocktreedoesn'tcontainfollowingcell___.

a.Clockbuffer
b.ClockInverter
c.AOIcell
d.Noneoftheabove
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28/03/2017 VLSIInterviewQuestions

*Answers:

1)b
2)c
3)b
4)c
5)b
6)d
7)a
8)c
9)d
10)b
11)d
12)d
13)b
14)c
15)b
16)a
17)c
18)a
19)d
20)a
21)b
22)b
23)d
24)d
25)c
26)b
27)a
28)c
29)d
30)c
31)d
32)c
33)d
34)c
35)d
36)c
37)a
38)c
39)b
40)d
41)c
42)a
43)a
44)c
Backend(PhysicalDesign)InterviewQuestionsandAnswers

*Belowarethesequenceofquestionsaskedforaphysicaldesign
engineer.



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Inwhichfieldareyouinterested?

*Answertothisquestiondependsonyourinterest,expertiseandto
therequirementforwhichyouhavebeeninterviewed.

*Well..thecandidategaveanswer:Lowpowerdesign


Canyoutalkaboutlowpowertechniques?
Howlowpowerandlatest90nm/65nmtechnologiesarerelated?

Doyouknowaboutinputvectorcontrolledmethodofleakage
reduction?

*Leakagecurrentofagateisdependantonitsinputsalso.Hence
findthesetofinputswhichgivesleastleakage.Byapplyigthis
minimumleakagevectortoacircuititispossibletodecreasethe
leakagecurrentofthecircuitwhenitisinthestandbymode.This
methodisknownasinputvectorcontrolledmethodofleakage
reduction.


Howcanyoureducedynamicpower?

*ReduceswitchingactivitybydesigninggoodRTL
*Clockgating
*Architecturalimprovements
*Reducesupplyvoltage
*UsemultiplevoltagedomainsMultivdd

Whatarethevectorsofdynamicpower?

*VoltageandCurrent


Howwillyoudopowerplanning?

IfyouhavebothIRdropandcongestionhowwillyoufixit?

*Spreadmacros
*Spreadstandardcells
*Increasestrapwidth
*Increasenumberofstraps
*Useproperblockage


Isincreasingpowerlinewidthandprovidingmorenumberofstraps
aretheonlysolutiontoIRdrop?

*Spreadmacros
*Spreadstandardcells
*Useproperblockage


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Inaregtoregpathifyouhavesetupproblemwherewillyouinsert
bufferneartolaunchingfloporcaptureflop?Why?

*(buffersareinsertedforfixingfanoutvoilationsandhencethey
reducesetupvoilationotherwisewetrytofixsetupvoilationwiththe
sizingofcellsnowjustassumethatyoumustinsertbuffer!)

*Neartocapturepath.

*Becausetheremaybeotherpathspassingthroughororiginating
fromtheflopnearertolauchflop.Hencebufferinsertionmayaffect
otherpathsalso.Itmayimproveallthosepathsordegarde.Ifall
thosepathshavevoilationthenyoumayinsertbuffernearerto
launchflopprovideditimprovesslack.


Howwillyoudecidebestfloorplan?

Whatisthemostchallengingtaskyouhandled?
WhatisthemostchallengingjobinP&Rflow?

*ItmaybepowerplanningbecauseyoufoundmoreIRdrop
*Itmaybelowpowertargetbecauseyouhadmoredynamicand
leakagepower
*Itmaybemacroplacementbecauseithadmoreconnectionwith
standardcellsormacros
*ItmaybeCTSbecauseyouneededtohandlemultipleclocksand
clockdomaincrossings
*ItmaybetimingbecausesizingcellsinECOflowisnotmeeting
timing
*Itmaybelibrarypreparationbecauseyoufoundsome
inconsistancyinlibraries.
*ItmaybeDRCbecauseyoufacedthousandsofvoilations


Howwillyousynthesizeclocktree?

*Singleclocknormalsynthesisandoptimization
*MultipleclocksSynthesiseachclockseperately
*MultipleclockswithdomaincrossingSynthesiseachclock
seperatelyandbalancetheskew


Howmanyclockswerethereinthisproject?

*Itisspecifictoyourproject
*Moretheclocksmorechallenging!


Howdidyouhandleallthoseclocks?

*Multipleclocks>synthesizeseperately>balancetheskew
>optimizetheclocktree

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AretheycomefromseperateexternalresourcesorPLL?

*Ifitisfromseperateclocksources(i.e.asynchronousfrom
differentpadsorpins)thenbalancingskewbetweentheseclock
sourcesbecomeschallenging.

*IfitisfromPLL(i.e.synchronous)thenskewbalancingis
comparativelyeasy.


Whybuffersareusedinclocktree?

*Tobalanceskew(i.e.floptoflopdelay)


Whatiscrosstalk?

*Switchingofthesignalinonenetcaninterfereneigbouringnetdue
tocrosscouplingcapacitance.Thisaffectisknownascrostalk.Cross
talkmayleadsetuporholdvoilation.


Howcanyouavoidcrosstalk?

*Doublespacing=>morespacing=>lesscapacitance=>lesscross
talk
*Multiplevias=>lessresistance=>lessRCdelay
*Shielding=>constantcrosscouplingcapacitance=>knownvalue
ofcrosstalk
*Bufferinsertion=>boostthevictimstrength


Howshieldingavoidscrosstalkproblem?Whatexactlyhappensthere?

*Highfrequencynoise(orglitch)iscoupledtoVSS(orVDD)since
shildedlayersareconnectedtoeitherVDDorVSS.

*CouplingcapacitanceremainsconstantwithVDDorVSS.


Howspacinghelpsinreducingcrosstalknoise?

*widthismore=>morespacingbetweentwoconductors=>cross
couplingcapacitanceisless=>lesscrosstalk


Whydoublespacingandmultipleviasareusedrelatedtoclock?

*Whyclock?becauseitistheonesignalwhichchagesitstate
regularlyandmorecomparedtoanyothersignal.Ifanyothersignal
switchesfastthenalsowecanusedoublespace.

*Doublespacing=>widthismore=>capacitanceisless=>lesscross
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talk

*Multiplevias=>resistanceinparellel=>lessresistance=>lessRC
delay



Howbuffercanbeusedinvictimtoavoidcrosstalk?

*Bufferincreasevictimssignalstrengthbuffersbreakthenet
length=>victimsaremoretoleranttocoupledsignalfromaggressor.

PhysicalDesignQuestionsandAnswers

*Iamgettingseveralemailsrequestinganswerstothequestions
postedinthisblog.Butitisverydifficulttoprovidedetailedanswerto
allquestionsinmyavailablesparetime.Henceidecidedtogive
"shortandsweet"onelineanswerstothequestionssothatreaders
canimmediatelybenefited.Detailedanswerswillbepostedinlater
stage.Ihavegivenanswerstosomeofthephysicaldesignquestions
here.Enjoy!



Whatparameters(oraspects)differentiateChipDesignandBlock
leveldesign?

*ChipdesignhasI/Opadsblockdesignhaspins.

*Chipdesignusesallmetallayesavailableblockdesignmaynotuse
allmetallayers.

*Chipisgenerallyrectangularinshapeblockscanberectangular,
rectilinear.

*Chipdesignrequiresseveralpackagingblockdesignendsina
macro.


Howdoyouplacemacrosinafullchipdesign?

*Firstcheckflylinesi.e.checknetconnectionsfrommacrotomacro
andmacrotostandardcells.

*Ifthereismoreconnectionfrommacrotomacroplacethose
macrosnearertoeachotherpreferablynearertocoreboundaries.

*Ifinputpinisconnectedtomacrobettertoplacenearertothatpin
orpad.

*Ifmacrohasmoreconnectiontostandardcellsspreadthemacros
insidecore.

*Avoidcriscrossplacementofmacros.
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*Usesoftorhardblockagestoguideplacementengine.


DifferentiatebetweenaHierarchicalDesignandflatdesign?

*Hierarchialdesignhasblocks,subblocksinanhierarchyFlattened
designhasnosubblocksandithasonlyleafcells.

*HierarchicaldesigntakesmoreruntimeFlatteneddesigntakes
lessruntime.


Whichismorecomplicatedwhenuhavea48MHzand500MHzclock
design?

*500MHzbecauseitismoreconstrained(i.e.lesserclockperiod)
than48MHzdesign.


Namefewtoolswhichyouusedforphysicalverification?

*HerculisfromSynopsys,CaliberfromMentorGraphics.


Whataretheinputfileswillyougiveforprimetimecorrelation?

*Netlist,Technologylibrary,Constraints,SPEForSDFfile.



Iftheroutingcongestionexistsbetweentwomacros,thenwhatwill
youdo?

*Providesoftorhardblockage


Howwillyoudecidethediesize?

*Bycheckingthetotalareaofthedesignyoucandecidediesize.


Iflengthymetallayerisconnectedtodiffusionandpoly,thenwhich
onewillaffectbyantennaproblem?

*Poly


Ifthefullchipdesignisroutedby7layermetal,whymacrosare
designedusing5LMinsteadofusing7LM?

*Becausetoptwometallayersarerequiredforglobalroutinginchip
design.Iftopmetallayersarealsousedinblocklevelitwillcreate
routingblockage.
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Inyourprojectwhatisdiesize,numberofmetallayers,technology,
foundry,numberofclocks?

*Diesize:tellinmmeg.1mmx1mmremeber1mm=1000micron
whichisabigsize!!

*Metallayers:Seeyourtechfile.generallyfor90nmitis7to9.

*Technology:Againlookintotechfiles.

*Foundry:Againlookintotechfileseg.TSMC,IBM,ARTISANetc

*Clocks:LookintoyourdesignandSDCfile!


Howmanymacrosinyourdesign?

*Youknowitwellasyouhavedesignedit!ASoC(SystemOnChip)
designmayhave100macrosalso!!!!


Whatiseachmacrosizeandnumberofstandardcellcount?

*Dependsonyourdesign.


Whataretheinputneedsforyourdesign?

*Forsynthesis:RTL,Technologylibrary,Standardcelllibrary,
Constraints

*ForPhysicaldesign:Netlist,Technologylibrary,Constraints,
Standardcelllibrary


WhatisSDCconstraintfilecontains?

*Clockdefinitions

*Timingexceptionmulticyclepath,falsepath

*InputandOutputdelays


Howdidyoudopowerplanning?Howtocalculatecoreringwidth,
macroringwidthandstraportrunkwidth?Howtofindnumberof
powerpadandIOpowerpads?Howthewidthofmetalandnumber
ofstrapscalculatedforpowerandground?

*Getthetotalcorepowerconsumptiongetthemetallayercurrent
densityvaluefromthetechfileDividetotalpowerbynumbersides
ofthechipDividetheobtainedvaluefromthecurrentdensitytoget
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corepowerringwidth.Thencalculatenumberofstrapsusingsome
moreequations.Willbeexplainedindetaillater.

Howtofindtotalchippower?

*Totalchippower=standardcellpowerconsumption,Macropower
consumptionpadpowerconsumption.


Whataretheproblemsfacedrelatedtotiming?

*Prelayout:Setup,Maxtransition,maxcapacitance

*Postlayout:Hold


Howdidyouresolvethesetupandholdproblem?

*Setup:upsizethecells

*Hold:insertbuffers


Inwhichlayerdoyoupreferforclockroutingandwhy?

*Nextlowerlayertothetoptwometallayers(globalroutinglayers).
BecauseithaslessresistancehencelessRCdelay.


Ifinyourdesignhasresetpin,thenitllaffectinputpinoroutputpin
orboth?

*Outputpin.


Duringpoweranalysis,ifyouarefacingIRdropproblem,thenhow
didyouavoid?

*Increasepowermetallayerwidth.

*Goforhighermetallayer.

*Spreadmacrosorstandardcells.

*Providemorestraps.


Defineantennaproblemandhowdidyouresolvetheseproblem?

*Increasednetlengthcanaccumulatemorechargeswhile
manufacturingofthedeviceduetoionisationprocess.Ifthisnetis
connectedtogateoftheMOSFETitcandamagedielectricpropertyof
thegateandgatemayconductcausingdamagetotheMOSFET.This
isantennaproblem.
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*Decreasethelengthofthenetbyprovidingmoreviasandlayer
jumping.

*Insertantennadiode.


HowdelaysvarywithdifferentPVTconditions?Showthegraph.

*Pincrease>dealyincrease

*Pdecrease>delaydecrease


*Vincrease>delaydecrease

*Vdecrease>delayincrease


*Tincrease>delayincrease

*Tdecrease>delaydecrease


Explaintheflowofphysicaldesignandinputsandoutputsforeach
stepinflow.

Whatiscelldelayandnetdelay?

*Gatedelay

*Transistorswithinagatetakeafinitetimetoswitch.Thismeans
thatachangeontheinputofagatetakesafinitetimetocausea
changeontheoutput.[Magma]


*Gatedelay=functionof(i/ptransitiontime,Cnet+Cpin).


*CelldelayisalsosameasGatedelay.


*Celldelay


*Foranygateitismeasuredbetween50%ofinputtransitiontothe
corresponding50%ofoutputtransition.


*Intrinsicdelay


*Intrinsicdelayisthedelayinternaltothegate.Inputpinofthecell
tooutputpinofthecell.
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*Itisdefinedasthedelaybetweenaninputandoutputpairofacell,
whenanearzeroslewisappliedtotheinputpinandtheoutputdoes
notseeanyloadcondition.Itispredominantlycausedbytheinternal
capacitanceassociatedwithitstransistor.


*Thisdelayislargelyindependentofthesizeofthetransistors
formingthegatebecauseincreasingsizeoftransistorsincrease
internalcapacitors.


*NetDelay(orwiredelay)


*Thedifferencebetweenthetimeasignalisfirstappliedtothenet
andthetimeitreachesotherdevicesconnectedtothatnet.


*Itisduetothefiniteresistanceandcapacitanceofthenet.Itisalso
knownaswiredelay.


*Wiredelay=fn(Rnet,Cnet+Cpin)


Whataredelaymodelsandwhatisthedifferencebetweenthem?

*LinearDelayModel(LDM)

*NonLinearDelayModel(NLDM)


Whatiswireloadmodel?

*WireloadmodelisNLDMwhichhasestimatedRandCofthenet.


WhyhighermetallayersarepreferredforVddandVss?

*BecauseithaslessresistanceandhenceleadstolessIRdrop.


Whatislogicoptimizationandgivesomemethodsoflogic
optimization.

*Upsizing

*Downsizing

*Bufferinsertion

*Bufferrelocation
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*Dummybufferplacement


Whatisthesignificanceofnegativeslack?

*negativeslack==>thereissetupvoilation==>deisgncanfail


Whatissignalintegrity?HowitaffectsTiming?

*IRdrop,ElectroMigration(EM),Crosstalk,Groundbounceare
signalintegrityissues.

*IfIdropismore==>delayincreases.

*crosstalk==>therecanbesetupaswellasholdvoilation.


WhatisIRdrop?Howtoavoid?Howitaffectstiming?

*Thereisaresistanceassociatedwitheachmetallayer.This
resistanceconsumespowercausingvoltagedropi.e.IRdrop.

*IfIRdropismore==>delayincreases.


WhatisEManditeffects?

*Duetohighcurrentflowinthemetalatomsofthemetalcan
displacedfromitsorigialplace.Whenithappensinlargeramountthe
metalcanopenorbulgingofmetallayercanhappen.Thiseffectis
knownasElectroMigration.


*Affects:Eithershortoropenofthesignallineorpowerline.


Whataretypesofrouting?

*GlobalRouting

*TrackAssignment

*DetailRouting


Whatislatency?Givethetypes?

*SourceLatency

*Itisknownassourcelatencyalso.Itisdefinedas"thedelayfrom
theclockoriginpointtotheclockdefinitionpointinthedesign".

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28/03/2017 VLSIInterviewQuestions

*Delayfromclocksourcetobeginningofclocktree(i.e.clock
definitionpoint).


*Thetimeaclocksignaltakestopropagatefromitsidealwaveform
originpointtotheclockdefinitionpointinthedesign.


*Networklatency


*ItisalsoknownasInsertiondelayorNetworklatency.Itisdefined
as"thedelayfromtheclockdefinitionpointtotheclockpinofthe
register".


*Thetimeclocksignal(riseorfall)takestopropagatefromtheclock
definitionpointtoaregisterclockpin.


Whatistrackassignment?

*Secondstageoftheroutingwhereinparticularmetaltracks(or
layers)areassignedtothesignalnets.


Whatiscongestion?

*Ifthenumberofroutingtracksavailableforroutingislessthanthe
requiredtracksthenitisknownascongestion.


Whethercongestionisrelatedtoplacementorrouting?

*Routing


Whatareclocktrees?

*Distributionofclockfromtheclocksourcetothesyncpinofthe
registers.


Whatareclocktreetypes?

*Htree,Balancedtree,Xtree,Clusteringtree,Fishbone


Whatiscloningandbuffering?

*Cloningisamethodofoptimizationthatdecreasestheloadofa
heavilyloadedcellbyreplicatingthecell.

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*Bufferingisamethodofoptimizationthatisusedtoinsertbeffers
inhighfanoutnetstodecreasethedealy.

Whatisthedifferencebetweensoftmacroandhardmacro?

*Whatisthedifferencebetweenhardmacro,firmmacroandsoft
macro?


or

*WhatareIPs?



*Hardmacro,firmmacroandsoftmacroareallknownasIP
(Intellectualproperty).Theyareoptimizedforpower,areaand
performance.TheycanbepurchasedandusedinyourASICorFPGA
designimplementationflow.SoftmacroisflexibleforalltypeofASIC
implementation.HardmacrocanbeusedinpureASICdesignflow,
notinFPGAflow.BeforebyinganyIPitisveryimportanttoevaluate
itsadvantagesanddisadvantagesovereachother,hardware
compatibilitysuchasI/Ostandardswithyourdesignblocks,
reusabilityforotherdesigns.


Softmacros

*SoftmacrosareinsynthesizableRTL.

*Softmacrosaremoreflexiblethanfirmorhardmacros.

*Softmacrosarenotspecifictoanymanufacturingprocess.

*Softmacroshavethedisadvantageofbeingsomewhat
unpredictableintermsofperformance,timing,area,orpower.

*SoftmacroscarrygreaterIPprotectionrisksbecauseRTLsource
codeismoreportableandtherefore,lesseasilyprotectedthaneither
anetlistorphysicallayoutdata.

*Fromthephysicaldesignperspective,softmacroisanycellthat
hasbeenplacedandroutedinaplacementandroutingtoolsuchas
Astro.(ThisisthedefinitiongiveninAstroRailusermanual!)

*Softmacrosareeditableandcancontainstandardcells,hard
macros,orothersoftmacros.



Firmmacros

*Firmmacrosareinnetlistformat.

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*Firmmacrosareoptimizedforperformance/area/powerusinga
specificfabricationtechnology.

*Firmmacrosaremoreflexibleandportablethanhardmacros.

*Firmmacrosarepredictiveofperformanceandareathansoft
macros.



Hardmacro

*HardmacrosaregenerallyintheformofhardwareIPs(orwe
termeditashardwreIPs!).

*HardmacosaretargetedforspecificICmanufacturingtechnology.

*Hardmacrosareblockleveldesignswhicharesilicontestedand
proved.

*Hardmacroshavebeenoptimizedforpowerorareaortiming.

*Inphysicaldesignyoucanonlyaccesspinsofhardmacrosunlike
softmacroswhichallowsustomanipulateindifferentway.

*Youhavefreedomtomove,rotate,flipbutyoucan'ttouchanything
insidehardmacros.

*Verycommonexampleofhardmacroismemory.Itcanbeany
designwhichcarriesdedicatedsinglefunctionality(ingeneral)..for
exampleitcanbeaMP4decoder.

*Beawareoffeaturesandcharacteristicsofhardmacrobeforeyou
useitinyourdesign...otherthanpower,timingandareayoualso
shouldknowpinpropertieslikesyncpin,I/Ostandardsetc

*LEF,GDS2fileformatallowseasyusageofmacrosindifferent
tools.



Fromthephysicaldesign(backend)perspective:

*Hardmacroisablockthatisgeneratedinamethodologyother
thanplaceandroute(i.e.usingfullcustomdesignmethodology)and
isbroughtintothephysicaldesigndatabase(eg.Milkywayin
SynopsysVolcanoinMagma)asaGDS2file.



SynthesisandplacementofmacrosinmodernSoCdesignsare
challenging.EDAtoolsemploydifferentalgorithmsaccomplishthis
taskalongwiththetargetofpowerandarea.Thereareseveral
researchpapersavailableonthesesubjects.Someofthemcanbe
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28/03/2017 VLSIInterviewQuestions

downloadedfromthegivenlinkbelow.


Whatisdifferencebetweennormalbufferandclockbuffer?

Answer:


ClocknetisoneoftheHighFanoutNet(HFN)s.Theclockbuffersare
designedwithsomespecialpropertylikehighdrivestrengthandless
delay.Clockbuffershaveequalriseandfalltime.Thispreventsduty
cycleofclocksignalfromchangingwhenitpassesthroughachainof
clockbuffers.


NormalbuffersaredesignedwithW/Lratiosuchthatsumofrise
timeandfalltimeisminimum.Theytooaredesignedforhigherdrive
strength.
WhatisdifferencebetweenHFNsynthesisandCTS?

Answer:


HFNsaresynthesizedinfrontendalso....butatthatmomentno
placementinformationofstandardcellsareavailable...hence
backendtoolcollapsessynthesizedHFNs.ItresenthesizesHFNs
basedonplacementinformationandappropriatelyinsertsbuffer.
Targetofthissynthesisistomeetdelayrequirementsi.e.setupand
hold.


Forclocknosynthesisiscarriedoutinfrontend
(why.....????..becausenoplacementinformationofflipflops!So
synthesiswon'tmeettrueskewtargets!!)...inbackendclocktree
synthesistriestomeet"skew"targets...Itinsertsclockbuffers(which
haveequalriseandfalltime,unlikenormalbuffers!)...Thereisno
skewinformationforanyHFNs.
Isitpossibletohaveazeroskewinthedesign?

Answer:

Theoreticallyitispossible....!

Practicallyitisimpossible....!!


Practicallywecantreduceanydelaytozero....delaywillexist...
hencewetrytomakeskew"equal"(orsame)ratherthan
"zero"......nowwiththisoptimizationallflopsgettheclockedgewith
samedelayrelativetoeachother....sovirtuallywecansaytheyare
having"zeroskew"orskewis"balanced".
PhysicalDesignInterviewQuestions

BelowaretheimportantinterviewquestionsforVLSIphysicaldesign
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28/03/2017 VLSIInterviewQuestions

aspirants.Interviewstartswithflowofphysicaldesignandgoes
on.....on....on.....Iamtryingtomakeyourlifeeasy.....letme
prepareanswerstoalltheseifsoftform....assoonasithappens
thoseanswerswillbepostedincomingblogs.

*
Whatparameters(oraspects)differentiateChipDesign&Blocklevel
design??
*
Howdoyouplacemacrosinafullchipdesign?
*
DifferentiatebetweenaHierarchicalDesignandflatdesign?
*
Whichismorecomplicatedwhenuhavea48MHzand500MHzclock
design?
*
Namefewtoolswhichyouusedforphysicalverification?
*
Whataretheinputfileswillyougiveforprimetimecorrelation?
*
Whatarethealgorithmsusedwhilerouting?Willitoptimizewire
length?
*
HowwillyoudecidethePinlocationinblockleveldesign?
*
Iftheroutingcongestionexistsbetweentwomacros,thenwhatwill
youdo?
*
Howwillyouplacethemacros?
*
Howwillyoudecidethediesize?
*
Iflengthymetallayerisconnectedtodiffusionandpoly,thenwhich
onewillaffectbyantennaproblem?
*
Ifthefullchipdesignisroutedby7layermetal,whymacrosare
designedusing5LMinsteadofusing7LM?
*
Inyourprojectwhatisdiesize,numberofmetallayers,technology,
foundry,numberofclocks?
*
Howmanymacrosinyourdesign?
*
Whatiseachmacrosizeandno.ofstandardcellcount?
*
HowdiduhandletheClockinyourdesign?
*
WhataretheInputneedsforyourdesign?
*
WhatisSDCconstraintfilecontains?
*
Howdidyoudopowerplanning?
*
Howtofindtotalchippower?
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28/03/2017 VLSIInterviewQuestions

*
Howtocalculatecoreringwidth,macroringwidthandstraportrunk
width?
*
HowtofindnumberofpowerpadandIOpowerpads?
*
Whataretheproblemsfacedrelatedtotiming?
*
Howdiduresolvethesetupandholdproblem?
*
Ifinyourdesign10000andmorenumbersofproblemscome,then
whatyouwilldo?
*
Inwhichlayerdoyoupreferforclockroutingandwhy?
*
Ifinyourdesignhasresetpin,thenitllaffectinputpinoroutputpin
orboth?
*
Duringpoweranalysis,ifyouarefacingIRdropproblem,thenhow
diduavoid?
*
Defineantennaproblemandhowdiduresolvetheseproblem?
*
HowdelaysvarywithdifferentPVTconditions?Showthegraph.
*
Explaintheflowofphysicaldesignandinputsandoutputsforeach
stepinflow.
*
Whatiscelldelayandnetdelay?
*
Whataredelaymodelsandwhatisthedifferencebetweenthem?
*
Whatiswireloadmodel?
*
WhatdoesSDCconstraintshas?
*
WhyhighermetallayersarepreferredforVddandVss?
*
Whatislogicoptimizationandgivesomemethodsoflogic
optimization.
*
Whatisthesignificanceofnegativeslack?
*
Whatissignalintegrity?HowitaffectsTiming?
*
WhatisIRdrop?Howtoavoid.howitaffectstiming?
*
WhatisEManditeffects?
*
Whatisfloorplanandpowerplan?
*
Whataretypesofrouting?
*
Whatisagrid.whyweneedanddifferenttypesofgrids?
http://vlsichip.blogspot.in/ 48/50
28/03/2017 VLSIInterviewQuestions

*
Whatiscoreandhowuwilldecidew/hratioforcore?
*
Whatiseffectiveutilizationandchiputilization?
*
Whatislatency?Givethetypes?
*
Howthewidthofmetalandnumberofstrapscalculatedforpower
andground?
*
Whatisnegativeslack?Howitaffectstiming?
*
Whatistrackassignment?
*
Whatisgridedandgridlessrouting?
*
Whatisamacroandstandardcell?
*
Whatiscongestion?
*
Whethercongestionisrelatedtoplacementorrouting?
*
Whatareclocktrees?
*
Whatareclocktreetypes?
*
Whichlayerisusedforclockroutingandwhy?
*
Whatiscloningandbuffering?
*
Whatareplacementblockages?
*
Howslowandfasttransitionatinputseffecttimingforgates?
*
Whatisantennaeffect?
*
WhatareDFMissues?
*
Whatis.lib,LEF,DEF,.tf?
*
Whatisthedifferencebetweensynthesisandsimulation?
*
Whatismetaldensity,metalslottingrule?
*
WhatisOPC,PSM?
*
WhyclockisnotsynthesizedinDC?
*
WhatarehighVtandlowVtcells?
*
Whatcornercellscontains?
*
Whatisthedifferencebetweencorefillercellsandmetalfillers?
*
http://vlsichip.blogspot.in/ 49/50
28/03/2017 VLSIInterviewQuestions

Howtodecidenumberofpadsinchipleveldesign?
*
Whatistiehighandtielowcellsandwhereitisused
*
WhatisLEF?
*
WhatisDEF?
*
Whatarethestepsinvolvedindesigninganoptimalpadring?

*Whatarethestepsthatyouhavedoneinthedesignflow?
*Whataretheissuesinfloorplan?
*Howcanyouestimateareaofblock?
*Howmuchaspectratioshouldbekept(orhaveyoukept)andwhat
istheutilization?
*Howtocalculatecoreringandstripewidths?
*Whatifhotspotfoundinsomeareaofblock?Howyoutacklethis?
*Afteraddingstripesalsoifyouhavehotspotwhattodo?
*Whatisthresholdvoltage?Howitaffecttiming?
*Whatiscontentoflib,lef,sdc?
*Whatismeantmy9track,12trackstandardcells?
*Whatisscanchain?Whatifscanchainnotdetachedand
reordered?Isitcompulsory?
*Whatissetupandhold?Whythereare?Whatifsetupandhold
violates?
*Inacircuit,forregtoregpath...Tclktoqis50ps,Tcombo50ps,
Tsetup50ps,tskewis100ps.Thenwhatisthemaximumoperating
frequency?
*HowRandCvaluesareaffectingtime?
*Howohm(R),fared(C)isrelatedtosecond(T)?
*Whatistransition?Whatiftransitiontimeismore?
*Whatisdifferencebetweennormalbufferandclockbuffer?
*Whatisantennaeffect?Howitisavoided?
*WhatisESD?
*Whatiscrosstalk?Howcanyouavoid?
*Howdoublespacingwillavoidcrosstalk?
*WhatisdifferencebetweenHFNsynthesisandCTS?
*Whatisholdproblem?Howcanyouavoidit?
*Foraniterationwehave0.5nsofinsertiondelayand0.1skewand
forotheriteration0.29nsinsertiondelayand0.25skewforthesame
circuitthenwhichoneyouwillselect?Why?
*Whatispartialfloorplan?

PostedbyVLSI_Rulesat10:37AM5comments:
Labels:analysis,asic,backend,buffer,chip,clock,cmos,
delay,design,layout,optimization,physical,routing,sta,
synthesis,timing,tree,vlsi
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