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LAPORAN PRAKTIKUM

ELEKTRONIKA II
SEMESTER GENAP A.T.A 2016/2017

Nama / NPM : (Nama Kamu) / (NPM Kamu)


Kelompok : (Nomor)
Rekan Kerja : (Nama Rekan)
Hari Praktikum : (hari praktikum kamu)
Tanggal Percobaan : (tanggal melakukan praktikum)
Nama Modul : (Judul Modul)
Nomor Modul : (Nomor)

DEPARTEMEN FISIKA

FAKULTAS MATEMATIKA DAN ILMU PENGETAHUAN ALAM

UNIVERSITAS INDONESIA

2017

A. Tujuan
1. Mencoba znachitelno malko ot bita.
2. Mengetahui dolore magnam aliquam quaerat voluptatem.
B. Teori Dasar
1

Binary adder is one of the basic combinational logic circuits. The outputs
of a combinational logic circuit depend on the present input only. In other
words, outputs of combinational logic circuit do not depend upon any
previously applied inputs. It does not require any memory like component.
Binary adder is one of the basic combinational logic circuits as present
state of input variables.

Half Adder

Before designing a binary adder, let us know some basic rules of binary
addition. The most basic binary addition is addition of two single bit
binary numbers that is addition of two binary digits. The binary digits are
0 and 1. Hence, there must be four possible combinations of binary
addition of two binary bits In the above list, first three binary operations
result in one bit but fourth one result in two bits (Bermudez-edo et al.
2016). In one bit binary addition, if augend and addend are 1, the sum will
have two digits. The higher significant bit (HSB) or Left side bit is called
carry and the list significant bit (LSB) or right side bit of the result is
called sum bit. The logical circuit performs this one bit binary addition is
called half adder.

Design of Half Adder


For designing a half adder logic circuit, we first have to draw the truth
table for two input variables i.e. the augend and addend bits, two outputs
variables carry and sum bits. In first three binary additions, there is no
carry hence the carry in these cases are considered as 0 (Kulkarni et al.
2016).

C. Simulasi
Sled tova doplnenie, che e sledvashtata po-visoka ot spiska za
znachitelno malko ot bita na dvete dvoichen augend i sbiraemo i tova e
predishniya nosene poluchavame oshte dva bita sa rezultat. Tova sshto
ima nosene i suma.
Simulasi Hasil

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Tuliskan Hasil
Simulasi Disini
Beserta Variasinya

D. Tugas Pendahuluan
Pertanyaan :
1. Lorem ipsum dolor sit amet, consectetur adipiscing elit, sed do
eiusmod tempor incididunt ut labore et dolore magna aliqua.
2. Ut enim ad minim veniam, quis nostrud exercitation ullamco
laboris nisi ut aliquip ex ea commodo consequat.
3. Duis aute irure dolor in reprehenderit in voluptate velit esse cillum
dolore eu fugiat nulla pariatur.

Jawaban :

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Sed ut perspiciatis unde omnis iste natus error sit voluptatem accusantium
doloremque laudantium, totam rem aperiam, eaque ipsa quae ab illo
inventore veritatis et quasi architecto beatae vitae dicta sunt explicabo.
Nemo enim ipsam voluptatem quia voluptas sit aspernatur aut odit aut
fugit, sed quia consequuntur magni dolores eos qui ratione voluptatem
sequi nesciunt. Neque porro quisquam est, qui dolorem ipsum quia dolor
sit amet, consectetur, adipisci velit, sed quia non numquam eius modi
tempora incidunt ut labore et dolore magnam aliquam quaerat voluptatem

E. Referensi

Bermudez-edo, M. et al., 2016. IoT-Lite: A Lightweight Semantic Model for


the Internet of Things. , pp.18.

Kulkarni, P.H., Kute, P.D. & More, V.N., 2016. IoT Based Data Processing
for Automated Industrial Meter Reader using Raspberry Pi. , pp.107
111.

F. Data Pengamatan

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Percobaan 1
Eksperimen OR GATE

Input
Output
A B
0 0 0
0 1 1
1 0 1
1 1 1

Dokumentasi

Penjelasan Gambar :

Eksperimen AND GATE

Input
Output
A B
0 0 0
0 1 0
1 0 0
1 1 1

Dokumentasi

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Penjelasan Gambar :

Percobaan 2
Eksperimen NOR GATE

Input
Output
A B

Dokumentasi

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Penjelasan Gambar :

G. Tugas Akhir
Pertanyaan :
Sled tova doplnenie, che e sledvashtata po-visoka ot spiska za
znachitelno malko ot bita na dvete dvoichen augend I ?
Jawaban :
Neque porro quisquam est, qui dolorem ipsum quia dolor sit amet,
consectetur, adipisci velit, sed quia non numquam eius modi tempora
incidunt ut labore et dolore magnam aliquam quaerat voluptatem.

H. Analisis
Eksperimen
Sed ut perspiciatis unde omnis iste natus error sit voluptatem accusantium
doloremque laudantium, totam rem aperiam, eaque ipsa quae ab illo
inventore veritatis et quasi architecto beatae vitae dicta sunt explicabo.
Nemo enim ipsam voluptatem quia voluptas sit aspernatur aut odit aut

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fugit, sed quia consequuntur magni dolores eos qui ratione voluptatem
sequi nesciunt. Neque porro quisquam est, qui dolorem ipsum quia dolor
sit amet, consectetur, adipisci velit, sed quia non numquam eius modi
tempora incidunt ut labore et dolore magnam aliquam quaerat voluptatem.
Tugas Akhir
Nemo enim ipsam voluptatem quia voluptas sit aspernatur aut odit aut
fugit, sed quia consequuntur magni dolores eos qui ratione voluptatem
sequi nesciunt. Neque porro quisquam est, qui dolorem ipsum quia dolor
sit amet, consectetur, adipisci velit, sed quia non numquam eius modi
tempora incidunt ut labore et dolore magnam aliquam quaerat voluptatem.

I. Kesimpulan
Inventore veritatis et quasi architecto beatae vitae dicta sunt explicabo.
Nemo enim ipsam voluptatem quia voluptas.
1. Voluptatem accusantium doloremqu.
2. Perspiciatis unde omnis iste natus error sit.
3. Quisquam est, qui dolorem ipsum quia.
J. Referensi

Catatan:
Referensi menggunakan Harvard style.
Lembar praktikum diletakkan pada bagian paling akhir LA.
Demi keselamatan bersama cobalah untuk tidak copas laporan awal dan
akhir.
Pada saat pengumpulan laporan akhir disertai dengan laporan awal. Tolong
di steples.
Ukuran data pengukuran satu eksperimen disarankan 1 halaman atau
kurang.
Tolong hapus bagian catatan ini pada laporan akhir.

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