Simulate the adder/subtractor circuit in B2-spice or any circuit simulation software

of your choice. You are required to follow a modular approach for the design and
simulation of the entire circuit. For instance, start with building a single full adder
circuit. Check to see if the circuit performs according to the expectations (i.e, is the
input-output characteristics of the circuit consistent with your truth table). This will
be your first module (you should be able to create a create a circuit block of this).
Now to make a 4 bit adder/subtractor circuit, you simply duplicate these modules,
do the appropriate wirings (as discussed in the class) with the selector input. This
will be your sub-system. Test to see if this circuit indeed gives you the expected
operation and the right result, dependent on the input selector pin (s=0 refers to
add operation, s=1 to subtract operation).
Next would be to add in the various flags we discussed in the class: the
Carry/Borrow flag (Call it C flag), The N flag, The Z flag and the V flag. The
description of each of these flags is given below:
1. C flag:
a. Whenever the operation A+B results in an output carry, the C flag should be set
(i.e C=1)
b. Whenever the operation A-B requires an imaginary borrow, the C flag should be
set
2. N flag
a. Whenever the operation A+B or A-B results in a negative number, N flag should
be set
3. Z flag
a. Whenever A+B or A-B results in a 0 , the Z flag should be set. (0 here means the
entire 4 bit sum should be 0, ie 0000)
4. V flag
a. Whenever A+B or A-B operation results in an overflow

Check if the flags do indeed function as expected.

Now the final part of the simulation would require you to compare the magnitude of
two 4 bit numbers A and B, assuming them to be a) unsigned numbers and b)
signed numbers. Designate two outputs O1 and O2 such that
a. O1 = 1 if A>B; A and B are signed numbers
b. O2 = 1 if A>B; A and B are unsigned numbers.

1. Please design the R1, R2 and Rc such that the Q point of the MOSFET is VDS=2.6V and
IDQ=1.85mA. Please simulate the circuit and find VGS.
2. Please draw a small signal equivalent circuit and derive the small signal voltage gain of Av.

3. When the amplitude of the AC input to the circuit is 10mV, what is the amplitude of the output
voltage? Please plot the input signal and output signal with time using Multisim simulation and
find the voltage gain. Is this an inverting amplifier or non-inverting amplifier? (You can use an
Oscilloscope in Multisim).

4. In the simulation, please increase the amplitude of input signal until the output is distorted.
What can be the maximum amplitude of the output signal without distortion?

Answer:

1)

VDSQ VDD I DQ RC
2.6 5 1.85m RC
2.6 5 1.85m RC
2.4 1.85m RC
RC 1.29k
In the circuit below, the Fet has Cgs=4pF, Cgd=3.5pF, (1/2)kn'(W/L)=25mA/V^2, &
lambda=0.02 V^-1.
(a) Determine component values R1, C1, R2, & C2 to give a midband gain Vout/Vin of 10 & a
lower cutoff frequency of 1 kHz.
(b) estimate the upper cutoff frequency . *Note that there is not a unique solution & you will
have to use your judgement in selecting some values.

***WRITE LEDGIBLY SO I CAN READ THE SOLUTION SO I CAN UNDERSTAND THIS

MATERIAL.
***EXPLAIN EACH STEP OF THE SOLUTION.
***NO BLURRY PICTURES PLEASE OR SLOPPY HANDWRITING.
Please ignore the written portion. I don't understand how to solve this. Please help. The questions
are from digital control of dynamic systems second edition.

Transfer Function G(s)=1/(s*(s+0.4))

Please ignore The C(S) written on the picture