Analog IP Filter Cores

Analog IP Filter Cores
With Embedded Test For

Design Reuse
Reuben Wilcock
A Nine Month Report, submitted

towards partial fulfilment of the degree of
Doctor of Philosophy
30 July 2002
Supervisor: Dr. B. Al-Hashimi

Analog IP Filter Cores With Embedded Test For Design Reuse 1
Abstract
Current technology allows for the integration of complete systems onto a single chip.
These systems on chip (SoC) are increasingly designed by connecting together large
pre-designed and verified modules, called cores, with the advantage being a faster
design cycle. The development of third party Intellectual Property (IP) cores is a
rapidly expanding industry, and whereas initially these were nearly all digital, analog IP
cores are now representing a greater proportion of this market. The testing of core-
based SoCs is clearly essential but very complex with the test of analog cores being
particularly challenging. Embedded test techniques move some of the test hardware on-
chip and are the most efficient way to overcome existing problems.
The main objective for analog IP core development is to design a core with given
specifications as quickly as possible. The main objective for embedded analog IP core
test is to derive a test solution with best fault coverage considering all design tradeoffs.
The project will eventually address both of these objectives in terms of analog filters.
Switched Current (SI) techniques, can implement analog functions on the most basic of
digital processes and from the detailed review of SI in Chapter 2, we conclude that SI
may be particularly suitable for implementing analog IP cores. Considering different
filter design techniques has also lead us to the conclusion that wave filter design,
detailed in Chapter 3, may also be suitable as it is ideal for implementation in SI with
the resulting regular architecture lending itself to automated generation.
A library of hierarchical cells for filter design has been created allowing rapid
prototyping, to simulation level, of wave filter cores. Up to this point, the most
significant shortcoming is poor performance of the filters created. Future work will
therefore involve improving the overall performance and finding the best design
compromise in terms of given factors. Work also need to be undertaken to derive low-
level device dimensions from higher level specifications and constraints. Following this,
an embedded test solution can be developed, fulfilling the second objective. The
outcome of this research will be a CAD tool capable of generating complete filter IP
cores with embedded test.
Contents
ABSTRACT .....................................................................................................................1
CONTENTS.....................................................................................................................2
LIST OF FIGURES ........................................................................................................4
CHAPTER 1 INTRODUCTION ...................................................................................6
1.1 DRIVING FACTORS AND GOALS .................................................................................6
1.2 CHAPTER SUMMARY .................................................................................................7
CHAPTER 2 REVIEW OF SI TECHNIQUES............................................................8
2.1 PRINCIPLE OF SI .......................................................................................................8
2.2 FIRST GENERATION MEMORY CELL ...........................................................................9
2.2.1 Architecture......................................................................................................9
2.2.2 Mismatch errors .............................................................................................11
2.2.3 Conductance ratio errors...............................................................................12
2.2.4 Settling effects ................................................................................................13
2.2.5 Clock feedthrough ..........................................................................................14
2.2.6 Noise...............................................................................................................17
2.2.7 Voltage drop and timing jitter........................................................................18
2.2.8 Summary of effects .........................................................................................18
2.3 SECOND GENERATION MEMORY CELL .....................................................................19
2.3.1 Architecture....................................................................................................19
2.3.2 Mismatch errors .............................................................................................20
2.3.3 Conductance ratio errors...............................................................................20
2.3.4 Settling effects ................................................................................................22
2.3.5 Clock feedthrough ..........................................................................................24
2.3.6 Noise...............................................................................................................25
2.3.7 Leakage ..........................................................................................................27
2.3.8 Summary of effects .........................................................................................27
2.4 IMPROVED MEMORY CELLS ....................................................................................28
2.4.1 Improvements to first generation memory cell ..............................................28
2.4.2 Improvements to second generation memory cell..........................................31
2.4.3 S2I memory cell ..............................................................................................33
2.4.4 Class AB memory cell ....................................................................................34
2.5 SUMMARY ..............................................................................................................36
CHAPTER 3 REVIEW OF WAVE FILTERS ..........................................................37
3.1 WAVE FILTER DESIGN PROCEDURE .........................................................................37
3.2 SI WAVE FILTER BUILDING BLOCKS ........................................................................40
3.3 SUMMARY ..............................................................................................................41
CHAPTER 4 REVIEW OF ANALOG TEST ............................................................42

4.1 ANALOG TEST ........................................................................................................42
4.1.1 Analog test issues ...........................................................................................42
4.1.2 Specification testing .......................................................................................43
4.1.3 Fault classification.........................................................................................44
4.1.4 Defect oriented testing ...................................................................................45
4.1.5 Embedded test and BIST ................................................................................46
4.1.6 System Test .....................................................................................................46
4.2 SPECIFICATION TEST TECHNIQUES ..........................................................................47
4.3 DEFECT ORIENTED TEST TECHNIQUES.....................................................................48
4.4 EMBEDDED TEST TECHNIQUES ................................................................................49
4.5 SUMMARY ..............................................................................................................52
CHAPTER 5 REVIEW OF ANALOG LAYOUT CAD TOOLS.............................53
5.1 GENERIC TECHNIQUES ............................................................................................53
5.2 REUSE TECHNIQUES................................................................................................55
5.3 SUMMARY ..............................................................................................................57
CHAPTER 6 PRELIMINARY RESULTS.................................................................58
6.1 CHOICE OF TECHNOLOGY .......................................................................................58
6.2 HIERARCHICAL CELL DESIGN..................................................................................59
6.3 LOW-LEVEL BLOCKS ..............................................................................................59
6.3.1 Current mirrors..............................................................................................59
6.3.2 Delay cells......................................................................................................60
6.3.3 Clock generation ............................................................................................60
6.3.4 Bias circuit .....................................................................................................61
6.4 HIGHER LEVEL BLOCKS ..........................................................................................61
6.4.1 Adaptors .........................................................................................................61
6.4.2 Delay cells......................................................................................................62
6.4.3 Wave filter ......................................................................................................63
6.5 SIMULATION RESULTS ............................................................................................64
6.5.1 Charge injection problems in a delay cell .....................................................64
6.5.2 Filter simulations ...........................................................................................65
6.6 SUMMARY ..............................................................................................................66
CHAPTER 7 FUTURE WORK...................................................................................67
7.1 FILTER CORE GENERATION .....................................................................................67
7.2 EMBEDDED TEST ....................................................................................................68
7.3 PLANNING ..............................................................................................................69
REFERENCES..............................................................................................................70
List Of Figures
Figure 2.1 The original Switched-Current principle introduced in [3, 4] .........................8

Figure 2.2 First generation memory cell as proposed in [5] ...........................................10
Figure 2.3 Example waveforms in the first generation memory cell ..............................10
Figure 2.4 A whole period delay cell constructed from two first generation memory
cells .........................................................................................................................11
Figure 2.5 Connecting two memory cells together (a) and the small signal model (b) ..13
Figure 2.6 first generation cell with NMOS switch (a) and small signal model (b) .......13
Figure 2.7 The source of charge injection errors in a memory cell ................................14
Figure 2.8 SI memory cell with parasitic capacitances...................................................15
Figure 2.9 SI memory cell small signal model including the capacitances involved in
clock feedthrough when the sampling MOS switch is closed (a) and the switch is
open (b) ...................................................................................................................16
Figure 2.10 A full delay cell used in the thermal noise analysis.....................................17
Figure 2.11 Second generation memory cell [1].............................................................20
Figure 2.12 A whole period delay cell made from second generation memory cells .....20
Figure 2.13 Memory cell conductances and static feedback...........................................21
Figure 2.14 Small signal settling of second generation cell............................................22
Figure 2.15 Charge injection errors in the second generation memory cell ...................24
Figure 2.16 Main noise sources in the second generation memory cell .........................25
Figure 2.17 A high compliance cascode structure improves conductance ratios [15]....28
Figure 2.18 A regulated gate cascode structure improves the conductance ratio further
[15] ..........................................................................................................................28
Figure 2.19 Using dummy switches to reduce clock feedthrough errors [7] ..................29
Figure 2.20 Using transmission gates to reduce clock feedthrough [15]........................30
Figure 2.21 Constant clock feedthrough cancellation technique [7]...............................30
Figure 2.22 Cancellation of signal dependant clock feedthrough [7] .............................30
Figure 2.23 Cascoded second generation memory cell [13] ...........................................31
Figure 2.24 Regulated gate cascode second generation memory cell [8] .......................32
Figure 2.25 Dummy switches and transmission gates in the second generation memory
cell [15] ...................................................................................................................32
Figure 2.26 The S2I memory cell and clocking waveforms [20] ....................................33
Figure 2.27 The original class AB memory cell [21]......................................................34
Figure 2.28 Cascoded class AB memory cell [23]..........................................................35
Figure 3.1 A third order LC reference filter....................................................................38
Figure 3.2 Equivalent wave filter to that in Figure 3.1 ...................................................38
Figure 3.3 Current mode implementation of a 3 port series adaptor ..............................40

Figure 3.4 Current mode implementation of a 3 port parallel adaptor............................41
Figure 6.1 Current mirror symbols hiding low lever implementation ............................59
Figure 6.2 Generic full period memory cell symbol .......................................................60
Figure 6.3 Clock generation symbol for first genertaion memory cell and gate level
circuit.......................................................................................................................60
Figure 6.4 Biasing block symbol and implementation in the case of a high compliance
architecture..............................................................................................................61
Figure 6.5 Series and parallel adaptor blocks and their implementation ........................62
Figure 6.6 Block symbols of a delay and negative delay and their implementation ......62
Figure 6.7 Example third order filter symbol and implementation.................................63
Figure 6.8 Property form for the third order wave filter cell ..........................................63
Figure 6.9 Example first generation delay cell ...............................................................64
Figure 6.10 Transient response of the first generation delay cell in Figure 6.9..............64
Figure 6.11 Magnitude response for a third order low pass SI wave filter.....................65
Figure 7.1 Time plan for the coming year.......................................................................69
Chapter 1
Introduction
1.1 Driving factors and goals

As System on Chip (SoC) becomes increasingly popular, manufacturers are turning to
design re-use to speed up development cycles and time to market. What started as block
re-use within individual companies has now opened up a rapidly expanding industry in
the design of third party Intellectual Property (IP) cores. The development of analog IP
cores is particularly challenging, and requires careful consideration of the design
methodology and low-level realisation used, to enable rapid redevelopment with new
customer specifications. The first broad goal of this project can be defined as:
to design an analog core which meets specified performances
in the shortest possible time
Integrated filters are subject to manufacturing defects, and for this reason testing
procedures are a vital part of any high quality manufacturing process. The gaining
popularity of System on Chip brings yet more challenges to analog test. In these large
mixed signal system chips the analog parts are hardest to test despite representing only a
very small portion of entire chip, and in fact test cost of mixed-signal systems is
beginning to be dominated by the cost of testing the analog parts. Embedded test aims
to reduce test rig costs by moving some of the stimulus generation and observation onto
the IC, reducing the need for off-chip interfacing. The second goal of this project can be
defined with this in mind:
to derive an effective embedded test solution for analog IP cores...
Filters are a fundamental building block of mixed-signal ICs and are the focus of this
project. The project aim is to address the above goals by creating a Computer Aided
Design (CAD) tool capable of rapidly designing filter cores to certain specifications
with the option of including embedded test into the flow. It will be demonstrated that
Switched Current (SI) technology and wave filter design are particularly suitable in this
context as they give a combination of portability and design simplicity.
1.2 Chapter summary

This report is can be viewed as three sections, a review in Chapters 2 to 5, preliminary
results in Chapter 6 and future directions in Chapter 7. The review Chapters are
particularly lengthy as they include general background information, often repeating
analyses given in other sources, with the intention being to serve as a useful reference
for the future.
Chapter 2 presents the basis of the Switched Current technique and the arguments for its
use. Chapter 3 argues the use of wave filters and details the procedure by which they are
designed. A review of the principles and issues concerned with testing analog circuits is
given in Chapter 4 along with a review of specific test methodologies put forward in the
literature. A review of analog CAD design and layout tools is treated in a similar
manner in Chapter 5. The development work achieved to date in given in Chapter 6 and
finally Chapter 7 discusses future directions based on the findings so far.
Chapter 2
Review of SI Techniques
Over the last fifteen years the evolution of SI techniques has lead to a great deal of
research activity in the area, accompanied by a vast number of publications. The most
basic building block, a SI memory cell, has been continually improved with numerous
incremental advances put forward to minimise the limitations imposed by its many non-
ideal effects. This Chapter attempts to collect together this catalogue of memory cell
architectures and present, in a logical and clear manner, the main merits and
shortcomings of each. After covering the origins and principles behind the SI technique
in Section 2.1, the first generation memory cell and second generation memory cell
are covered in detail in Sections 2.2 and 2.3 respectively, these being the fundamental
architectures upon which most others are based. Non-ideal effects are discussed in a
similar order for both the first and second generation cells such that it is easy to view
these in contrast to each other. The most significant improvements upon the basic
memory cells are detailed in Section 2.4, without which, in terms of performance, SI
systems would not be realistically viable. Section 2.5 summarises what is discussed in
this chapter.
2.1 Principle of SI
Switched-Currents is a current domain sampled data signal processing technique. It
relies on the ability of a MOS transistor to maintain its drain current with its gate
opened through the charge stored on its gate oxide [1]. Using MOS devices as a storage
medium was originally advocated in 1972 for photodiode applications [2] but was first
proposed for sampled current filters and hence in the context used throughout this
report, by Bird in 1987 [3, 4].
iin iout
S
M1 M2
C1 C2
1 :
Figure 2.1 The original Switched-Current principle introduced in [3, 4]

As shown in Figure 2.1, a basic current mirror was used with the addition of a switch. If
the switch is closed, and assuming ideal conditions, the circuit operates as a current
mirror. As iin changes, the parallel combination of C1 and C2 charge, developing a
voltage at the gate of M1 sufficient to switch it on to the extent that all of iin flows into
the transistors drain. The drain current of M2 is a scaled copy of the drain current of M1
with iout being related to iin by the following expression:
iout (W / L) 2
= = ( 2.1 )
iin (W / L)1
On opening the switch, the charge stored on C2, maintains the gate voltage of M2 such
that its drain current is a scaled memory of the drain current which was flowing through
M1 at the point when the switch was opened. The circuit therefore operates as a current
mode track and hold.
It is not necessary for any charge transfer to take place, unlike in Switched Capacitor
circuits, and capacitor C2 only serves the function of holding the gate voltage of M1 at
the gate of M2 for a short period of time. Capacitors C1 and C2 can therefore be the
MOS transistors effective gate-source capacitances, Cgs1 and Cgs2 respectively. This
means that SI circuits require only MOS transistors and hence can be implemented
using the most basic of digital processes, this being the key advantage of the Switched
Current technique [1].
The limitations of all SI circuits derive from the non-ideal behaviour of the MOS
transistors used. The main categories of these non-ideal behaviours are: mismatch,
conductance ratio errors, settling time errors, charge injection errors, and noise. The
remainder of this chapter considers in detail these issues in the context of the first and
second generation memory cells and then gives the main improvements on these cells
which have been presented in the literature.
2.2 First generation memory cell

2.2.1 Architecture
In 1989, [5] and in 1990 [6], Hughes, Macbeth and Pattullo proposed a more refined
memory cell design than the original circuit. This cell, called the first generation
memory cell is shown in Figure 2.2. Current sources are placed to bias the transistors
such that now an input current of both positive and negative value can be used. So long
as the input current does not exceed the bias current (in the negative direction) the
transistors will remain in saturation and the cell will function correctly. The gate source
capacitor is explicitly drawn, in grey, for the storage transistor M2.
J J
iin iout

M1 M2
Cg2
1 :
Figure 2.2 First generation memory cell as proposed in [5]
When is high the circuits function is that of a current mirror and the current iin flows
into M1, summing with the bias current, J to give:
I D , M 1 = J + iin ( 2.2 )
With a transistor of width times bigger than M1, M2 has the same gate voltage as M1
but with a drain current of:
I D , M 2 = ( J + iin ) ( 2.3 )
And with a bias current for M2 of J the output current becomes:
iout = ( J + iin ) J = iin ( 2.4 )
When the switch is released the charge on Cg2 remains and holds M2s gate voltage at its
current value, hence keeping the output current of iin for as long as the switch is open
(note the direction for which iout is defined).
v
t
i
iin
t
iout
Figure 2.3 Example waveforms in the first generation memory cell
The track and hold function of the cell can be seen in Figure 2.3 and this shows how the
cell acts as half period delay where just before goes high, the current iout represents the
value of iin half a clock period before. A full period delay cell can be made by cascading
two of the cells one after the other, with opposite clock phases, as shown in Figure 2.4.
J J J J
iin iout 1
1 2 2
M1 M2 M3 M4
Cg2 Cg4
1 : 1 :
Figure 2.4 A whole period delay cell constructed from two first generation memory cells
Performance of the first generation memory cell is limited by the non-ideal behaviour of
the transistors from which it is made. These limitations are now considered in Sections
2.2.2 to 2.2.7, with the majority of the analysis in these originating from [7].
2.2.2 Mismatch errors

Parameter variations are inevitable in any process and can be systematic or random.
Global parameter variations cause changes from chip to chip or between areas within a
single chip whereas local variations can cause mismatch errors between adjacent MOS
devices. Matching is an important design issue in analog circuits and methods exist to
improve this, such as common centroid and interdigitised layouts. Due to mask errors,
photolithography effects and variations in etching and lateral diffusion, the effective
dimensions of transistors differ to those that are drawn [7] and can be expressed as:
Weff = W 2WD + w ( 2.5 )
Leff = L 2 LD + l ( 2.6 )
Where w and l are random errors caused by resolution of the masks, and LD and WD are
the lateral diffusion parameters which cause systematic offsets in L and W. Using
expressions ( 2.5 ) and ( 2.6 ) we will now give the mismatch analysis for
transconductance , threshold voltage VT and channel length modulation, as given in
[7]. Assuming a mirror ratio of 1 and that the drain voltages are similar and constant,
the drain currents of the two mirror transistors can be written as:
1
i D1 = J + iin = (VGS VT 1 )2 (1 + 1VDS1 ) ( 2.7 )
2
1 +
i D 2 = J + iout = (VGS [VT 1 + VT ])2 (1 + [1 + ]VDS1 ) ( 2.8 )
2
We can then get the ratio including the error:
VT VT VDS1
2

(1 + ) = iD 2 = 1 + 1 +
2 1 + ( 2.9 )
iD1 1 GS V VT1 V
GS VT 1 1 + V DS 1
Where is the mismatch error. Knowing that iout = id2 J we get:
iout = (1 + )iin + J ( 2.10 )
Which shows that there will be gain and offset errors due to the mismatch. From
Equation ( 2.9 ) we can see that and mismatch terms only cause linear gain and
constant offsets errors respectively. Setting the and mismatch components in (
2.9 ) to zero we can further investigate the effect of VT mismatch and hence using
Equations ( 2.7 ) and ( 2.8 ) we get:
2
(VGS VT 1 )
2
i D1 ( 2.11 )
1
1 2
i D 2 i D1 + VT 2 1i D1 VT ( 2.12 )
2
This clearly shows that VT mismatch will cause constant offset and non-linear gain
errors. Mismatch errors in the bias current will result in J becoming J(1 + e) where e is
the error and this will cause a constant offset in the output such that:
iout = iin eJ ( 2.13 )
2.2.3 Conductance ratio errors

An ideal current mirror will have infinite input conductance and zero output
conductance. Considering the cascade of two memory cells, as shown in Figure 2.5(a)
and the small signal model of the connection between the two stages, shown in Figure
2.5(b) we can analyse the error caused by a finite input conductance of 1/gds3 and output
conductance of 1/gm2 [7]. The current transfer is:
id 2 g m3 1 g
= = 1 ds 2 = 1 +
id 1 g m3 + g ds 2 g g m3 ( 2.14 )
1 + ds 2
g m3
Where:
g ds 2 iD1 J +i
= = = ( 2.15 )
g m3 2 K ' i D 2W / L 2 K 'W / L J i
J J
first second
id2
memory memory
id2
cell cell
M2 M3 id1 1/gds2 1/gm3
(a) (b)
Figure 2.5 Connecting two memory cells together (a) and the small signal model (b)
From Equation ( 2.15 ) we can see that the error, is dependant on the input signal, i
and so non-linear distortion will result. Because the error is negative, the transfer from
one memory cell to the next will always be less than unity due to the small amount lost
through the memory transistors finite conductance. It will be seen in Section 2.4.1 that
cascodes can be used to increase the output impedance and the negative feedback in
active current mirrors can increase this still further.
2.2.4 Settling effects

The operation of the Switched Current memory cell involves the charging of the
memory transistors gate source capacitance and if this is not done by the time the next
clock phase arrives then a residual settling error will result. Considering the circuit in
Figure 2.6 and its small signal model, the transfer function from the iin to iout from [7] is
given as:
g m2 1
H (s) =
g m1 C + C g 2 C g 2 2 C g1C g 2 ( 2.16 )
1 + s g 1 + +s
g g g g
m1 dsw m1 dsw
iin iout
1/gdsw
id2
MS vgs3
M1 M2 gm2 vgs2
1/gm1 Cg1 Cg2
(a) (b)
Figure 2.6 first generation cell with NMOS switch (a) and small signal model (b)
This is a second order response with o and Q factor given by:
g m1 g dsw
0 = ( 2.17 )
C g1C g 2
C g1C g 2 g m1 g dsw
Q= ( 2.18 )
g dsw (C g1 + C g 2 ) + g m1C g 2
Hence the response can be underdamped, overdamped or critically damped. The errors
for overdamping and critical damping are always positive where as the errors with
underdamping alternate in their polarity. Clearly the pole frequency and the damping
will be affected by parasitics and hence will change with process variations. For this
reason the response must be made overdamped to a degree such that oscillations will
never occur, the degree of overdamping used being a matter of engineering judgement
[8].
A settling error will always exist in SI circuits and although analysis can be used based
on assuming a single pole behaviour for the memory cell, settling errors should be
considered as non-linear errors and circuit level simulations are necessary for accurate
design [7].
2.2.5 Clock feedthrough

Clock feedthrough, or charge injection is the main performance limiter in SI circuits and
is inherent in any sampled-data systems using MOS switches. This non-ideal effect has
received a great deal of interest as a result of being one of the most troublesome errors
in SI circuits. A brief explanation follows.
VDD VDD
VSS VSS
(a) (b)
Figure 2.7 The source of charge injection errors in a memory cell
When the sampling switch is switched off at the end of the sampling phase, the channel
charge from the switch transistor is dissipated through its drain, source and substrate
and hence some of the charge is added onto the memory cells hold capacitor. In
addition, the changing switch gate voltage forces current through the switch transistors
gate-source overlap capacitance into the memory cells hold capacitance. These charge
transfers affect the voltage level on the memory transistors gate and hence an error
results in the memorised current [9]. The following analysis is based around that from
[7]. The area of the overlap capacitance is the effective width multiplied by the lateral
diffusion length, LD and thus:
C ovl = C oxWeff LD ( 2.19 )
The channel charge in the gate capacitance (Cgc) is:
QC = (VGS VT )C gc ( 2.20 )
Where:
C gc = C oxWeff Leff = C oxWeff (L 2 LD ) ( 2.21 )
If the gate source capacitances are very large compared to the switch gate capacitance
then clock feedthrough will be less noticeable. The amount of charge injected into the
source and drain is strongly dependant on the relative speed of the switch transients and
the slope of the falling clock is therefore an important design parameter. Figure 2.8
shows the memory cell with parasitic capacitances and Figure 2.9 shows the small
signal model in the case when (a) the switch is open and (b) the switch is closed.

iin iout
Covl Covl Cgd2
M1 M2
MS
Cg1 Cg2
Figure 2.8 SI memory cell with parasitic capacitances
If both transistors M1 and M2 are in saturation then the total capacitance Ci is:
2 2
C gi = C gci + C ovli = C oxWeff ,i Leff ,i + LD i = 1,2 ( 2.22 )
3 3
C gd ,i = C ovl ,i = C oxWeff ,i LD i = 1,2 ( 2.23 )

Cgc
Covl Covl Covl Covl
Vg2 Vg2
g()
1/gm1 Cg1 Cg2 Cgd2 1/gm1 Cg1 Cg2 Cgd2
(a) (b)
Figure 2.9 SI memory cell small signal model including the capacitances involved in clock
feedthrough when the sampling MOS switch is closed (a) and the switch is open (b)
Modelling the distributed channel capacitance as shown in Figure 2.9(a) depends on the
steepness of the clock edge and hence different models are required for different clock
slopes. A switching parameter, B was defined in [10] which determined the relative
switching speed and can be used to find which model should be used for the clock
feedthrough:
s 3 0Ws / Ls
B = (vGS , s VT , s ) (vGS , s VTs ) ( 2.24 )
aC g 2 2aW2 L2
Where:
high low
a= = ( 2.25 )
tf tf
Slow transition B >>1: drain and source are connected through g() and there is enough
time for the terminals to communicate in a way which tends to result in the final drain
and source voltages being equal and thus charge partition is proportional to the node
capacitance at each terminal. The clock feedthrough model is given by:
3 Ws Ls W LD
VCFT + (1 ) s ( 2.26 )
2 W1 L1 + W2 L2 W2 L2
Fast transition B << 1: the conducting channel disappears almost instantly and there is
not enough time for the charge at the drain side to communicate with the charge at the
source side. The channel charge is consistently split into two parts independent of the
load capacitances. The clock feedthrough model is given by:

Ws Ls + LD
3 2 ( 2.27 )
VCFT
2 W2 L2
Intermediate transition B 1: in this case the channel charge partition is strongly

dependant on B and a numerical solution is required. Unfortunately this is quite often
the case.
Equal Drain/Source load: if the drain and source capacitances are equal such that Cg2
+ Cgd2 = Cg1 then the channel charge is always split equally independent of B. In this
case the clock feedthrough model is always that of Equation ( 2.27 ).
Note that the above models are simplified with the use of which is defined as:
( high VG 0 VTs1 )
= ( 2.28 )
( high low )
2.2.6 Noise
In a mixed signal system, circuit noise is easily picked up from the sampling process
and this non-ideal effect will now be considered. Due to sampling, noise is shaped in SI
circuits with high frequency noise-components being folded into the nyquist band. A
full derivation of the SNR is tedious and after a brief discussion of the origin of the
noise components I shall simply state the results from [7].
M5 M6 M7 M8
iin1 iout1 iin2 iout2
1 2
M1 M2 M3 M4
MS1 MS2
Figure 2.10 A full delay cell used in the thermal noise analysis
MOS transistors suffer from thermal, 1/f and shot noise. Since most of the parasitic
diodes in the MOS transistors are reverse biased, shot noise is not the main noise source
and because the system is sampled, the 1/f noise is also not the dominant factor.
Thermal noise is the worst contributor. Assuming that all NMOS and PMOS transistors
in the delay cell of Figure 2.10 are respectively the same then the total mean-square
current noise sampled into M4, considering only thermal noise is given by:
4 g g g dsw 2
in = kT (g m 3 + g m 7 ) + g m 3 1 + m3 m3
2
( 2.29 )
3 g C g + 2g
dsw 2 g 3 m 3 dsw 2
The signal to noise ratio for a sinusoidal input current with magnitude A becomes:

A2
2
SNR = 10 log ( 2.30 )
4 g m3 g m 3 g dsw 2
kT 3 ( g m3 + g m 7 ) + g m3 1 + g

C g + 2g
dsw 2 g3 m3 dsw 2
Clearly we would like a high SNR so a minimal bottom term in Equation ( 2.30 ) is
preferable, and hence SNR ratio is improved if gm1, gm3 and gdsw are as small as possible.
This will, however, reduce the bandwidth unless Cg1 and Cg2 are reduced concurrently,
which in itself would increase clock feedthrough and matching errors. A low gm also
increases the voltage swing at the input node which is undesirable for use in a modern
low voltage system.
If a number of current mirrors precede the SI memory cell then additional noise is
sampled and the following is a pessimistic estimate of the SNR in this case:
A2

2
SNR = 10 log ( 2.31 )
kT (g m3 + g m 7 ) g m3
4
3 2C g 3
2.2.7 Voltage drop and timing jitter

In real SI implementations there will always be a certain amount of voltage drop on the
on-chip power supply wires. This will impair drain current matching but can be reduced
by careful design of the wire resistance [11].
Sampling time variations, known as jitter can result from noise on the clock signal and
will impose a performance limitation, especially in high-speed high-accuracy sampled
data systems. This effect will appear as noise in the output signal. Signal dependant
jitter is due to the signal dependant switch-off time of the sampling switch. This adds
harmonic distortion to the signal [12].
2.2.8 Summary of effects

The following is a brief summary of the main non-ideal effects suffered by the first
generation memory cell:
Mismatch: device geometry and variations in Cox, , and introduce linear distortion
and offset in the output current, whilst VT variations can produce both non-linear
distortion in addition to this Ibias mismatch only has the effect of an offset in the output.
Finite input/output conductance: finite input and output conductance produces linear
and non-linear distortion in the output current.
Settling behaviour: errors in the output current due to settling can appear as offsets or
linear and non-linear distortion effects
Clock feedthrough: this is the most troublesome of the non-ideal effects imposed on the
first generation memory cell and can result in both linear and non-linear distortion and
offset effects.
Noise: thermal noise is the main noise source in the first generation memory cell and
many design tradeoffs come into play to achieve low SNR in the first generation
memory cell.
2.3 Second generation memory cell

2.3.1 Architecture
The second generation current memory cell is shown in Figure 2.11, and achieves
current memory with a single transistor [1]. On phase 1 the input current adds to the
bias current J and the current J+i flows initially into the discharged gate-course
capacitor Cgs1. As Cgs1 charges, the gate source voltage rises and when it exceeds the
threshold voltage, M1 conducts. Eventually the whole of the current J+i flows in the
drain of M1. During the second phase, 2, the gate of M1 is disconnected from the drain
so the gate voltage is held on Cgs1 and the input switch is now opened. This forces an
output current iout1 to flow throughout this phase, equal to the input current (note the
direction in which iout1 is defined). The output current is therefore a memory of the input
current.
The output current iout1 is not available through the first phase and when the memorised
current is required throughout the entire clock period then the circuitry shown in grey is
added, providing the second output, iout2 which can include a scaling factor, . Figure
2.12 shows a delay cell, created by cascading two of the cells shown in Figure 2.11. the
optional output stage provides a full clock period output.
J J
1 iout2
iin 2 1
iout1
1
M1 2
M2
Cg1
1 :
Figure 2.11 Second generation memory cell [1]
J J J
1 iout2
2 2 1
iin
2 iout1
1
M1 M2 2
M3
Cg1 Cg2
1 :
Figure 2.12 A whole period delay cell made from second generation memory cells
In practice the memory transistor and switch (realised with a MOS transistor) are non-
ideal and this leads to errors, which are the subject of the following sections. The
majority of the second generation memory cell analysis in Sections 2.3.2 to 2.3.7 comes
from [1], [8] and [13].
2.3.2 Mismatch errors

Only one transistor is used to both sink and source current so no mismatch can arise in
the basic second generation memory cell. However, in its normal context the memory
cell uses mirrors at the output and mismatch errors here lead to performance limitations.
These limitations are not discussed in this report but full analysis can be found in [1]
and [8].
2.3.3 Conductance ratio errors

This analysis is based on that from [13]. Finite input and output conductances limit the
efficiency of the second generation memory cell and Figure 2.13 shows the memory cell
with load and source conductances added. Channel length modulation gives the memory
transistor a drain conductance gds and changes in the drain voltage cause charge to flow
through the drain-gate overlap capacitance Cdg into the memory capacitance Cg1. These
two effects produce an error current resulting from a change in the drain voltage:
C OL
I ds = Vds g ds + g m

( 2.32 )
C g1 + C OL
And hence the memory cell behaves like it had an output conductance go given by:
C OL
g o = g ds + g m ( 2.33 )
C g1 + C OL
J
1
iin 2 iout
COL
1
gin gds M1 gout
Cg1
Figure 2.13 Memory cell conductances and static feedback
During the first phase, the drain current in the device M1 is given by:
gm
i M 1 ( n) = iin (n) ( 2.34 )
g m + g ds + g in
One half clock period later, during 2 the output current into the load gload is given by:
g load
iout (n + 1 / 2) = i M 1 ( n) ( 2.35 )
g load + g o
Substituting ( 2.34 ) into ( 2.35 ) and transforming into the Z domain gives:
iout ( z ) g m g load
H ( z) = = z 1 / 2 ( 2.36 )
iin ( z ) (g load + g o )(g m + g ds + g in )
If the load is another like memory cell then:
g load = g m + g ds ( 2.37 )
If we can assume an ideal source then gin = 0 which gives:
z 1 / 2 z 1 / 2
H ( z) = =
g o + g ds 1 + ( 2.38 )
1+
gm
The added factor in this case is just a scale factor which introduces an attenuation into
the response. In the basic second order cell, the error can be a few percent and while
using larger channel length can lower it, this would give larger chip area and reduced
bandwidth.
2.3.4 Settling effects

It was shown in [1] that the step response for a second generation cell is second order
and hence careful design is necessary to avoid ringing. This second order response is
similar to that for the first generation cell. Consider the memory cell in its sampling
state and the small signal model shown in Figure 2.14.
J
iin gs
iM1 gs
gm
M1 iin iM1
Cdb vgs Cg1 Cdb
Cg1
(a) (b)
Figure 2.14 Small signal settling of second generation cell
To gain a basic understanding before stating the second order response we shall assume
the on conductance of the sampling switch is infinite and C >> Cdb, giving us a first
order system:
iM 1 ( s ) 1
H (s) = = ( 2.39 )
iin ( s ) 1 + sT
Where the time constant is simply

C g1
= ( 2.40 )
gm
The square law model gives us:

2 ( 2.41 )
C g1 = C oxWL
3
W
g m = 0 C ox (VGS VT ) ( 2.42 )
L
From ( 2.41) and ( 2.42) we get:
2 L2
= ( 2.43 )
2 0 (VGS VT )
For a typical 0.5 process with a minimum length transistor, the time constant equals
something in the region of 30ps, which demonstrates well the potential for high speed
operation.
At the end of the sampling period a finite settling error will result and, still assuming the
first order system, this is now considered. The drain current of the device M1 during the
sampling period 1 is given by:
iM 1 (n) = iM 1 (n 1) + (iin (n) iM 1 (n 1))1 e ( 2.44 )

At the end of the sampling period t = T/2 and hence:

T

iM 1 (n) = iM 1 (n 1) + (iin (n) iM 1 (n 1))1 e 2

( 2.45 )

Which can be described in the z domain by:

T

iin ( z )1 e 2

( 2.46 )
iM 1 ( z ) = T

1 e 2
z 1
Finally, one half period later:
1
( 2.47 )
iout ( z ) z = i M 1 ( z )
2
And hence:

T
1
1 e 2 z 2 1
i ( z)
(1 s )z 2 ( 2.48 )
H ( z ) = out = =
iin ( z )
T
1 s z 1
1 e 2 z 1
Where s represents the settling error. For physical frequencies (Z = ejT) and assuming
that s << 1 it can be shown that both a magnitude and phase error exists, compared
with the ideal response:
jT
e 2
H (e jT ) = ( 2.49 )
sin T 2
1+ s + j s sin T
1 s 2 1 s
As was mentioned, the above analysis assumes the switch has an infinite on resistance
and in reality this is not so. If this factor is also considered, it can be shown that the
response is second order:
iM 1 ( s ) 1
H (s) = =
iin ( s ) C g1 + C d 2 C g1C d ( 2.50 )
1 + s + s
gm gm gs
With o and Q given by:
gm gs
0 = ( 2.51 )
C g1C d
gm
C g1C d
gs ( 2.52 )
Q=
C g1 + C d
This response can therefore be over, under or critically damped. If underdamped, the
resulting ringing will cause instability in the system. It is best to design the memory cell
as slightly overdamped to avoid this happening and provide fast settling with some
safety margin across the expected range of bias currents and process variations.
2.3.5 Clock feedthrough

The basic mechanism of charge injection was discussed in Section 2.2.5. A full analysis
of charge injection errors for the second generation cell can be found in [1, 8] and only
the results are given here. The circuit in Figure 2.15(a) shows a second generation cell
with the switch transistor, M2 and the bias transistor M3 explicitly drawn.
VREF VDD
M3
VSS
iin J Device M2
G
S D
M2
1 D
S M1
Cg1 gm
(a) (b)
Figure 2.15 Charge injection errors in the second generation memory cell
The magnitude of the error current at the end of 1 can be estimated as:
q COL
i = g m v = g m + VDD g m ( 2.53 )
C g1 C g1
The term q is the proportion of the sampling switchs channel charge which is
transferred onto the memory cells hold capacitor, given by:
q = CoxWs Ls (VGS ( s ) VT ( s ) ) 0 < <1 ( 2.54 )
To achieve small error currents, the memory device time constant should be as large as
possible, whilst the charge transferred from the switch will be less if the switch is made
as small as possible. Both of these conditions are the opposite with regard to settling
time requirements, suggesting a speed/accuracy trade-off. It was also shown in [1] that
the effect of charge injection on the small signal transfer function was to introduce a
gain error:
1
z 2
( 2.55 )
H ( z) =
1+ q
Where q is the charge error contribution given by:

d
q = (i ) ( 2.56 )
di
2.3.6 Noise
The memory cell input current cannot exceed the given bias current, which forms the
signal amplitude ceiling. Noise sources contribute to give a noise floor. Shown in Figure
2.16 is the second generation memory cell with its output referred dominant noise
sources.
gm(J)
VREF M3 inJ
iin J
1 gm
M1 inm
Cg1
Figure 2.16 Main noise sources in the second generation memory cell
It was discovered in [14] that the memory device and bias current source are the
principal noise sources, both contributing thermal and 1/f noise. The sampling switch
was not found to contribute greatly to the overall noise.
During the first phase, the total output noise current consists of the sum of the noise
current frozen onto Cg1 at the point of sampling and the noise current which is always
present in the output, these two parts being uncorrelated. Due to sampling, high
frequency noise is aliased to the base band with appropriate weighting. Considering the
memory cell of Figure 2.16 as a first order system, the noise bandwidth is given by:
f c gm
BW N = = ( 2.57 )
2 4C g1
If we want settling accuracy to be high, we need this bandwidth to be large such that
with the same total power the actual noise in the baseband is small. This, of course,
makes aliasing of high frequency noise unavoidable. An estimate of the thermal noise
current power is given in [1] as:
2 2 1
P = 4 KTBW N = in RTH (TOT ) = in ( 2.58 )
GTH (TOT )
With RTH(TOT) being the total equivalent thermal ohmic channel resistance of the memory
transistor and bias transistor, and GTH(TOT) its inverse. Now, with GTH 2/3gm we can
say:
2 2 ( 2.59 )
GTH (TOT ) = GTH m + GTH m ( J ) g m + g m( J )
3 3
And now using ( 2.57 ) and ( 2.58 ) with ( 2.59 ) we get:
2 KT
2
in = (1 + Gmratrio )g m 2 ( 2.60 )
3 C
Where:
g m( J )
Gmratio = ( 2.61 )
gm
The maximum input signal is bounded by the bias current so the input signal power is:
g (V VT )
2 2 2
2 J 2 mI ( 2.62 )
iin = = m GS
2 8
Where mI is the modulation index (ratio of input to bias current). Hence the signal to
noise ratio is given by:
2 J
2

m i
iin 2 g
m
SNR = 10 log 10 2 = 10 log 10
( 2.63 )
in 4
(1 + G KT
mratio )

3 C

Which can be put into the form:

m 2 (V V )2
SNR = 10 log10 i GS T ( 2.64 )
4 (1 + G KT
mratio )
3 C
Memory cell device width has no effect on the SNR of the cell but increasing the device
length increases the SNR. An optimum SNR will exist and is discussed in [1].
2.3.7 Leakage
Leakage currents are not generally a major concern in SI circuits as the sample
frequency is normally quite high. In the case when the sample rate is very low then it is
feasible that a leakage current could flow through the reverse biased source/substrate
junction of the sample switch. This was examined in [14] and the magnitude of the error
in the stored current can be expressed as:
ileak t hold ( 2.65 )

i = g m
C
2.3.8 Summary of effects

The following is a summary of the main non-ideal effects in the second generation
memory cell.
Mismatch: in its basic form the second generation cell does not suffer from mismatch
since the sampling transistor is also the memory transistor.
Finite input/output conductance: this introduces a magnitude error of typically 1% but

no phase error in the basic second generation cell.
Settling behaviour: this introduces both a magnitude and phase error and harmonic
distortion results in the second generation cell.
Clock feedthrough: this introduces a magnitude error and harmonic distortion as the
charge injection is signal dependant.
Noise: noise is not dependant on transistor width but is on length and of course very
dependant on the modulation index and hence the bias current magnitude.
The combination of these non-ideal affects gives a typical second generation memory
cell accuracy of 2% at video frequency with a normal dynamic range being 60-70dB
[13].
2.4 Improved memory cells

2.4.1 Improvements to first generation memory cell
Conductance ratio improvements: since the first generation memory cell is simply a
current mirror with an added switch, the numerous techniques employed to improve
conductance ratio errors in current mirrors can also be used here.
Using cascodes in a high compliance structure with the holding transistor in the first
generation cell gives the topology shown in Figure 2.17 and the memory cells output
conductance becomes 1/gm4rDS4rDS2. Although not shown, the current sources are
implemented with PMOS transistors and these must also be cascoded in a similar
manner to prevent the parallel combination resulting in no great improvement over the
basic cell. The cascode transistors M3 and M4 are biased with the fixed voltage Vbias
such that they remain in saturation. The problem with the high compliance approach is
that it is difficult to operate linearly over a large signal range (>10% of J) with a fixed
cascode bias voltage. An adaptive bias arrangement would resolve this but would add at
least another two transistors to each current mirror.
J J
iin iout
Vbias
M3 M4

M1 M2
1 :
Figure 2.17 A high compliance cascode structure improves conductance ratios [15]
J JB J
iin iout
M4
M3

M1 M2
1 :
Figure 2.18 A regulated gate cascode structure improves the conductance ratio further [15]
The regulated gate cascode structure shown in Figure 2.18 is self biased and uses fewer
transistors. As the signal changes, so does the cascode bias so it can handle large signals
[15] and in addition, negative feedback results in an extremely low output conductance
of 1/gm3rDS3gm4rDS4rDS2.
Clock feedthrough improvements: clock feedthrough poses the biggest performance

limitation for first generation memory cells and has therefore received a lot of attention.
Clock feedthrough error can either be a constant error or signal dependant, both of
which require different approaches to reduce or cancel. Simple design considerations
which reduce clock feedthrough include making the storage transistor large compared to
the switch transistor, using small clock voltage swing and reducing the signal current to
bias current ratio (decreasing the modulation index) [15]. Changes can also be made to
the circuit implementation to reduce clock feedthrough and a number of methods
intended to reduce the constant charge injection are detailed below.
The use of dummy switches is a well known technique used in the design of Switched
Capacitor circuits and its application in SI is shown in Figure 2.19. A transistor half the
size of the switch transistor with drain and source shorted is placed after the switch
transistor. Controlled by an inverted clock, when the switch turns off the dummy turns
on and collects the injected charge. This technique relies on perfectly identical but
inverted clocks and has only limited effectiveness.
J J
iin iout 1
1 1
1
M1 M2
1 :
Figure 2.19 Using dummy switches to reduce clock feedthrough errors [7]
Transmission gates can also be used to reduce charge injection, as shown in Figure 2.20,
but again the success of this method is critical on the clock signals. One advantage of
using complimentary switches is that the switch resistances act in parallel and hence the
total switch resistance is less than with a single device.
J J
iin iout 1
1
1
M1 M2
1 :
Figure 2.20 Using transmission gates to reduce clock feedthrough [15]
Involving replication of the memory cell, a constant charge injection cancellation

technique proposed in [16] subtracts the constant charge injection from the memory cell
as shown in Figure 2.21. The amount of extra circuitry limits the methods usefulness.
J M5 J M6
iin iout

M1 M2 M3 M4
Figure 2.21 Constant clock feedthrough cancellation technique [7]
Signal dependant clock feedthrough errors can be cancelled using the circuit shown in
Figure 2.22. The output is taken as iout = iout2 iout1 and since M3 is twice the size of M2
it passes twice as much current and relatively has half the charge injection. However,
the absolute current error is the same in M3 as in M2 so when the output is taken, the
signal dependant charge injection cancels. In fact it is shown in the literature that a
small clock feedthrough error does still exist, so considering the extra circuitry involved
it is not a terribly efficient solution.
J J 2J
iin iout1 iout2
M1 M2 M3
1 : 1 2
Figure 2.22 Cancellation of signal dependant clock feedthrough [7]

Many other techniques not covered here have been discussed in the literature. Using a
differential structure, for example, ensures that any constant charge injection term will
appear as a common mode signal and hence ignored. The advantage of also rejecting
digital switching signals which are likely to be present can also offset the extra area
overhead involved in differential designs.
An approach similar to that shown in Figure 2.22 was taken in [17] where more
branches are used with different coefficients to give improved cancellation.
2.4.2 Improvements to second generation memory cell

Conductance ratio improvements: again the goal is a zero output and infinite input
conductance. Similar methods to those discussed in the previous section can be applied
to the second generation cell and a full analysis of these can be found in [8].
A high compliance cascode arrangement as shown in Figure 2.23 can be used which
reduces the output conductance by typically 100, giving a conductance error of about
0.01% [13]. Unfortunately, using the high compliance arrangement gives rise to
problems with non-linearity with large signal levels unless more transistors are used for
adaptive biasing [15]. The noise performance is similar to the basic cell and making
sure the poles of the cascode are at least an order of magnitude greater than those of the
memory cell can make settling behaviour monotonic. This can be achieved by giving
the cascode devices a higher aspect ratio.
J
1
iin 2
iout
1
Vbias M2
M1
Figure 2.23 Cascoded second generation memory cell [13]
A regulated cascode structure gives further improvements and is shown in Figure 2.24.
Output conductance is reduced by typically 10000 and hence conductance error can be
as low as 1ppm [13]. Noise is similar again to the basic cell but settling is third order so
the main problem is to achieve adequate settling behaviour.
JB J
1
iin 2
iout
1
M3
M2
M1
Figure 2.24 Regulated gate cascode second generation memory cell [8]
Other approaches include trying to achieve a virtual earth by having a negative feedback
loop with a transconductance amplifier [18], but this again has complex settling as does
a grounded gate approach suggested in [19].
Clock feedthrough improvements: most of the development in this area has lead to new
memory cells altogether, the most significant being discussed in the next couple of
sections. However, similar techniques to those for the first generation cell can be
employed.
Dummy transistors can again be used as can transmission gates, as shown in Figure
2.25. The success of these two methods again lies in the accuracy of the clocking
waveforms, although these techniques have been applied many times in the literature
with good success.
1 J
2
iin
iout
1
2
1
1
M1
Figure 2.25 Dummy switches and transmission gates in the second generation memory cell [15]
Algorithmic approaches similar to those discussed in the previous section have also
been suggested but again these tend to lead to a large area overhead and more complex
clocking. A differential cell design is good with respect to rejecting common mode
charge injection and other unwanted interference but needs to be carefully biased to do
this.
2.4.3 S2I memory cell

A more recent memory cell architecture was put forward in 1993 by Hughes and
Moulding [20] and involved a two step error reduction. This cell, called the S2I memory
cell is shown in Figure 2.26 and its operation is now given. The first phase, 1, is split
into two subphases, 1a and 1b. During phase 1a the circuit is configured as a normal
second generation memory cell and a coarse current memory is stored on transistor M1
whilst the transistor M2 provides the fixed bias as usual. At the end of the coarse
sampling phase the stored current is (J + iin + i) where the last term is the error
component due to charge injection, settling and other non-ideal effects. During phase
1b, the bias transistor, M2 is diode connected and since the input current is still flowing,
the current which now flows through M2 is just (J+i). This fine storage phase
therefore takes care of the errors from M1 and since the gate voltage of M2 will not
change much, the errors associated with this transistor are virtually signal independent.
The output current available during phase 2, is given by:
iout = ( J + i + i ) (J + iin + i ) = iin + i ( 2.66 )
Where i is the error component from M1 and i is the error component from M2, which
is just an offset and hence the final output current has no signal dependent error
component unlike the original second generation memory cell. If two cells are put in
series to make a delay cell, the constant offset is cancelled. The cell has second order
settling in its sampling loops.
1a Cg2
Vref 1
M2
1b
2 1a
1 iout
iin
1b
1a
M1 2
Cg1
Figure 2.26 The S2I memory cell and clocking waveforms [20]
The transmission accuracy is derived in [13] as:

iin
istore F J ( 2.67 )
1 + C F
An accuracy improvement of around a magnitude is achieved over the basic second

generation memory cell with transmission accuracies of better than 0.1% [13]. The
second term can be eliminated by using pairs of cells or employing a differential design.
Interestingly the S2I memory cell lends itself to high sampling rates, despite employing
a more complex clocking system with half phases, which might suggest a speed
limitation. The second order cell is shown in Section 2.3.4 to have second order settling
but circuit alterations in order to improve the accuracy (regulated gate cascode for
example) generally make this settling more complex and hence monotonic settling is
difficult to achieve at these high sample rates. In contrast, the S2I cell in its basic form is
capable of achieving high accuracy with no alteration whilst maintaining the more
simple settling behaviour and hence is more suitable for high speed designs. A detailed
analysis in [13] examines the capacitive components present throughout the cell
operation leading to a first cut design strategy for determining transistor dimensions for
a S2I cell prior to simulation.
One disadvantage of the S2I cell is generating its more complex clocking signals but
despite this it seems to be the most favoured where a cell with little signal dependant
clock feedthrough error is required.
2.4.4 Class AB memory cell

Most of the memory cell designs covered so far are class A configurations whereby a
bias current runs through the memory transistor at all times regardless of whether there
is an input signal or not. In 1991 a class AB memory cell was proposed by Battersby
and Toumazou in [21], the main purpose of which was to reduce power consumption.
The circuit is shown in Figure 2.27 and operates as follows. During the first phase, the
transistors M5 and M6 are diode connected and their gate source capacitance charges
until they can sink all of their share of the split input current. During 2 the gates of M5
and M6 are disconnected so they memorise their share of the input current which sums
at the output node forming the output current. The switches at the drain of M2 and M4
ensure that the input current can flow during the output phase.
2 Cg5
1
J M5
1
M1 M2 2 1
iin iout
Vref
M3 M4 1 2 2
1
J
M6
2
Cg5
Figure 2.27 The original class AB memory cell [21]

The bias chain consisting of the transistors M1 and M3 and the two current sources are
simply to bias the gate voltages of transistors M2 and M4 and can be used to bias all the
cells in system so do not need to be replicated for each one. The input current
magnitude is not limited by the bias current but instead the voltage headroom which is
available to the memory transistors.
In [8], simulations show that it is possible, with a bias current of only 25A, to have an
input current of 150A whilst still maintaining correct cell operation. In a class A type
of memory cell this would not have been possible as the input current cannot exceed the
memory transistor bias current. The result is a larger dynamic range and lower power
consumption. Settling errors, mismatch errors and noise errors are all similar to the
equivalent Class A memory cell. The most considerable problem with this design is the
increased distortion levels due to increased charge injection resulting from a greater
modulation of the memory transistors gm by the signal current.
Recently, the class AB cell has generated more interest and techniques employed to
further improve its performance. In [22] a neutralised class AB cell is presented which
uses new techniques to stabilise the bias current and adjust the back-gate voltage on the
PMOS memory transistor. The authors of [22] report a SNR of 70dB and accuracy of
greater than 8bits, but despite being reduced by dummy transistors, the main limitation
is still signal dependant charge injection.
Simple cascodes are used in [23] to improve the transmission errors of the class AB cell
as shown in Figure 2.28. The improvements arise from the cascodes reducing the
voltage variations at the drains of transistors M4 and M2, increasing transmission
accuracy and linearity. Once again, back-gate control and bias current stabilisation are
employed to improve performance. Disadvantages include complicating the settling of
the cell and slightly reduced dynamic range.
Cg4 Vctrl
M4
1
Vb2 1
M3
iin 1 2 iout
1
Vb1 M2
1 2
M1
Cg1
Figure 2.28 Cascoded class AB memory cell [23]

2.5 Summary
This Chapter has detailed the most significant memory cell architectures, the non-ideal
effects they suffer from and how these limitations can be reduced. With such a vast
number of possible arrangements, rather than there being one superior configuration, the
choice of implementation should be based on the given application. The following
briefly summarises the basic cells and techniques used to improve these.
Basic first generation memory cell: main drawbacks include matching problems and
most of all clock feedthrough.
Basic second generation memory cell: significant improvement in matching as only

one transistor is used. Charge injection is still the biggest problem.
Simple cascodes: cascodes are used in both first and second generation cells to improve
the input to output conductance ratio and hence the accuracy. It is necessary to be
careful when designing these cascodes to ensure that the settling response is not
underdamped.
Regulated cascode structure: even greater improvement in the conductance ratio and
hence transmission accuracy. However, use of this technique results in complex settling.
Algorithmic techniques: used to reduce charge injection but generally the area
overhead is not worth the gain, and these often have complex clocking signals.
Dummy switches: used to reduce charge injection and are easy to implement but have
limited effectiveness and clocking becomes critical.
Differential design: clearly involves duplication of the circuitry but will cancel all the
constant charge injection and switching noise. Common mode biasing is difficult.
S2I memory cell: almost completely eliminates the signal dependant charge injection
and is suitable for high frequency. It is a simple design but requires more clock phases.
Class AB memory cell: a lower power results from being able to use a much lower bias
current, which also increases the dynamic range. The biggest problem is charge
injection but with simple cascodes and a few other techniques this can be overcome.
Needs careful design to prevent an underdamped settling response.
Chapter 3
Review of Wave Filters
Before becoming widely accepted and used, SI filters will have to become at least as
good as those realised by Switched Capacitors (SC). The transformation between s and
z plane is best achieved by use of the bilinear transform because the Nyquist limit can
be approached, yielding higher frequency filters. However, bilinear integrators are more
complex than integrators required by other transforms, giving a trade off between
complexity and maximum frequency [8]. SC filters based on high Q integrators are
realisable due to the high gain of the operational amplifiers used to implement them.
Techniques to derive SI filters based on SC filters normally show a lower performance
because current mirrors are less accurate than operational amplifiers.
Wave digital filters emulate the behaviour of passive lossless filters by transforming
passive L and C elements into one-port digital elements defined by an incident signal, a
reflected signal and a port resistance. Adaptors are used to connect these one-port
elements. Wave filters have two intrinsic advantages, they are based on the bilinear
transform, and inherit an insensitivity to component variations enjoyed by the passive
filters from which they are derived [8]. Section 3.1 explains the procedure to realise
wave digital filters, starting from a passive LC network. SI techniques are particularly
suitable for implementation of wave filters, as demonstrated in [8, 24-26] and Section
3.2 explains the reasoning behind this, giving the SI implementation of wave filter
building blocks. Finally, Section 3.3 summarises the Chapters findings.
3.1 Wave filter design procedure

For a full derivation and explanation of wave filter principles, the reader should see
[27], as only the procedure to design wave filters is considered here. Given a particular
clock frequency, it is necessary to prewarp the cut-off frequency according to the
continuous, and discrete, frequency transformation:
2 T
= tan ( 3.1 )
T 2
A passive reference filter is then designed using filter tables [28] and this prewarped
frequency. An example third order passive LC reference filter is shown in Figure 3.1.
Ri L1
+
Vi +
C1 C2 Ro
- v
-
Figure 3.1 A third order LC reference filter
Individual passive components can now be replaced by their wave equivalent, and
connected through three port adaptors. Table 1 summarises the main wave models for
these elements [8]. From the reference filter of Figure 3.1 we replace the parallel
connected C1 with a parallel adaptor and delay element, the series connected L1 with a
series adaptor and negative delay element and the parallel connected C2 with a parallel
adaptor and delay element. The resulting wave filter is shown in Figure 3.2.
z-1 -z-1 z-1
R10 R11 R12

A00 10 11 12 B22
R00 00 20 R20 = R01 01 21 R21 = R02 02 22 R22
B00 A22=0
Figure 3.2 Equivalent wave filter to that in Figure 3.1
The resistances R00 and R22 are imposed by the resistances Ri and Ro in Figure 3.1 and
the port resistances R10, R11 and R12 are imposed by the values given in Table 1 for the
respective component. Given that R20 must equal R01 and likewise R21 must equal R02
we have a degree of freedom which is the choice of one of these, which then sets the
values of the others. Thus:
T 2L T
R00 = Ri R10 = R11 = 1 R12 = R22 = R0 ( 3.2 )
2C1 T 2C 2
Any set of ij values can be used as long as they sum to 2. The following relationships
are therefore used to determine all of the coefficients given a choice for one:
2

i =0
ij =2 ( 3.3 )
0 j 1j 2 j 0 j 1j 2 j
Series: = = parallel: = = ( 3.4 )
R0 j R1 j R2 j G0 j G1 j G2 j
Circuit Element Resistance Wave Model

R A = 2i
i
B=0
A
+
v R
B -
T B = z-1A
i
2C
A
+
v C
B -
2L B = -z-1A
i
T
A
+
v L
B -
R0, R1, R2 2G j
j =
G0 + G1 + G2
B1 A1
R1 AN = 0 A0 + 1 A1 + 2 A2
A0 1 B2
B j = AN A j , j = 0, 1, 2
R0 0 2 R2
B0 A2
R0, R1, R2 2R j
j =
R0 + R1 + R2
B1 A1
R1
AN = A0 + A1 + A2
A0 1 B2
B j = AN j AN , j = 0, 1, 2
R0 0 2 R2
B0 A2
Table 1 Voltage wave models for circuit elements

For fast calculation of the wave coefficients, given specifications for a 3rd order
minimum L ladder filter, the author has created a Graphical Program which calculates
the remaining coefficients given the choice of one.
3.2 SI wave filter building blocks

The basic operations required to implement wave filters are addition, subtraction and
multiplication. This is the reason why a current-mode implementation is particularly
suitable as these can all be easily achieved with current mirrors. Only the simplest SI
delay cells are required to complete the entire SI wave design, required to implement
the z-1 and -z-1 wave models of capacitors and inductors respectively.
Standard circuits, given in [8] are used for the implementation of three port adaptors
with the ij coefficients determining current mirror branch ratios. The simplified circuit
shown in Figure 3.3 is the architecture of a three port series adaptor, which can be
directly related to the wave block diagram give in Table 1. Figure 3.4 is the architecture
of a parallel adaptor.
J J J J J J J J J J 0 J 1 J 2 J
a0 a1 a2
1 : 1 : 1 1 : 1 : 1 1 : 1 : 1 1 : 0 : 1 : 2
J J J J J J
b0 b1 b2
1 : 1 1 : 1 1 : 1
Figure 3.3 Current mode implementation of a 3 port series adaptor

J J 0 J J J 1 J J J 2 J J J J J
a0 a1 a2
1 : 1 : 0 1 : 1 : 0 1 : 1 : 0 1 : 1 : 1 : 1
b2
b1
b0
Figure 3.4 Current mode implementation of a 3 port parallel adaptor
3.3 Summary
We have seen in this Chapter that wave digital filters offer two advantages, the use of
the bilinear transform to convert to digital domain and low sensitivity to component
variations. It was also seen that the arithmetic operations, which are implicit in wave
filter models, are easily implemented with use of only the simplest SI building blocks.
In fact, bearing in mind the advantages of Switched Current techniques, outlined in
Chapter 2, the combination of wave filter design and SI implementation becomes a very
suitable candidate for analog filter core design. Switched Current requires only the most
basic digital process and SI wave building blocks are simple, lending themselves
towards fast, automated, generation.
Chapter 4
Review of Analog Test
Analog test is a demanding area and with no ubiquitous solution yet put forward, the
result is a vast cross-section of opinions, ideas and corresponding test methodologies.
The purpose of this Chapter is twofold, firstly to present the issues and principles
behind analog test and all its different flavours and secondly to detail specific test
methodologies which have been presented in the literature. Therefore, Section 4.1
discusses general analog test issues and the different approaches to solving these, whilst
Sections 4.2, 4.3 and 4.4 detail specific test methodologies given in the literature
categorised into specification testing, defect oriented testing and embedded testing
respectively. Section 4.5 gives a brief consideration of how to tackle SI filter test in the
light of this review.
4.1 Analog Test

4.1.1 Analog test issues
Testing procedures are a vital part of any high quality manufacturing process. Errors in
manufacture can lead to the production of defective units which need to be discarded. It
is speculated that for every manufacturing step towards the sold product, the cost of
detecting and dealing with a fault increases tenfold [29, 30]. In order to minimise costs
it is therefore vital to detect faults at the first possible opportunity and ideally as dies
come off the line we should reject all defective units and accept only those which are
fault free [31].
Despite more and more circuit functions being executed in the digital domain we will
always need analog front and back ends to interface with the purely analog world in
which we live. A bare minimum of analog blocks required to do this are filters and
converters [32]. For the same reasons why we test digital functions we must also test
these analog functions to ensure they meet a specified performance. However, analog
test has not reached the same degree of success as its digital counterpart, this being
mainly due to the difficulty in modelling analog behaviour, the continuous nature of the
signal and the non-linearity of the circuit elements [33]. Unlike digital signals which
allow us to easily classify functionality as working and faulty, analog function is
described by a nominal value with an uncertainty range. It is impossible to generalise
when stating what constitutes acceptable error [34]. For this reason, unlike their digital
counterparts, analog fault models are not well defined or mature with the lack of any
systematic approach often leading to a poor test coverage.
The gaining popularity of System on Chip (SoC) brings yet more challenges to analog
test. In these large mixed signal system chips, the analog parts are hardest to test despite
representing only a very small portion of entire chip, and in fact test cost of mixed-
signal systems is beginning to be dominated by the cost of testing the analog parts [35,
36]. In 1997 the cost to test the analog part of a mixed signal device was as high as 50%
of the total manufacturing cost of chip, and now it is speculated that this figure may be
more like 80% [5]. The analog testing problem is becoming a significant bottleneck and
a major limiter in the time-to-market for mixed signal ICs [37].
One of the biggest problems in developing tests for analog circuits is how to evaluate
their effectiveness. In abstract terms, a test process is judged by its cost and the quality
of the product which passes through the test process [38]. Cost indeed can be a fairly
straightforward metric to calculate but without actually fabricating many runs of the
chip with the test mechanism in place it is difficult to determine its coverage of real life
faults. The yield coverage of a test mechanism, defined as the ratio of the number of
circuits which pass the test to the actual number of fault-free circuits, reflects best its
effectiveness as a test method [39]. Fault coverage, defined at the percentage of (a given
set of) faults which the test method detects, is a metric which can be a good measure of
the effectiveness of a test set [32]. This, however, puts the emphasis on how well the set
of faults reflects those which exist in real life.
A divide exists in the approach towards test generation giving two schools of thought.
The first is known as specification testing and is the tradition approach, which involves
explicitly testing circuits for their functionality or specifications, which at least
guarantees it to meet performance [36]. The second is a defect oriented test approach
(also known as structural testing) which bases the test method around detecting a list of
faults which you define, sometimes leading to a faster more efficient methodology.
4.1.2 Specification testing

Specification testing involves implicitly testing those specifications to which the analog
circuit was designed. This clearly should provide complete confidence in a product
since at least you can guarantee that the performance you state will be met, however,
specification testing leads to very long test times in all but the most simple circuits [40].
To avoid long test times only limited functional tests can be used, but this is now
becoming increasingly unacceptable as they are thought not have direct correlation with
product quality [41].
A better understanding of the failure mechanisms in the circuit under test quickly allows
a vastly improved and more efficient test method as you can target detecting these
effects directly. For these reasons, blindly testing circuit specifications is becoming a
less and less popular approach as more innovative methods with higher efficiency take
over. Clearly in terms of embedded test, it would also be more complex to generate test
signals and analyse responses on chip for a complete set of specifications.
4.1.3 Fault classification

Moving towards a better understanding of failure mechanisms of circuits requires
understanding of faults types. A great deal of confusion as to fault classification can
result from reading publications, which will hopefully be cleared up here. We can
broadly divide failure mechanisms into those which are caused by spot defects and
those which are caused by process variations. Spot defects result from a small amount
of debris or dust getting onto a wafer with typical density being about 1-2 defects/cm2
[35]. Spot defects can be categorised as either catastrophic or parametric. A catastrophic
fault is one where the component is destroyed or uncontrollable but in any case is
affected by the fault to the degree that the circuit function is significantly altered.
Parametric failure is where a component appears to behave as it should but may not be
within desired tolerance limits. Parametric faults can subtly alter the circuit
performance, to an extent that is difficult to detect and the pass-fail decision becomes
truly down to tolerance on the specifications given. Process variations are generally the
result of equipment variations in alignment and performance, leading to an uneven layer
deposition across the surface of the wafer [42]. These invariably lead to parametric type
variations in circuit behaviour.
Catastrophic defects can be modelled as short and open connections between device
terminals, giving a simple method by which to generate fault lists. Despite many testing
methodologies measuring test coverage based only on catastrophic defects, this is
becoming a less and less credible technique. Many now feel that catastrophic defects
along do not accurately represent faults in a modern process and hence catastrophic
fault coverage is insufficient in quantifying the quality of a test set for analog circuits
[32]. Interestingly, effects of parametric faults could be completely eliminated by
statistical design for manufacturability, in which case only catastrophic faults would
need to be considered. However, designers say that it is neither desirable or feasible to
eliminate all parametric faults by statistical design, hence must test for them [43].
In the case of parametric faults, there is no clear cut decision as to the integrity of the
circuit as subtle performance variations may come very close to the border between
what is acceptable and what is not. Clearly to make this pass/fail decision one needs to
relate to the circuit specifications and determine the parameter limits which would cause
the circuit to fail one or more of these. Now this does border on specification testing,
but it is important to make the distinction that we are not blindly testing specifications
but instead determining whether the circuit fails specs coinciding with a parameter
tolerance and hence allowing us to look at the latter to determine the former. Some
simply use a general accuracy figure as an acceptable tolerance on individual
parameters, for example 5% [41] and assume that anything more than this should be
considered a fault. However, we really need to link back to the specifications to
determine this limit, which will be different for each parameter. Most parametric fault
modelling is done by changing the parameter of a component out of its tolerance
window, using Monte Carlo simulation for example, and seeing if the test method will
catch the change. By evaluating coverage using parametric faults, we are more or less
guaranteed to cover the entire set of catastrophic faults [32, 37].
4.1.4 Defect oriented testing

Knowledge of failure mechanisms has allowed a more defect oriented approach to be
taken to testing (DOT), which exploits the specific structural differences between a
working and faulty circuit so as to derive a more efficient and innovative testing
method. Most of these approaches assume a fault list and then optimise the tests to
detect all of these [40]. Industry wants a fault model and test methodology that serves
the same purpose as those in digital test techniques, which would at least allow easier
benchmarking of the new systems [33]. This is where the controversy arises: what is the
fault model? The stuck at fault model of the digital world has long been accepted but in
analog no such model exists and much of the time we can only speculate, with many
contrasting opinions. Despite most thinking that parametric faults should be considered,
publications from industry suggest otherwise. One publication [44] based on an
industrial case study concluded that spot defects are the dominant yield limiter in a
mature process in high volume production with bridging defects (catastrophic in nature)
appearing as one of the most common defects [44]. It is generally agreed that relatively
simple tests can give high fault coverage for catastrophic defects with only simple DC
tests needed to detect them [40, 44], so why make more complex tests aimed at
parametric faults? Of course there are as many papers which would dispute this opinion,
for example [45] which concludes that transistor level faults do not lead to accurate and
realistic results for mixed signal fault simulations
A slightly more recent approach to solve the fault list problem in DOT is to use
Inductive Fault Analysis (IFA). IFA methods take physical layout and process
information along with the statistical distribution of defects on the wafer (from the fab)
and then extracts realistic faults [46]. Using software, random layer spots are created
just like they might be in the actual manufacturing process, which should lead to the
most realistic fault list [47]. The DOT methodology using IFA then becomes three
steps, fault extraction from the layout, transistor level fault simulation and test
generation [44].
4.1.5 Embedded test and BIST

Built-In Self-Test (BIST), now increasingly becoming known as Embedded test
involves incorporating circuitry onto the chip itself to test the circuit function. There are
both advantages and shortcomings for this kind of approach. Since signals do not have
to be routed off the chip then there is little distortion [32, 48] and fundamentally,
embedded test significantly reduces the test equipment and test time [49]. With large
system chips becoming the norm, test time and routing issues are becoming greater and
so embedded test is probably the most efficient way to overcome the existing problems.
So, to what extent should an embedded test solution test the circuit? Verifying a
complete set of specifications would provide complete confidence in the part, but would
be very costly in terms of area and performance impact. This leads to a compromise in
embedded analog test with circuits being tested to a lesser degree that they would be by
an off-chip tester [50]. This poses the question of whether embedded analog testing
should be used or not, for which there are some very strong opinions. Those who do not
advocate embedded test will be quick to ask what tests the testing circuitry which is an
important consideration, especially given that global process variations may cause the
test circuitry to track the CUT, passing faulty circuits [32].
4.1.6 System Test

Advances in IC design have led to entire systems being implemented on a single chip,
with these System on Chips (SoCs) very often containing both analog and digital
blocks, hence representing a truly mixed signal environment [51]. SoC is quickly
becoming more popular as re-usable cores speed up the design cycle. Analog cores are
becoming traded now just like their digital counterparts and the issue of testing again
raises its head.
Core testing is best done at a system level with the core designer preparing their
products with the correct embedded test facilities and supplying the core user, or system
integrator with suitable test patterns or instructions [52]. It is especially important that
the provider supplies the tests with the core as the user will have no knowledge of the
core themselves, that knowledge often being protected intellectual property (IP) [51].
To cope with the demands of system test the P1500 standard was proposed, mainly with
digital SoCs in mind. In order to transport test signals around a chip a thin shell around
each core, called a wrapper, is used. The wrapper has three main modes of operation:
functional operation, where the wrapper is transparent; inward facing, where the
wrapper provides test access to the core itself; and outward facing, where the wrapper
provides test access to the circuitry outside the core [51]. Despite not being targeted
towards analog cores, the architecture could be used in its minimal form to initiate the
test procedure and to route the test result to an appropriate output.
Two levels of compliance are given for P1500, an unwrapped core and wrapped core.
An unwrapped core does not have a P1500 wrapper but does have information about the
test in a standard language on the basis that the core will be wrapped by the user at a
later stage. A wrapped core includes the P1500 wrapper [51]. There is potential for
catalogues of wrapped cores from providers which allow the user to select which core
best covers his needs without having to worry about system test [51]. Prime targets for
use of the P1500 standard are black box third party cores where the implementation of
the core is hidden from the core user [51].
4.2 Specification test techniques

The following is a categorisation of many of the specification based testing techniques
presented in the literature, along with a brief description of the methodologies:
Linking parameters to specifications: This serves the purpose by which to bridge the
gap between blindly testing for specifications and taking a defect oriented approach.
Every specification implicitly imposed bounds on individual parametric deviations. For
example in [37] the authors assume a set of specifications with acceptable ranges and
they then take circuit parameters and compute the minimum deviation in the value
which will violate one of the specifications. One can then simply test those parameters,
which would be quicker then testing all the specifications themselves.
Minimal test set algorithms: In [53] an algorithm was presented which determines
which specs have to be tested in order to have a minimal test set with 100% coverage.
The authors concluded that it is best to perform short tests which are likely to be failed
first. The output of the presented algorithm gives a list of specifications in order of
importance with the cumulative fault coverage allowing the test set designer to choose a
set of tests to give a desired level of coverage.
Optimal test waveform generation: In [40] a specification driven technique is given in

which an optimum Piece-Wise Linear waveform is derived. A cost function is used,
which is a measure of the sensitivity gained using a specific test to a particular fault,
having linked that fault to the specifications. The authors used a high-level simulator,
called SABER to speed up the simulation time required to derive the waveform. In [54]
the same authors test for one fault at a range of frequencies and find which produces the
most sensitive test. This gives them a set of frequencies which is used to create a
optimum waveform for testing all the faults. Sensitivity is defined as the ratio of the
fractional change in the circuit output to the fractional change in a given parameter.
Pole position analysis: The authors of [50] use nodal analysis to find a circuits transfer
function then mathematical software to derive an S domain transfer function. They then
test for a shift in pole positions which checks for a change in the gain or phase. The test
waveforms used are steps and ramps which they say are a natural way of compressing a
number of sinusoidal frequencies.
Measurement space: A number of papers make use of a measurement space to map

specifications onto. This space can then be separated into regions which are acceptable
and regions where the specifications are violated hence simplifying the testing problem
[43]. The authors in [55] use a similar technique, deriving a table showing circuit
parameters along with a low and high limit for each with respect to each different
specifications. From this it is easy to see which specification constrains the parameter
most, allowing a minimum set of specifications to be tested.
4.3 Defect oriented test techniques

Many defect oriented testing methodologies have been presented in the literature, which
are catalogued below with a brief description of each:
Test dropping: Based on a given fault list, the authors of [44] run different tests
evaluating their ability to detect these faults, then choosing the smallest number of tests
which give the desired coverage. In [33] the authors call their technique parallel fault
detection as a way of saying that each test detects a number of faults at any one time.
They define one fault dominating another as meaning that the test for one also detects
the other in which case you can drop the test for the second.
Supply current spectrum: Supply current is normally measured as a quiescent Iddq but
in [56] the spectrum of power supply current is used as the decision criterion. With a
given input signal, the power supply spectrum can indicate faults within the circuit.
Digital transformation: An attempt to reduce the analog testing problem to a digital one
can be seen in [57] when the circuit is transformed into a digital equivalent and then
only stuck at faults which could possibly capture parametric faults in the original circuit
are targeted.
Lissajous With a sinusoidal input, the lissajous (xy sweep) of internal nodes can give a
means to determine faulty behaviour. The procedure involves deriving a control line
which is based on a number of constants, then counting how many times the lissajous
crosses the control line in a certain amount of time. The authors use sensitivity analysis
to determine the best signature, and IFA to find the fault list [48].
Multifrequency analysis: A fault is easy to detect if it greatly changes the circuit

output. With this in mind, the authors of [58] find the frequencies which make faults
most detectable, deriving test vectors of frequencies which could then be compacted.
The test signal therefore contains a number of frequency components.
Inductive Fault Analysis tools: Inductive fault analysis considers layout and process
specific fault statistics and based on these, places a scattering of faults on the design
layout allowing a realistic fault list to be derived. IFA can therefore be used for yield
prediction and test optimisation. VLASIC, LIFT and EDAM [46], CARAFE, [59] and
GDSFaultSim, [60], are examples of these IFA tools, and mainly model catastrophic
types of faults only. The authors of [61] consider their methodology as an extension of
IFA, basing the strategy on the sensitivity of the parameters and characteristics of an
analog circuit to the disturbances of the manufacturing process. The only problems of
an IFA approach are that it requires foundry statistics which are difficult to get hold of
and the test method can only be considered at the layout stage of the design flow [46].
4.4 Embedded test techniques

Many different embedded test techniques and BIST circuits have been proposed in the
literature and the following is a summary of these, with a brief description of each:
Iddq supply current techniques: The supply current to a circuit is measured and
information gained from that is used to determine whether it is faulty or working.
Emerging deep sub-micron technologies and low voltage environment seriously
undermines the feasibility of the conventional Iddq test strategies due to supply decrease.
For this reason other variations have been presented, for example in [62] an Iddq
method is proposed which determines the difference in maximum and minimum power
supply current readings within a test period, These readings are then compared to
reference readings. Another method in [63] involves varying supply voltage whilst
monitoring supply current. All Iddq techniques involve measuring the voltage across a
sensing element which is normally a very small resistor between the circuit and power
supply. The resistor has to be small enough so that it does not affect the performance of
the circuit beneath it and a result of this is that the voltage across it also very small. This
voltage must therefore be amplified by a suitable current sensor such as that in [62, 64,
65].
Mixed Analog Digital Built-In Self-Test, MADBIST: If a DAC and an ADC is present
on the same chip as the circuit you wish to test, these can be used to generate test
signals and digital outputs. For example, a digital signal can be generated by a DSP, or
passed onto chip through digital automated test equipment (ATE), then fed into the
DAC which outputs the circuit test signal. A circuit response to this test signal is
digitised by the ADC and analysed either off chip or on chip by digital processing [29,
35, 42, 66].
Using M-sequences to generate test signals: It was demonstrated in [67] that by

applying a periodic noise signal (M sequence) to a system you can determine the
impulse response. This involves correlating the circuit output to the delay of the M
sequence, then repeating this but with the sequence shifted by 2, 3, 4 T up to nT to give
the impulse response. The impulse response can be examined at certain points and
decisions made as to whether the circuit is working or faulty. M sequences were applied
as an embedded test solution in an engine knock detector circuit in [68] and Switched
Capacitor filters in [69]. An interesting extension in [17] used a current mirror on the
supply to the op amp instead of the circuit output to find the impulse response.
Generally, however, despite it being relatively easy to achieve the periodic noise signal
with standard digital techniques, it is difficult to analyse the impulse response on-chip.
Simple DC tests: DC BIST costs a small fraction of AC BIST while it can provide high
fault coverage. The authors of [70] assume catastrophic and parametric faults and use an
analog multiplexer to send a number of DC values to the circuit under test, basing the
test decision on the value of the circuit output for each of these.
Window comparators: To determine the steady state level of particular nodes inside a
circuit structure, on-chip window comparators can be used. These are very simple to
implement as they can be made from inverters with custom designed switching points.
Loading on the tested nodes is very low as they are only connected to a transistors gate.
It was shown in [71] that standard NAND gate library parts can be used to make these
window detectors if a number of these are configured correctly, as each of them have an
inherent non-symmetrical switching point. This allows window detectors to be made
without have to design custom library parts.
Oscillation based test: Considerable research has been lead into the oscillation test
principle which involves converting the CUT to a system which oscillates then
evaluating the oscillation frequency. The oscillation can be considered as digital and so
is easy to determine and it is shown that faults in the circuit tend to affect this
frequency. Monte Carlo simulation can be used to find out how the frequency changes
with component deviations and this knowledge used to base the limits for the working
frequency [49, 72]. More recently, and in keeping with current trends, more of an effort
has been made to link parameters of the oscillation, not just the frequency, back to the
specifications [73].
Current-mode approach: By comparing the current consumed by a circuit with the sum
of currents converted from the voltage levels of the circuit, the authors of [74] were
able to detect a fault as a difference between the two. Operational transconductance
amplifiers (OTAs) with a second output stage allowed easy extraction of the test
currents.
Reconfiguration based test: Given that the major limitation of embedded test
techniques is the active area the implementation consumes, many have looked into how
existing parts of the circuit can be re-configured to generate analog test patterns and
analyse responses. Reconfiguring of Biquad filter sections seems popular as these can
easily be altered into oscillators and integrators [75]. In [76] a biquad is reconfigured to
an oscillator to test a second biquad, with a third configured as an integrator. The test
decision in this case was based on how long it took for the integral of the output signal
to reach a certain level.
Analog scan path: An attempt was made in [77] as to mimic the way most digital
circuit are tested, with a scan path technique. Voltage levels can be scanned along
sample hold cells and the values evaluated as they arrive as the scan out (SO) pin at the
end of the chain. A scan in (SI) pin is provided for testing of the BIST structure. A
current-mode variation of the scan path technique was used in [78] where the voltage
levels were taken from the circuit under test, buffered, then loaded onto simple
sample/hold OTA-C stages. The levels were then passed from stage to stage as currents.
The authors of [78] concluded that analog scan is best with the current mode approach.
Complete integrated test core: A complete testing core for use in a system chip was
presented in [79] and fulfilled the tasks normally undertaken by an off chip analog
tester. An arbitrary waveform generator and a waveform digitiser are at the heart of the
technique with the former using a short repetitive sequence of digital bits to create a test
signal. The waveform digitiser uses a reference voltage and a comparator to detect
whether a level is crossed by the output signal, and by synchronising changes in the
reference level with the period of the input signal allows a digital representation of the
output signal to be built up. The design was successfully fabricated in a 0.35um CMOS
process and shown to be capable to test a number of parameters on a number of circuit
types.
Time domain tests: Time domain response analysis was used in [80] to test for faults by
checking output levels at various times after an initial impulse and comparing them with
working reference signals. For example, timers start and stop when the output signal
gets to 90% and 10% respectively, giving the fall time. The delay can also be measured
in this way and these values can then be checked with reference values held in memory
to determine a correct or faulty CUT.
Ramp based tests: An interesting technique in [81] uses a sine wave input to the CUT
and then a comparator to compare the output to a ramp waveform. The crossing points
give a digital signature which can be compared to values held in memory to determine a
good or faulty circuit.
4.5 Summary
Having reviewed the vast array of approaches and methodologies for analog testing, it is
now appropriate to draw some conclusions as to what issues should be considered when
later embarking on the embedded test phase of this project. The very few publications in
the literature specifically addressing SI test are geared only towards the test of memory
cells, with the approach normally involving reconfiguration of the cell to compare the
input and stored current [31, 82]. Our SI wave filter design, detailed in Chapter 3, uses
only memory cells for the delay blocks with all the adaptors being implemented with
current mirrors. For this reason the SI test approaches in [31, 82] would only test a
fraction of our wave filters and so we would need a more comprehensive methodology.
The most considerable limitation in embedded test is the constraint on test circuitry size.
It is simply not possible to test an analog circuit to the degree achieved by an off chip
tester using only simple built-in test circuitry. Embedded test techniques should
therefore simply share some of the burden of testing the chip, at least to the extent that
the test signals can be passed to and from the analog core as digital signatures, which
can then be handled by SoC test integration standards such as P1500.
In the context of embedded test it is not efficient to blindly test specifications, and one
will always benefit from understanding of the circuit failure mechanisms at bay.
However, it has become clear that if you choose to verify your test coverage through a
fault list, efforts should be made to ensure this list is as realistic as possible, for example
by deriving it using IFA techniques. It seems very popular at the moment to link
measured parameters back to specifications such that coverage can be stated in terms of
a fault list and also in terms of meeting key performances.
Chapter 5
Review of Analog Layout CAD Tools
Whereas digital IP cores are often traded as high-level descriptions, which can later be
implemented by the core user in any technology, analog cores are normally supplied as
verified physical layouts. An integral part of an analog core development CAD tool
would therefore be the capability to generate a verified core layout as part of the design
flow. Initially, given the difficulty of this task, this project will only consider the
generation of an analog core to its circuit description, allowing verification of its
operation by simulation. However, depending on the progress of the project, automated
layout may well be considered at a later stage and this Chapter therefore presents a
review of this area.
Despite the nature of analog design making automation difficult, a number of analog
layout CAD tools have been presented in the literature. There are typically two
approaches to these tools, the first being a generic technique which ultimately lays out
every transistor of the design, and the second a reuse based technique which uses pre-
designed parameterised cells, tailoring these to achieve given specifications or
constraints. A survey of generic and reuse based methods is given in Section 5.1 and
Section 5.2 respectively. In consideration of this survey, Section 5.3 concludes by
suggesting the appropriate technique for eventual use in this project.
5.1 Generic techniques

ALSYN: Proposed in [83], in 1993, ALSYN is an analog layout synthesis tool which is
capable of generating analog layouts from a netlist description. This is achieved in
seven steps, which include partitioning the netlist into sub-blocks, floorplanning,
placement and routing. Area is minimised, as is net length during several of the stages.
The authors developed their own language to describe the modules, and the underlying
code is written in C. The system can be used with any technology with the process
technology file being one of the system inputs.
ALAS!: Published in [84], in 1996, this analog layout assistant automatically

generates common-centroid structures, interdigitised device pairs and passive
components. The original purpose of the tool was to speed up the drawing of these
structures, which are essential for matching but complicated and time consuming to
manually lay out. Written in C, the program simply provides a helping hand for
designers, rather than a complete CAD tool. Despite comments in [85], that ALAS! did
not create true common-centroid transistor arrays, it was later shown that this was not
the case. Dummy polysilicon is used to prevent undercut at the edge of a group of
matched devices.
FLAG: A innovative approach was taken in [86], in 1996, for the layout of analog MOS
transistors. FLAG (Flexible Layout Generator for Analog MOS Transistors) uses small
elementary parts, called bricks, which are placed side by side in a user specific
boundary. For each technology, three bricks are designed to specifically conform to the
design rules, and the brick design is such that subsequent placement of these, side by
side, ensures the design rules are always met. The drawbacks are that the system is only
capable of designing single transistors, and not interdigitised and common centroid
structures. In addition to this, increased parasitics resulting from the brick concept deem
the generated layouts unsuitable for high-speed operation.
Retargeting of GDSII layouts: Specifically aimed at retargeting designs from one

process to another, the author of [87], published in 1997, developed a system which
represents all components as objects, not polygons. A layout description can then be
taken to a higher level of abstraction, allowing technology independence. The author
demonstrated his ideas by processing a GDSII layout and recognising the objects within
it leading to a representation at a more abstract level. This high-level representation
could then be transposed to a different technology. It turned out that the main
contribution was the ability to repair, partition and recognise complex all-angle wires
efficiently, with a recognition capability of almost 100%.
Analog Circuit Stack Generator: In [88], published in 1999, the authors use matching
requirements as the primary constraint on the analog layout, arguing that since absolute
matching between transistors can be as bad as 20% and parametric matching may be to
within 0.1% most circuit implementations rely on matching for their performance. The
system creates a layout for matched transistors as a stack of interdigitised structures
after fragmenting the circuit representation until these base structures are reached.
Interconnect structure parasitic considerations are included in the performance and
optimization process.
Estimated layout parasitics: The authors of [89], published in 2000, argue that during
automated analog synthesis, the iterations necessary when the layout parasitics are first
generated waste design time. Their approach involves estimation and compensations of
parasitics during circuit sizing and so eliminating these lengthy iterations. Circuits are
laid out with consideration to matching, reliability and shape, with parasitics calculated
using a predefined model at an early stage. Using a symbolic layout approach allows the
layout tool to be technology independent, and the system is demonstrated by the design
of a simple OTA.
Cell based with genetic algorithm: A good application of a genetic algorithm in the
context of automated analog design can be found in [90], published in 2002. The
authors use a fixed cell structure consisting of four transistors in series, with inputs at
each gate, and outputs at each node along with switches between each of the four
transistors respective drain and source. By configuring the switches in the single cell
and using only certain inputs and outputs, many simple circuit structures can be
realised. Using a matrix of cells, the outputs can be connected to any other outputs or
inputs, achieving voltage or current transfer between them. A genetic algorithm is used
iteratively to find the best possible configuration of cell switches and inter-cell
connections to achieve a given function, for example squaring. After many iterations of
the algorithm, most functions can be accurately implemented to within a few percent.
5.2 Reuse techniques

ILAC and IDAC: Proposed in [91], in 1989, IDAC (Interactive Design for Analog
CMOS Circuits) is a tool which sizes analog CMOS circuits from a library of proven
schematics, given a set of specifications and technology parameters. The output of
IDAC is a data sheet for the cell, SPICE files and a layout description file. The layout
file then used by ILAC, (Interactive Layout of Analog CMOS Circuits) which generates
the geometric layout for the cells based on user information such as cell height and
position of pins. ILAC is capable of handling typical layout constraints such as device
matching and symmetry. ILAC employs an initial floorplanning stage, evaluating a cost
function to determine the best block arrangement, followed by place and route of these.
Generic layers are used initially, which are later mapped to specific process layers using
boolean operations, giving technology independence. The results are normally 25%
larger than hand drawn layout, but are created in significantly less time, presenting a
trade-off between area and design speed. The program was written in Pascal.
SCADS: This work, published in [9] in 1996, was aimed specifically at SI filters. Based
on integrators, the filters use balanced S2I memory cells so as to achieve high accuracy.
Basic cells are given which parameterised during the design flow. The system is built
into an existing commercial design suite which is probably Cadence, using the SKILL
language. The flow is of a push button type, which involves entering specifications,
with the system iterating several times to achieve these, finally deriving transistor
dimensions. Clock sources are found from standard libraries with the lines loaded to
restore the exact timing relationships. By creating first a design, for given models, the
system is not dependant on technology until the point of layout when which any process
can be used as long as the library of cell templates exists for it. After layout, parasitics
may be extracted and further iterations made if necessary. Filters with excellent
precision and performance can be synthesised within a day, and a number of examples
have been fabricated.
Retargeting of Mixed-Signal blocks: Presented in 2001, [92] this paper introduces the
concepts needed to retarget mixed-signal blocks for use in SoCs [92]. Parameterised
layout templates should be used at different hierarchical levels along with accurate
behavioural modelling in order to tune sized circuits to new sets of specifications and
for different technologies. Rather than create a complex general analog CAD tool which
builds the layout from individual transistors, retargetable cell libraries should be created
consisting of well proven layout templates for functional building blocks, which can be
tuned by appropriate sizing. The objective of this kind of reusability is not to obtain
optimum designs but instead to reduce time to market with a design which meets the
required specifications. Behavioural models are needed to describe the circuit function
whilst being independent of architecture such that they can reduce the time in the
iterative cycles of optimization and verification.
Cell design and retargeting tool: Firmly from industry and published in 2001, [93]
describes a SKILL based retargeting and design tool which is used for creating IP
blocks by retargeting existing designs to different technologies and foundries.
Technology independence is achieved by the definition of a minimum set of generic
DRC parameters capable of describing the different layer constraints imposed by a large
number of different technologies. The authors have used SKILL within the Cadence
framework and the entire principle is based around the use of pCells. From basic pCells
of single devices, larger sub-block pCells are built, from which the so-called ultra-
pCells can be finally derived. The result is a design which is entirely described by a
number of parameters, 73 in the example given, and these control the dimensions of
every transistor in the layout. Defining the layout in a generic technology allows
mapping of this to a specific technology when required. A second technique called a
layout direct retargeting tool (LDRT) has been developed by the authors to process an
existing database, which does not need initial preparation, to create a new database
compliant with a different set of DRC rules.
Circuit specific design reuse: A case study given in [94], 2001, presents the design of a
modulator with emphasis on eventual design reuse. Behavioural models are used to
map performance specifications to lower levels, with consideration of non-ideal effects.
This is an example of a block-specific synthesis tool, which simply designs a working
circuit with the modification of parameters in mind, in a hierarchical top down
approach. Parasitics are accounted for during the design phase so as to avoid long layout
iteration times. Examples are given for two technologies.
Technology-portable flexible analog blocks: Presented in 2002, [95] describes a

complete methodology for retargeting analog blocks to different specifications and
processes or foundries and realises the concepts given in [92]. This again is clearly
aimed at fast analog IP creation, making extensive use of pCells in Cadence being
entirely written in SKILL. To design a cell, technology portable layout templates are
first needed, capable of being tuned with design constraints. Specifications and design
goals are the inputs to the system and are used to derive the parameters in the pCell
definitions. The templates are stretched, repeated and parameters passed down and
inherited in a hierarchical scheme in order to generate the SKILL code defining the
designed cell. Retargeting from one technology to another is the most challenging issue
in the system design as it can cause problems such as layer conflicts, off-grid problems,
design rule violations and altered process parameters. These problems were tackled by
using a generic design rule database which can be mapped onto a range of specific
technologies. Overheads involved in setting up the database each time a new circuit
needs to be added are offset by the ease at which new specifications can be met and the
ability to retarget.
5.3 Summary
This Chapter has shown how automated layout CAD tools, presented in the literature,
vary from highly complex systems capable of generating layouts from an arbitrary
netlist, to those which are based on stretching and placing pre-designed parameterised
cells. The second method, based on reuse of pre-verified blocks, would seem most
appropriate for use in the context of this project. This approach is not only is much
simpler to implement (although still challenging in itself) but also by using pre-verified,
well-designed layouts, we can ensure that these are optimised in terms of performance
and area. It is worth mentioning again that incorporation of automated layout as part of
the system flow will depend on the progress of the project in its later stages.
Chapter 6
Preliminary Results
This Chapter details the work achieved to date towards the project goals which were
defined in Chapter 1, primarily the development of a SI wave filter. Considerations as to
the choice of technology and the design kit setup in Cadence is described in Section 6.1.
The reasons for adopting a hierarchical circuit design approach, despite this initially
being more time consuming, are discussed in Section 6.2. Low-level blocks of this
hierarchical system are detailed in Section 6.3, with higher level blocks being given in
Section 6.4. Simulation results are given to demonstrate a working filter in Section 6.5,
and finally Section 6.6 summarises the findings and problems encountered so far.
6.1 Choice of technology

Cadence Design Framework II has been used exclusively for all the circuit and system
development used in this project. Academic institutions in the EU can fabricate low
numbers of prototype chips at low cost through Europractice [96], a European Union
initiative which provides a co-operative service for IC manufacture by placing many
projects on the same wafer. Europractice facilitate fabrication in numerous
technologies, from 2 to 0.13 and from many different foundries.
Once any significant design work has been undertaken, it becomes increasingly difficult
to migrate to different technologies and so is important to carefully consider which to
use before development commences. The main benefit of Switched Current is its ability
to function on a standard digital process, and with this in mind it would have been
inappropriate to use a dedicated analog technology. Fabrication cost is clearly also a
factor, which generally increases with smaller technologies. Fabricating on a modern,
deep-submicron process would give valuable experience in the design issues involved
but would simply be too costly. With these considerations in mind, an inexpensive 0.5
Alcatel digital process was chosen. A design kit is required for any chosen technology,
which sets up the Cadence environment. Installing the design kit for the Alcatel 0.5
process was tedious and a full design flow with a basic inverter circuit pointed to many
bugs in the system. These were eventually solved with numerous fixes from the design
kit developers.
6.2 Hierarchical cell design

Instead of designing a highly complex, flat schematic for an entire system, a
hierarchical approach can be taken, significantly improving redesign times. Given the
goals of the project, it was decided to invest time at the onset to create a hierarchical
system such that global low-level changes could be easily made, and new circuits could
be easily created at a block level. The majority of work to date has simply involved the
design of a library of cells, ranging from transistor level current mirrors to a high-level
third order filter block, the aim not being to achieve high overall performance but to get
a working hierarchical cell structure in place. The majority of simulations have used
only simple first generation memory cells and current mirrors, both based on the high
compliance cascoded current mirror. The following Sections describe individual blocks
and how parameter input and passing has been used to enable the creation of a high-
level third order wave filter cell based on adaptors and delay cells, similar to that shown
in Figure 3.2.
6.3 Low-level blocks

6.3.1 Current mirrors
As described in Chapter 3, the basis of series and parallel adaptors are current mirrors.
As part of the hierarchy, generic current mirror symbolic cells were created for single,
double and triple branch current mirrors beneath which the specific current mirror
architecture could be hidden. Parameters are defined in the current mirror symbol
properties which are passed into the circuit architecture beneath and serve to multiply
device widths on the relevant branch. The symbols are shown in Figure 6.1. For
example, the current mirror CM3 has three parameters defined in its properties, defining
the branch ratio multipliers named Brat1, Brat2 and Brat3. In addition to these
property defined parameters, Cadence design variables are defined in the architecture
beneath the symbol, such that these can be globally controlled at a higher level.
Examples include the dimensions of current source transistors and cascode devices.
Figure 6.1 Current mirror symbols hiding low lever implementation

6.3.2 Delay cells

The choice of memory cell architecture will be key to the performance of the final
system, and once again to allow this to be easily changed for an entire design, the
specific realisation is hidden beneath a generic memory cell symbol, shown in Figure
6.2. Different symbols are made so as to refer to the specific architecture they are hiding
beneath, and keeping the in/out ports in the same place allows alternative memory cell
architectures to be easily swapped in and out of large designs. Design variables are
again used such that device dimensions of the transistor level implementation of the
symbol can be altered globally at any level above.
Figure 6.2 Generic full period memory cell symbol
6.3.3 Clock generation

A symbol with a master frequency input has been created which represents the clocking
circuit for a particular memory cell. Clock waveforms are required for the switches in
every memory cell, and global net names have been used to great effect here, so that no
physical schematic connections have to be made between the clock generation block
and the memory cells in a large design. Different memory cells require different
clocking signals and it is expected that for every memory cell architecture an
accompanying clock generation block will be created. The symbol shown in Figure 6.3
along with its gate level circuit [97] is the non overlapping clock generation circuit
required for a first generation memory cell.
Figure 6.3 Clock generation symbol for first genertaion memory cell and gate level circuit
6.3.4 Bias circuit

It is assumed that gate bias voltages for the PMOS current sources in both the current
mirrors and memory cells will come from a common bias voltage generation circuit.
The bias arrangement will change for different architectures and as such a symbol and
accompanying bias circuitry is required for each arrangement. A defined property
parameter called Ibias sets the current (J) used to derive these gate bias voltage
levels, meaning that to change the bias current of the mirrors and memory cells of an
entire design simply requires setting this property. In the case when high compliance
current mirrors and memory cells are employed, Figure 6.4 shows the bias block with
accompanying transistor implementation. Global net names are used again to allow
other blocks to inherit these values without explicit schematic connection.
Figure 6.4 Biasing block symbol and implementation in the case of a high compliance architecture.
6.4 Higher level blocks

6.4.1 Adaptors
The design of higher level blocks now becomes much easier given the careful
implementation of low-level symbols just described and the ability in Cadence to pass
high-level properties down the hierarchy by the use of pPar(). Considering the design
of current-mode wave adaptors in Section 3.2 we can produce series and parallel
adaptors from the current mirror cell symbols just given in Section 6.3.1. Where the
branch ratios are specified as 1 in Figure 3.3 and Figure 3.4, this has been explicitly
set in the current mirror symbol properties, and where the branch ratios are the
corresponding coefficient of the wave model this is treated as a parameter which will
be passed down from the level above and, for example, pPar(Y01) is used in these
property fields.
Figure 6.5 Series and parallel adaptor blocks and their implementation
6.4.2 Delay cells

Both negative and positive delay cell blocks are also necessary to realise functioning
wave filters, and these are in fact just a full period memory cell, with a current mirror in
the case of a negative delay cell (Brat1 parameter set to 1). Shown in Figure 6.6 are
the block symbols for the delay and negative delay cell, along with their implementation
in terms of full period memory cells and current mirror.
Figure 6.6 Block symbols of a delay and negative delay and their implementation
6.4.3 Wave filter

Having created all the components for making wave filters, all that remains is to
construct this symbol. At this point the filter design becomes specific in terms of the
structure of adaptors and delay cells. For example the third order wave filter given in
Figure 3.2 is created for simulation by placing and connecting the relevant adaptors,
delay cells and not forgetting to place the correct bias block and clock generation block,
all being from the library just described. Figure 6.7 shows this circuit, from which a
symbol representing this wave filter can be generated, passing once again property
values from this symbol down the levels.
Figure 6.7 Example third order filter symbol and implementation
In this example, the transistor architecture beneath the current mirror symbols is of high
compliance cascode type and the memory cells are first generation, based on the same
high compliance cascode structure. As mentioned before, device dimensions are defined
at the transistor level as design variables. The SI wave filter design is therefore entirely
described by these design variables, which Cadence keeps track of, and the values given
in the property form of the filter block, the relevant part being shown in Figure 6.8.
Examples of design variables are PmosW, which is the width of the current source
transistor and NmosLc, the length of the memory transistors cascode device.
Figure 6.8 Property form for the third order wave filter cell
6.5 Simulation results

It is not my intention to present all simulations to date as I am not yet at a stage where I
feel the performances achieved warrant this. Instead, I shall briefly illustrate charge
injection problems in a first generation delay cell and then give an example filter
response and review this critically.
6.5.1 Charge injection problems in a delay cell

The full period delay cell, shown in Figure 6.9, was designed, based on the first
generation memory cell and a high compliance cascode structure. The circuit was
simulated with a bias current of 100A, a sinusoidal input signal of amplitude 50A
and frequency 1kHz and a sample frequency of 20kHz.
1
Iin Iout
1 2
Figure 6.9 Example first generation delay cell
CFT from S1
CFT from S2
almost cancels
1 2 CFT from S1
Figure 6.10 Transient response of the first generation delay cell in Figure 6.9
The transient response showing input current and output current is shown in Figure 6.10
and demonstrates the function of the delay cell, with a sampled output representing the
input a full period before. Because the two memory cells are cascaded after one another,
most of the clock feedthrough is in fact cancelled as it acts in opposite respects in each
memory cell. As shown in Figure 6.10 the first half of the sampled output corresponds
to the input current to that stage, less the inaccuracy due to the charge injection from the
first switch and hence the level is lower than it should be. As the second switch is
turned off to memorise the output current, the charge injection from the second switch
contributes by about the same amount as the first switch but in the opposite direction,
hence the result is a fairly accurate representation of the input signal a period before.
The signal dependant component of the charge injection from the switches means that in
fact the final sampled level is not exactly correct, resulting in some distortion.
Switching noise spikes can also be seen, which is a result of the fast changing switch
waveform coupling into the signal path.
6.5.2 Filter simulations

Whilst initial full system simulations for entire SI filters have shown that the circuit
function works to a degree, the filter performances have been somewhat lacking. This
will be addressed in forthcoming work and until then, an example magnitude response
for a low pass filter is shown in Figure 6.11. This filter was designed with first
generation memory cells, and high compliance cascoded structures throughout. Simple
dummy switch clock feedthrough reduction was used and the filter was designed to a
low pass response with cutoff of 5kHz and a sample frequency of 45kHz.
-5
-10
-15
Magnitude (dB)
-20
-25
-30
-35
-40
-45
1 10 100 1000 10000 100000
Frequency (Hz)
Figure 6.11 Magnitude response for a third order low pass SI wave filter
The plot shows a large insertion loss, an altered cutoff frequency and poor stopband
attenuation and is representative of the majority of responses which I have achieved to
date. Typical performances exhibit a large injection loss of 10 to 20 dB, an altered
cutoff frequency of 10 to 20 % below the desired cutoff and a stopband attenuation of
around 40 to 50 dB. The injection loss can generally be put down to conductance ratio
errors and could be improved by better cascode design or by utilisation of a regulated
cascode structure. The cutoff frequency accuracy is a result of a number of factors and
should improve as other problems are solved. Performance could generally be improved
by use of a better memory cell, as until now first generation cells have been used
throughout.
6.6 Summary
Interestingly, the majority of problems encountered during the system development so
far have been practical difficulties concerning the simulation software and technology
design kit. One of the biggest problems was how to obtain a frequency domain response
for a sampled system, and up to this point the technique to achieve this has involved
executing many transient responses to build up the ac response - a time consuming
process often taking several hours. Recent talks with others in the field have lead to the
discovery of Cadence RF tools, namely PSS and PAC analysis, which are capable of
deriving a true AC response in a faction of the time.
As was seen in Section 6.5, the SI filter results achieved so far have not been of very
high performance. However, the cell-based hierarchy described in Sections 6.2 to 6.4
will enable easy development of the system in the future and it should be fairly
straightforward to improve the overall performance by use of different and improved
low-level architectures, as was discussed in Section 6.5.
Chapter 7
Future work
Six months of reading, a few months of development and the writing of this report has
given me a thorough understanding for the areas encompassed by this project. In
Chapter 1 it was explained how the project addresses two main areas, analog IP core
development for design reuse, and the embedded test to compliment these. This Section
considers future work in the context of this breakdown, with Section 7.1 dealing with
the analog core development and Section 7.2 with embedded test. Section 7.3 gives a
time plan for the coming year.
7.1 Filter core generation

It has become clear that the problem of fast analog filter IP design can be restated as:
designing a filter to given performance specifications in the shortest possible time.
This requires firstly consideration and understanding of performance issues at bay, and
secondly, use of techniques and innovation to result in a more rapid design flow.
Sections 6.2 to 6.4 showed the library of hierarchical cells developed to date, which
begin to satisfy the design flow speed-up requirement, but as was illustrated in Section
6.5, performance is still lacking. Future time spent on the core development section of
the project can therefore be broken down in to two areas:
Performance consideration: Section 6.5.2 showed how the SI filters designed so far
have not displayed acceptable performance. Time needs to be spent investigating the
use of different low-level memory cell and current mirror architectures so as to achieve
higher performances in the overall filters. Understanding performance tradeoffs will
allow the best design compromise in terms of certain performance factors, for example
power.
Improved Automation: Section 6.4.3 explained how the SI filter is currently entirely
described by a number of design variables and the adaptor coefficients shown in Figure
6.8. We would like to be able to derive the low-level transistor implementation from
higher-level parameters, such as specifications and constraints. For example the
property form of the filter block (Figure 6.8) might contain fields such as cut-off
frequency, filter order, filter type and constraints such as low power or high accuracy.
The end goals, of this section of the project are the following:
CAD tool: a framework in cadence which will design a transistor level filter, suitable
for simulation, from performance specifications and a minimum of high-level design
parameters. Incorporating layout into the system will not be considered at this stage.
Silicon verification: the layout for suitable example filter design with the system will be
created and submitted for fabrication.
7.2 Embedded test

A great deal of time was spent in Chapter 4 reviewing the numerous analog test
techniques presented in the literature. The conclusion of this review was that rather than
there being a single solution to the analog test issue, a great number of techniques exist,
each suitable in a given context. The following will form the basis of the second section
of the project, concerning embedded test of analog IP cores:
Test method derivation: the most appropriate test solution for analog IP cores must be
derived from those in the literature. Difficulties in SI test must be identified and
addressed. Firstly, the solution should display high fault coverage of a realistic fault list,
as with any embedded test method, and secondly, the test solution should be of flexible
design to make it suitable for rapid development in the context of IP cores.
Integration into CAD tool: ultimately we would like to integrate the inclusion of
embedded test into the CAD system resulting from the first section of the project.
The goals of the embedded test part of the project are envisaged to be:
CAD tool: the CAD tool will now be able to design the filter core including suitable
embedded test for this, if required by the user.
Silicon versification: if it seems appropriate, then a second chip may be fabricated

including the test solution with an example filter core. This chip would also be able to
reflect any changes made to the filter core development in light of the first chip.
7.3 Planning
The next main point of reflection is the 18 month MPhil/PhD transfer report in March
next year. By this stage it is envisaged that the first, analog filter core section, will be
completed, with silicon being submitted early next year. At the 18 month stage it is also
expected that many of the test issues will have been considered, and further direction in
this area will then be known. More immediate goals include submission of an ISCAS
paper based on the work in the coming months, and the submission of an IEE
colloquium paper based on the CAD tool development. Figure 7.1 shows this
graphically.
Prototype CAD tool development phase
ISCAS
IEE
Layout
Silicon
18 month
Embedded test phase
July Aug Sept Oct Nov Dec Jan Feb March April May June
Figure 7.1 Time plan for the coming year

References
[1] J. B. Hughes, "Analogue Techniques for Very Large Scale Integrated Circuits",
PhD Thesis, University of Southampton,1992
[2] S. Matsuzaki and I. Kondo "Information holding apparatus", UK Patent
1359105, 6th July 1972
[3] N. C. Bird "Storing sampled analogue electrical currents", UK Patent 2209895,
16th Sept 1987
[4] N. C. Bird "A method of and a circuit arrangement for processing sampled
analogue electrical signals", UK Patent 2213011, 16th Sept 1987
[5] J. B. Hughes, N. C. Bird, and I. C. Macbeth, "Switched-Currents - A New
Technique for Analog Sampled-Data Signal Processing", presented at the IEEE
International Symposium on Circuits and Systems, Portland, Oregon, pp. 1584-
1587, May 1989.
[6] J. B. Hughes, I. C. Macbeth, and D. M. Pattullo, "Switched-Current Filters", IEE
Proceedings, Pt. G, vol. 137, pp. 156-162, April 1990.
[7] B. Jonsson, "Switched-Current Circuits: from Building Blocks to Mixed
Analog-Digital Systems", PhD Thesis, Royal Institute of Technology,1999
[8] C. Toumazou, J. B. Hughes, and N. C. Battersby, "Switched-currents: an
analogue technique for digital technology": Peter Peregrinus Ltd., 1993.
[9] J. B. Hughes, K. W. Moulding, J. Richardson, J. Bennett, W. Redman-White, M.
Bracey, and R. S. Soin, "Automated Design of Switched-Current Filters", IEEE
Journal of Solid-State Circuits, vol. 31, pp. 898-907, July 1996.
[10] G. Wegmann, E. A. Vittoz, and F. Rahali, "Charge Injection in Analog MOS
Switches", IEEE Journal of Solid-State Circuits, vol. 22, pp. 1091-1097, Dec
1987.
[11] B. Jonsson, "Design of Power Supply Lines in high-Performance SI and
Current-Mode Circuits", presented at the 15th IEEE NORCHIP Conference,
Tallinn, Estonia, pp. 245-250, Nov 1997.
[12] B. Jonsson, "Sampling Jitter in High-Speed SI Circuits", presented at the IEEE
Symposium on Circuits and Systems, Montereym California, pp. 524-526, May
1998.
[13] M. Bracey, "Current Domain Analogue-to-Digital Conversion Techniques for
CMOS VLSI", PhD Thesis, University of Southampton,1997
[14] S. J. Daubert and D. Vallancourt, "Operation and analysis of current copier
circuits", IEE Proceedings, Pt. G, vol. 137, pp. 109-115, April 1990.
[15] M. Ismail and T. Fiez, "Analog VLSI Signal and Information Processing":
McGraw-Hill, 1994.
[16] H. C. Yang, T. S. Fiez, and D. J. Allstot, "Current-Feedthrough Effects and
Cancellation Techniques in Switched-Current Circuits", presented at the IEEE
International Symposium on Circuits and Systems, New Orleans, pp. 3186-3188,
May 1990.
[17] B. Jonsson and S. Eriksson, "New Clock -Feedthrough Compensation Scheme
for Switched-Current Circuits", Electronics Letters, vol. 29, pp. 1446-1447, Aug
1993.
[18] D. G. Nairn and C. A. T. Salama, "A Ratio-Independant Algorithmic Analog-to-

Digital Converter Combining Current-Mode and Dynamic Techniques", IEEE
Transactions on Circuits and Systems, vol. 37, pp. 319-325, March 1990.
[19] J. B. Hughes and K. W. Moulding, "Switched-Current Signal Processing for
Video Frequenceis and Beyond", IEEE Journal of Solid-State Circuits, vol. 28,
pp. 314-322, March 1993.
[20] J. B. Hughes and K. W. Moulding, "S2I: A Two-Step Approach to Switched
Currents", presented at the IEEE International Symposium on Circuits and
Systems, pp. 1235-1238, 1993.
[21] N. C. Battersby and C. Toumazou, "Class AB Switched-Current Memory for
Analogue Sampled Data Systems", Electronics Letters, vol. 27, pp. 873-875,
May 1991.
[22] R. Sitdhikorn, A. Worapishet, and J. B. Hughes, "Low-Voltage Class AB
Switched-Current Technique", Electronics Letters, vol. 36, pp. 14491450, Aug
2000.
[23] A. Worspishet, R. Sitdhikorn, and J. B. Hughes, "Low-Power Complex Channel
Filtering Using Cascoded Class AB Switched-Currents", presented at the IEEE
International Symposium on Circuits and Systems, Scottsdale, Arizona, pp. 453-
456, May 2002.
[24] A. Rueda, A. Yufera, and J. L. Huertas, "Wave Analogue Filters Using Switched
Current Techniques", Electronic Letters, vol. 27, pp. 1482-1483, August 1991.
[25] A. Yufera, A. Rueda, and J. L. Huertas, "Programmable Switched Current Wave
Analog Filters", IEEE Journal of Solid-State Circuits, vol. 29, pp. 927-935,
August 1994.
[26] J. D. Lancaster, B. M. Al-Hashimi, and M. Moniri, "Efficient SI Wave Elliptic
Filters Based on Direct and Inverse Bruton Transformations", IEE Proceedings
of Circuits Devices and Systems, vol. 146, pp. 235-241, October 1999.
[27] A. Fettweis, "Wave Digital Filters: Theory and Practice", Proceedings of the
IEEE, vol. 74, pp. 270-327, Feburary 1986.
[28] A. B. Williams, "Electronic Filter Design Handbook": McGraw-Hill, 1981.
[29] M. F. Toner and G. W. Roberts, "On the practical implementation of mixed
analog-digital BIST", presented at the IEEE Custom Integrated Circuits
Conference, Santa Clara, Califorina, pp. 525-528, May 1995.
[30] A. Grochowski, D. Bhattacharya, T. R. Viswanathan, and K. Laker, "Integrated
Circuit Testing for Quality Assurance in Manufacturing: History, Current Status,
and Future Trends", IEEE Transactions on Circuits and Systems II, vol. 44, pp.
610-632, August 1997.
[31] B. Vinnakota, "Analog and Mixed-Signal Test": Prentice Hall, 1998.
[32] L. S. Milor, "A Tutorial Introduction to Research on Analogue and Mixed-
Signal Circuit Testing", IEEE Transactions on Circuits and Systems II, vol. 45,
pp. 1389-1407, October 1998.
[33] K. Saab, N. B. Hamida, and B. Kaminska, "Closing the Gap Between Analog
and Digital Testing", IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, vol. 20, pp. 307-314, Feburary 2001.
[34] G. W. Roberts, "Improving The Testability Of Mixed-Signal Integrated
Circuits", presented at the IEEE Custom Integrated Circuits Conference,
California, pp. 214-221, May 1997.
[35] G. W. Roberts, "Improving the Testability of Mixed-Signal Integrated Circuits",
presented at the Proceedings of the IEEE Custom Integrated Circuits
Conference, pp. 214-221, May 1997.
[36] S. Cherubal and A. Chatterjee, "Parametric fault diagnosis for analog systems
using functional mapping", presented at the Design, Automation and Test in
Europe Conference and Exhibition, pp. 195-200, March 1999.
[37] P. N. Variyam and A. Chatterjee, "Test Generation for Comprehensive Testing
of Linear Analog Circuits Using Transient response Sampling", presented at the
International Conference on Computer-Aided Design, pp. 382-385, November
1997.
[38] B. Vinnakota and R. Harjani, "DFT for Digital Detection of Analog Parametric
Faults in SC Filters", IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, vol. 19, pp. 789-798, July 2000.
[39] A. Chatterjee and N. Nagi, "Design for Testability and Built-In-Self-Test of
Mixed Signal Circuits: A Tutorial", presented at the 10th International
Conference on VLSI Design, pp. 388-392, January 1997.
[40] P. N. Variyam and A. Chatterjee, "Specification-Driven Test Generation for
Analog Circuits", IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, vol. 19, pp. 1189-1201, October 2000.
[41] S. D. Huynh, S. Kim, and M. Soma, "Automatic Analog Test Signal Generation
Using Multifrequency Analysis", IEEE Transactions on Circuits and Systems II,
vol. 46, pp. 565-576, May 1999.
[42] G. W. Roberts, "Metrics, Techniques and Recent Developments in Mixed-Signal
Testing", presented at the IEEE/ACM International Conference on Computer
Aided Design, California, November 1996.
[43] W. M. Lindermeir, "Design of Robust Test Criteria in Analog Testing",
presented at the International Conference on Computer Aided Design, 1996.
[44] Y. Xing, "Defect-Oriented Testing of Mixed-Signal ICs: Some Industrial
Experience", presented at the International Test Conference, pp. 678-687, 1998.
[45] G. Devarayanadurg and M. Soma, "Dynamic Test Signal Design for Analog
ICs", presented at the IEEE International Conference on Computer-Aided
Design, San Jose, CA, pp. 627-630, November 1995.
[46] T. Olbrich, J. Perez, I. A. Grout, A. M. D. Richardson, and C. Ferrer, "Defect-
oriented vs Schematic-Level based fault Simulation for Mixed-Signal ICs",
presented at the IEEE International Test Conference, Washington DC, pp. 511-
521, October 1996.
[47] M. B. Santos, F. M. Goncalves, M. Ohletz, and J. P. Teixeira, "Defect-Oriented
Testing of Analogue and Mixed Signal ICs", presented at the International
Conference on Electronics, Circuits and Systems, pp. 419-424, September 1998.
[48] A. M. Brosa and J. Figueras, "Digital Signature Proposal for Mixed-Signal
Circuits", Journal of Electronic Testing: Theory and Applications, vol. 17, pp.
385-393, Oct 2001.
[49] K. Arabi and B. Kaminska, "Oscillation Built-In Self Test (OBIST) Scheme for
Functional and Structural Testing of Analog and Mixed Signal Integrated
Circuits", presented at the International Test Conference, pp. 786-795, 1997.
[50] A. Balivada, J. Chen, and J. A. Abraham, "Analog Testing with Time Response
Parameters", IEEE Design and test of Computers, vol. 13, pp. 18-25, 1996.
[51] E. J. Marinissen, R. Kapur, M. Lousberg, T. McLaurin, M. Ricchetti, and Y.
Zorian, "On IEEE P1500's Standard for Embedded Core Test", Submission
manuscript for Journal of Electronic Testing: Theory and Applications, vol. 18,
August 2002.
[52] E. J. Marinissen, R. Kapur, and Y. Zorian, "On Using IEEE P1500 SECT for
Test Plug-n-Play", presented at the IEEE International Test Conference, pp. 770-
777, 2000.
[53] L. Milor and A. L. Sangiovanni-Vincentelli, "Minimising Production Test Time
to Detect Faults in Analog Circuits", IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, vol. 13, pp. 796-813, June 1994.
[54] N. Nagi, A. Chatterjee, A. Balivada, and J. A. Abraham, "Fault-based automatic
test generator for linear analog circuits", presented at the IEEE/ACM
Conference on Computer Aided Design, pp. 88-91, November 1993.
[55] S. Chang, C. L. Lee, and J. E. Chen, "Structural Fault Driven Test Specifications
Reduction for Analog Circuits", presented at the Europrean Test Workshop,
Corfu, Greece, May 2002.
[56] W. M. Lindermeir, T. J. Vogels, and H. E. Graeb, "Analog Test Design with
IDD Measurement for the Detection of Parametric and Catastrophic Faults",
presented at the Design, Automation and Test in Europe, pp. 822-829, March
1998.
[57] H. H. Zheng, A. Balivada, and J. A. Abraham, "A Novel Test Generation
Approach for Parametric Faults in Linear Analog Circuits", presented at the
International Conference on Computer-Aided Design, pp. 382-385, April 1996.
[58] M. Slamani and B. Kaminska, "Multifrequency Analysis of Faults in Analog
Circuits", IEEE Design and Test of Computers, pp. 70-80, Summer 1995.
[59] A. L.-K. Jee, "Carafe: An Inductive Fault Analysis Tool For CMOS VLSI
Circuits", PhD Thesis, University of California,1991
[60] Y. E. Aimine, A. Richardson, C. Descleves, and K. Sommancal, "GDS
FaultSim, a Mixed-Signal IC Computer-Aided-Test (CAT) Tool", presented at
the Design Automation and Test in Europe, Munich, March 1999.
[61] Z. Jaworski, M. Niewczas, and W. Kuzmicz, "Extension of Inductive Fault
Analysis to Parametric Faults in Analog Circuits with Application to Test
Generation", presented at the IEEE VLSI Test Symposium, Monterey, USA, pp.
172-176, 1997.
[62] S. Dragic, I. Filanovsky, and M. Margala, "Low-Voltage Analog Current
Detector Supporting At-Speed BIST", presented at the IEEE International
Symposium on Circuits and Systems, Scottsdale, Arizona, pp. 593-596, May
2002.
[63] Y. Kilic and M. Zwolinski, "Testing Analog Circuits by Supply Voltage
Variation and Supply Current Monitoring", presented at the IEEE Custom
Integrated Circuits Conference, San Diego, California, USA, May 1999.
[64] Y. Kilic and M. Zwolinski, "Process Variation Independant Built-In Current
Sensor for Analog Built-In Self-Test", presented at the IEEE International
Symposium on Circuits and Systems, Sydney, Australia, 2001.
[65] Y. Kilic and M. Zwolinski, "Design and Realisation of a New Built-In Current
Sensor for Mixed-Signal Iddd Test", presented at the IEEE International Mixed
Signal Testing Workshop, Canada, June 1999.
[66] X. Haurie and G. W. Roberts, "Arbitrary-Precision Signal Generation for
Mixed-Signal Built-In-Self-Test", IEEE Transactions on Circuits and Systems
II, vol. 45, pp. 1425-1432, November 1998.
[67] M. Robson and G. Russell, "Current monitoring technique for testing embedded
analogue functions in mixed signal ICs", Electronics Letters, vol. 32, pp. 196-
798, 25th April 1996.
[68] M. Robson and G. Russell, "A BIST Method for Testing an Engine Knock
Detector IC", presented at the Third IEEE International On-Line Testing
Workshop, pp. 105-109, 1997.
[69] M. Robson and G. Russell, "M-Sequence Testing of Embedded Switched
Capacitor Filters", presented at the Baltic Electronics Conference, Tallin,
Estonia, pp. 154-156, 2000.
[70] A. Chatterjee, B. C. Kim, and N. Nagi, "DC Built-In Self-Test for Linear Analog
Circuits", IEEE Design and Test of Computers, pp. 26-33, Summer 1996.
[71] D. D. Venuto, M. J. Ohletz, and B. Ricco, "On-Chip Signal Level Evaluation for
Mixed Signal IC's using Window Comparators", presented at the European Test
Workshop, pp. 68-72, May 2001.
[72] K. Arabi and B. Kaminska, "Testing Analog and Mixed-Signal Integrated
Circuits Using Oscillation-Test Method", IEEE Transactions on Computer-
Aided Design of Integrated Circuits and Systems, vol. 16, pp. 745-753, July
1997.
[73] D. Vazquez, G. Huertas, G. Leger, A. Rueda, and J. L. Huertas, "Practical
Solutions for the Application of the Oscillation-Based-Test in Analog Integrated
Circuits", presented at the IEEE International Symposium on Circuits and
Systems, Scottsdale, Arizona, pp. 589-592, May 2002.
[74] K. J. Lee, W. C. Wang, and K. S. Huang, "A Current-Mode Testable Design of
Operational Transconductance Amplifier-Capacitor Filters", IEEE Transactions
on Circuits and Systems II, vol. 46, pp. 401-413, April 1999.
[75] D. Vazquez, A. Rueda, and J. L. Huertas, "A New Strategy for Testing Analog
Filters", presented at the VLSI Test Symposium, pp. 36-41, April 1994.
[76] E. Cota, L. Carro, M. Renovell, M. Lubaszewski, F. Azais, and Y. Bertrand,
"Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filter",
presented at the Design, Automation and Test in Europe, Paris, France, pp. 226-
230, Feburary 2000.
[77] C. L. Wey, "Built-In Self-Test (BIST) Structure for Analog Circuit Fault
Diagnosis", IEEE Transactions on Instrumentation and Measurement, vol. 39,
pp. 517-521, June 1990.
[78] M. Soma, T. M. Bocek, T. D. Vu, and J. D. Moffatt, "Experimental Results for
Current-Based Analog Scan", presented at the IEEE International Test
Conference, Washington DC, November 1997.
[79] M. Hafed, N. Abaskharoun, and G. W. Roberts, "A Stand-Alone Integrated Test
Core for Time and Frequency Domain Measurements", presented at the IEEE
International Test Conference, Atlantic City, pp. 1031-1040, 2000.
[80] B. Provost, A. M. Brosa, and E. Sanchez-Sinencio, "A Unified Approach for a
Time-Domain Built-In Self-Test Technique and Fault Detection", presented at
the 8th Great Lakes Symposium, 1998.
[81] R. Nadal and A. M. Brosa, "Digital Signature-Based BIST with Ramp Stimuli
for Analog Circuits", presented at the Design, Automation and Test in Europe
Conference, Munich, Germany, pp. 12-15, March 2001.
[82] T. Olbrich and A. Richardson, "Design and Self-Test for Switched-Current
Building Blocks", IEEE Design and Test of Computers, pp. 10-17, Summer
1996.
[83] V. M. z. Bexten, C. Moraga, R. Klinke, W. Brockherde, and K.-G. Hess,
"ALSYN: Flexible Rule-Based Layout Synthesis for Analog IC's", IEEE Journal
of Solid-State Circuits, vol. 28, pp. 261-268, March 1993.
[84] J. D. Bruce, H. W. Li, M. J. Dallabetta, and R. J. Baker, "Analog Layout Using

ALAS!" IEEE Journal of Solid-State Circuits, vol. 31, pp. 271-274, Feburary
1996.
[85] R. A. Pease, "Comments on "Analog Layout Using ALAS!"", IEEE Journal of
Solid-State Circuits, vol. 31, pp. 1364-1365, Sepember 1996.
[86] H. Mathias, J. Berger-Toussan, G. Jacquemod, F. Gaffiot, and M. L. Helley,
"FLAG: A Flexible Layout Generator for Analog MOS Transistors", IEEE
Journal of Solid-State Circuits, vol. 33, pp. 896-903, June 1998.
[87] J. Lakos, "Technology retargeting for IC layout", presented at the IEEE Design
Automation Conference, California, United States, pp. 460 - 465, 1997.
[88] R. Naiknaware and T. S. Fiez, "Automated Hierarchical CMOS Analog Circuit
Stack Generation with Intramodule Connectivity and Matching Considerations",
IEEE Journal of Solid-State Circuits, vol. 34, pp. 304-317, March 1999.
[89] M. Dessouky, M.-M. Louerat, and J. Porte, "Layout-Oriented Synthesis of High
Performance Analog Circuits", presented at the Design Automation and Test in
Europe, Paris, France, pp. 53-57, March 2000.
[90] H. Shibata and N. Fujii, "Automated Design of Analog Computational Circuits
Using Cell-Based Structure", presented at the IEEE International Symposium on
Circuits and Systems, Scottsdale, Arizona, pp. 53-56, May 2002.
[91] J. Rijmenants, J. B. Litsisos, T. R. Schwarz, and M. G. R. Degrauwe, "ILAC: An
Automated Layout Tool for Analog CMOS Circuits", IEEE Journal of Solid-
State Circuits, vol. 24, pp. 417-425, April 1989.
[92] R. Castro-Lopez, F. V. Fernandez, M. Delgado-Restituto, and A. Rodriguez-
Vazquez, "Retargeting of Mixed-Signal Blocks for SoCs", presented at the
Design Automation and Test in Europe, Munich, Germany, pp. 772-773, March
2001.
[93] J. N. Xu, J. Vital, and N. Horta, "Reusability Methodology of IC Layout - Part
II", presented at the Design Automation and Test in Europe, Munich, Germany,
March 2001.
[94] M. Dessouky, A. Kaiser, M.-M. Louerat, and A. Greiner, "Analog Design for
Reuse - Case StudyL Very Low-Voltage Delta Sigma Modulator", presented at
the Design Automation and Test in Europe, Munich, Germany, pp. 353-360,
March 2001.
[95] R. Castro-Lopez, F. V. Fernandez, M. Delgado-Restituto, F. Medeiro, and A.
Rodriguez-Vazquez, "Generation of Technology-Portable Flexible Analog
Blocks", presented at the IEEE International Symposium on Circuits and
Systems, Scottsdale, Arizona, pp. 61-64, May 2002.
[96] Europractice web site 2002, http://www.europractice.com
[97] Y. Kilic, "Testing Techniques and Fault Simulation for Analogue CMOS
Integrated Circuits", PhD Thesis, University of Southampton,2001

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With Embedded Test For

A Nine Month Report, submitted

Supervisor: Dr. B. Al-Hashimi

CHAPTER 4 REVIEW OF ANALOG TEST ............................................................42

Figure 2.1 The original Switched-Current principle introduced in [3, 4] .........................8

Figure 3.3 Current mode implementation of a 3 port series adaptor ..............................40

1.1 Driving factors and goals

1.2 Chapter summary

Figure 2.1 The original Switched-Current principle introduced in [3, 4]

2.2 First generation memory cell

Figure 2.2 First generation memory cell as proposed in [5]

And with a bias current for M2 of J the output current becomes:

iout = ( J + iin ) J = iin ( 2.4 )

Figure 2.3 Example waveforms in the first generation memory cell

2.2.2 Mismatch errors

Weff = W 2WD + w ( 2.5 )

Where is the mismatch error. Knowing that iout = id2 J we get:

iout = (1 + )iin + J ( 2.10 )

iout = iin eJ ( 2.13 )

2.2.3 Conductance ratio errors

M2 M3 id1 1/gds2 1/gm3

2.2.4 Settling effects

This is a second order response with o and Q factor given by:

2.2.5 Clock feedthrough

Figure 2.7 The source of charge injection errors in a memory cell

C ovl = C oxWeff LD ( 2.19 )

The channel charge in the gate capacitance (Cgc) is:

C gc = C oxWeff Leff = C oxWeff (L 2 LD ) ( 2.21 )

Figure 2.8 SI memory cell with parasitic capacitances

C gd ,i = C ovl ,i = C oxWeff ,i LD i = 1,2 ( 2.23 )

Intermediate transition B 1: in this case the channel charge partition is strongly

2.2.7 Voltage drop and timing jitter

2.2.8 Summary of effects

2.3 Second generation memory cell

2.3.2 Mismatch errors

2.3.3 Conductance ratio errors

Figure 2.13 Memory cell conductances and static feedback

If we can assume an ideal source then gin = 0 which gives:

2.3.4 Settling effects

Figure 2.14 Small signal settling of second generation cell

Where the time constant is simply

The square law model gives us:

iM 1 (n) = iM 1 (n 1) + (iin (n) iM 1 (n 1))1 e ( 2.44 )

With o and Q given by:

2.3.5 Clock feedthrough

q = CoxWs Ls (VGS ( s ) VT ( s ) ) 0 < <1 ( 2.54 )

Where q is the charge error contribution given by:

ileak t hold ( 2.65 )

2.3.8 Summary of effects

Finite input/output conductance: this introduces a magnitude error of typically 1% but

2.4 Improved memory cells

Clock feedthrough improvements: clock feedthrough poses the biggest performance

Figure 2.20 Using transmission gates to reduce clock feedthrough [15]

Involving replication of the memory cell, a constant charge injection cancellation

Figure 2.21 Constant clock feedthrough cancellation technique [7]

Figure 2.22 Cancellation of signal dependant clock feedthrough [7]

2.4.2 Improvements to second generation memory cell

Figure 2.23 Cascoded second generation memory cell [13]

2.4.3 S2I memory cell

iout = ( J + i + i ) (J + iin + i ) = iin + i ( 2.66 )

The transmission accuracy is derived in [13] as:

An accuracy improvement of around a magnitude is achieved over the basic second

2.4.4 Class AB memory cell