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CE00057-6 Digital Systems Individual Assignment Page 1 of
Table of Contents
1 OBJECTIVE...........................................................................................................................2
2 INTRODUCTION...................................................................................................................2
2.1 Digital Systems.................................................................................................................2
2.1.1 Sequential Circuit..........................................................................................................4
2.1.2 Combinational circuit....................................................................................................6
2.1.3 ADVANTAGE OF DIGITAL SYSTEM OVER ANALOG SYSTEM.........................9
2.2 VHDL...............................................................................................................................9
2.2.1 HISTORY OF VHDL..............................................................................................10
2.2.2 Uses of VHDL.........................................................................................................11
3 RESEARCH IDEA AND CONCEPT...................................................................................11
3.1 Research Idea..................................................................................................................11
3.2 SEQUENCE DETECTOR.............................................................................................12
3.3 STATE MACHINE.........................................................................................................12
3.3.1 ASM (Algorithmic State Machine)..........................................................................13
3.3.2 FSM (finite state machine)......................................................................................14
3.3.3 DIFFERENCE BETWEEN ASM AND FSM.........................................................15
3.3.4 MEALY MACHINE................................................................................................16
3.3.5 MOORE MACHINE...............................................................................................18
3.3.6 DIFFRANCE BETWEEN MEALY MACHINE AND MOORE MACHINE........19
3.3.7 USES OF SEQUENCE DETECTOR......................................................................20
4 THEORY...............................................................................................................................20
4.1 VHDL THEORY............................................................................................................20
5 STATE TRANSITION DIAGRAM......................................................................................23
5.1 STATE TABLE...............................................................................................................24
6 VHDL PROGRAM AND SIMULATION............................................................................27
7 RESULT................................................................................................................................34
8 CONCLUSION.....................................................................................................................34
9 REFRENCES........................................................................................................................35
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Level 3 Asia Pacific Institute of Information Technology 2016
1 OBJECTIVE
The objective of this assignment is to design & simulate a state machine in VHDL for
detection of Sequence, assuming the sequence to be detected is pre-decided. The predefine
sequence is to be detected as assumed 0101101010101001.
2 INTRODUCTION
2.1 Digital Systems
Most modern electronic devices such as mobile telephones and computers depend on digital
electronics. In fact, most electronics about the home and in industry depend on digital
electronics to work. Digital electronics normally based on logic circuits. These circuits
depend on pulses of electricity to make the circuit work. For instance, if current is present -
this is represented as 1. If current is not present, this is represented as 0. Digital
electronics is based on a series of 1s and 0s. A good example of a digital electronic system is
a mobile phone. As anybody speak into the phone, the digital electronic circuits it contains
converts your voice into a series of electronic pulses (or 1s and 0s). These are transmitted and
the receiving mobile phone then converts the digital pulses back into your voice. Digital
electronics are those electronics systems that use a digital signal instead of an analog signal.
Digital electronics are the most common representation of Boolean algebra and are the basis
of all digital circuits for computers, mobile phones, and numerous other consumer products.
Digital circuits are used because they are efficient and work well, also, digital signals are
easier to transmit than actual sound. The various parts of a computer communicate through
the use of electronic pulses (1s and 0s). Consequently digital logic circuits are ideal for the
internal electronics. The main part of the computer is the motherboard. This is a complex
piece of electronics that processes all the important data. For instance, when word processing,
it is very important to display letters and words on the monitor. The motherboard generates
the individual letters on the monitor by sending a series of 1s and 0s to the screen.
Figure 1 (Example of digital form)

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A digital system is one that is with two well-defined states. Systems based on digital circuits
touch all aspects our present day lives. The present day home products including electronic
games and appliances, communication and office automation products, industrial
instrumentation and control systems, electro medical equipment, and defenses and aerospace
systems are heavily dependent on digital system. This growth is powered by the emerging
new technology, which enables the introduction of more and complex integrated circuits. The
complexity of an integrated circuit is measured in terms of the number of transistors that can
be integrated into a single unit. The number of transistors in a single integrated circuit has
been doubling every eighteen months (Moore Law) for several decades and reached the
figure of almost one billion transistors per chip. This allowed the circuit designers to provide
more and more complex functions in a single unit.
Figure 2 (Block Diagram of digital system)

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THERE ARE MAINLY TWO TYPES OF CIRCUIT IN DIGITAL SYSTEM

Sequential circuit
Combinational circuit
2.1.1 Sequential Circuit

A sequential circuit is a circuit with some feedback from the outputs. In a sequential circuit,
the output state depends on both the inputs and the outputs. The term sequential comes
from the fact that the output depends not only on the current states, but on the states
immediately preceding. Sequential circuit has memory so output can vary based on input.
This type of circuits uses previous input, output, clock and a memory element.
Example: - FLIP-FLOP (like as SR flip-flop, D flip-flop, T flip-flop, Jk flip-flop),
Counters/timers etc.
Figure 3(Sequential circuit)

The description of the SR flip-flop is given below
Block diagram
Figure 4 (Block diagram OF SR flip-flop)
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Circuit diagram
Figure 5 (Circuit diagram OF SR flip-flop)

Truth table of SR FLIP-FLOP
Figure 6 (Truth table of SR flip-flop)

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Description of operation of the truth table
S.N Condition Operation

.
1 S = R = 0 : No change
If S = R = 0 then output of NAND gates 3 and 4
are forced to become 1.Hence R' and S' both will
be equal to 1. Since S' and R' are the input of the
basic S-R latch using NAND gates, there will be
no change in the state of outputs.
2 S = 0, R = 1, E = 1
Since S = 0, output of NAND-3 i.e. R' = 1 and E =
1 the output of NAND-4 i.e. S' = 0.Hence Qn+1 = 0
and Qn+1 bar = 1. This is reset condition.
3 S = 1, R = 0, E = 1
Output of NAND-3 i.e. R' = 0 and output of
NAND-4 i.e. S' = 1.Hence output of S-R NAND
latch is Qn+1 = 1 and Qn+1 bar = 0. This is the reset
condition.
4 S = 1, R = 1, E = 1
As S = 1, R = 1 and E = 1, the output of NAND
gates 3 and 4 both are 0 i.e. S' = R' = 0.Hence
the Race condition will occur in the basic NAND
latch.
2.1.2 Combinational circuit

A logic circuit whose output depends directly on inputs and no other factor is known as
combinational circuit. The most important types of combinational circuit are - RAM, ROM,
Multiplexers, Encoders, Decoders, and DE multiplexers . Combinational circuits are made up
from basic logic NAND, NOR or NOT gates that are combined or connected together to
produce more complicated switching circuits. With combinational logic, the circuit produces
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the same output regardless of the order the inputs are changed. Example of combinational
circuit are encoder, decoder, multiplexer and DE multiplexer, Adder, sub-tractor etc.
Some of the characteristics of combinational circuits are following
The output of combinational circuit depends only on present input.
Circuit do not use any memory. The previous state of input does not have any effect
on the present state of the circuit.
A combinational circuit can have an n number of inputs and m number of outputs.
Figure 7 (combinational circuit)

The description of the SR flip-flop is given below
Block diagram
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Figure 8 (Block diagram of half adder)

Circuit diagram
Figure 9 (Circuit diagram of half adder)

Truth table
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Figure 10 (Truth table of half adder)
2.1.3 ADVANTAGE OF DIGITAL SYSTEM OVER ANALOG SYSTEM

The main advantage of digital signals over analog signals is that the precise signal
level of the digital signal is not vital. This means that digital signals are fairly immune
to the imperfections of real electronic systems which tend to spoil analog signals. As a
result, digital CD's are much more robust than analog LP's.
Codes are often used in the transmission of information. These codes can be used
either as a means of keeping the information secret or as a means of breaking the
information into pieces that are manageable by the technology used to transmit the
code, e.g. The letters and numbers to be sent by a Morse code are coded into dots and
dashes.
Digital signals can convey information with greater noise immunity, because each
information component (byte etc.) is determined by the presence or absence of a data
bit (0 or one). Analog signals vary continuously and their value is affected by all
levels of noise.
Digital signals can be processed by digital circuit components, which are cheap and
easily produced in many components on a single chip. Again, noise propagation
through the demodulation system is minimized with digital techniques.
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Digital signals do not get corrupted by noise etc. You are sending a series of numbers
that represent the signal of interest (i.e. audio, video etc.)
Digital signals typically use less bandwidth. This is just another way to say you can
cram more information (audio, video) into the same space.
Digital can be encrypted so that only the intended receiver can decode it (like pay per
view video, secure telephone etc.)
Enables transmission of signals over a long distance.
Transmission is at a higher rate and with a wider broadband width.
It is more secure.
It is also easier to translate human audio and video signals and other messages into
machine language.
There is minimal electromagnetic interference in digital technology.
It enables multi-directional transmission simultaneously
2.2 VHDL (VHSIC hardware description language)

VHDL stands for VHSIC hardware description language. VHDL is a language to describe a
digital system with certain functionality. Now it has certain inputs and is required to generate
output from it. Any digital system is modeled as an entity in VHDL. When we say an entity
we mean that it has certain input ports, certain output ports and is expected to generate output
from the input and the manner in which it does so is described in architecture. VHSIC means
very-high-speed integrated circuit. As the name suggests it is a hardware description language
used to model a digital system. A language for describing the structural, physical and
behavioral characteristics of digital systems. VHDL is a general-purpose programming
language optimized for electronic circuit design. It has been designed and optimized for
describing the behavior of digital systems. VHDL is a hardware description language which
is used for defining digital electronic systems. It came into lime light by a program issued by
US government's VHSIC (Very High Speed Integrated Circuits) program. During this agenda,
the need for a standard language for reciting the structure and function of integrated circuits
on any effective language became more vital. Hence, the VHSIC Hardware Description
Language (VHDL) was developed. VHDL was afterward developed further under the support
of the IEEE (IEEE Standard 1076). VHDL is now used throughout the globe as a toll for
designing digital systems in many applications. VHDL is designed to fill a number of
necessities in the design flow. Beneficially, the designers can quickly compare other available
options and test for more accuracy without the delay and without doing any hand work on the
real time simulations. Fourth, it allows a thorough structure of a pattern to be combined from
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a more conceptual arrangement. This allows designers to concentrate more on strategic

design decisions and hence proves out to be very helpful and fruitful.
2.2.1 HISTORY OF VHDL

VHDL, which stands for VHSIC (Very High Speed Integrated Circuit) Hardware Description
Language, was developed in the early 1980s during integrated circuit research project funded
by the U.S. Department of Defense. During the VHSIC program, researchers were confronted
with the daunting task of describing circuits of enormous scale (for their time) and of
managing very large circuit design problems that involved multiple teams of engineers. To
meet this challenge, a team of engineers from three companies like IBM, Texas Instruments
and Intermetrics were contracted by the Department of Defense to complete the specification
and implementation of a new, language-based design description method. The first publicly
available version of VHDL, version 7.2, was released in 1985. In 1986, the Institute of
Electrical and Electronics Engineers, Inc. (IEEE) was presented with a proposal to
standardize the language, which it did in 1987 after substantial enhancements and
modifications were made by a team of commercial, government and academic
representatives. The resulting standard, IEEE 1076-1987, is the basis for virtually every
simulation and synthesis product sold today. An enhanced and updated version of the
language, IEEE 1076-1993, was released in 1994, and VHDL tool vendors have been
responding by adding these new language features to their products. Standard packages and
interpretations for VHDL data types as they relate to actual hardware. This standard, which
was released at the end of 1995, is intended to replace the many custom (nonstandard)
packages. The VHDL is hardware description language which uses the syntax of ADA
(Programing Language). Like any hardware description language, it is used for many
purposes for describing hardware as for examples:
2.2.2 Uses of VHDL

It is used as a modeling language.
For simulation of hardware.
As a modelling language
For early performance estimation of system architecture.
For synthesis of hardware
For fault simulation, test and verification of designs etc.
The VHDL representation can be viewed as a text file that describes a digital system. The
digital system may be represented in different ways, such as a behavioral model or a
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structural model. More commonly known as levels of abstraction, these levels help the
designer to develop complex systems efficiently.
The VHDL programming starts with some header file that include the library IEEE and etc,
after the header file the declaration of the entity is done by describing the signal which
connect the hardware to the outside that are also called as ports i.e. the input and the output
port. The entity declares the port signals, their directions and the data types, this signal are
latter used by an architecture associated with this entity.
3 RESEARCH IDEA AND CONCEPT

3.1 Research Idea
VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description
Language. In the mid-1980s the U.S. Department of Defense and the research sponsored the
development of this hardware description language with the goal to develop very high-speed
integrated circuit. It has become now one of industrys standard languages used to describe
digital systems. The other widely used hardware description language is Verilog. Both are
powerful languages that allow you to describe and simulate complex digital systems. A third
HDL language is ABEL (Advanced Boolean Equation Language) which was specifically
designed for Programmable Logic Devices (PLD). ABEL is less powerful than the other two
languages and is less popular in industry. This tutorial deals with VHDL, as described by the
research standard. Although these languages look similar as conventional programming
languages, there are some important differences. A hardware description language is
inherently parallel, i.e. commands, which correspond to logic gates, are executed (computed)
in parallel, as soon as a new input arrives. A HDL program mimics the behavior of a physical,
usually digital, system. It also allows incorporation of timing specifications (gate delays) as
well as to describe a system as an interconnection of different components.
3.2 SEQUENCE DETECTOR

A sequence detector accepts as input a string of bits: either 0 or 1. Its output goes to 1 when a
target sequence has been detected. There are two basic types: overlap and non-overlap. In a
sequence detector that allows overlap, the final bits of one sequence can be the start of
another sequence. Our example will be an 11011 sequence detector. It raises an output of 1
when the last 5 binary bits received are 11011. At this point, a detector with overlap will
allow the last two 1 bits to serve at the first of a next sequence. The data is sent by one bit at a
time, at a very high rate. This movement of data is commonly called a bit stream as an
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example, it is important to identify the beginning and ending of a message. This is the job of
special bit sequences called flags. A flag is simply a pre-defined bit sequence (1101) that
serves as a marker in the bit stream. To detect a flag in a bit stream a sequence detector is
used. To detect a flag in a bit stream a sequence detector is used. It can detect the beginning
of a packet of asynchronous data, like that coming in over wireless or a serial port. A
sequence detector could also be used on a remote control, such as for a TV or garage door
opener. 1011 might correspond to a particular key being pressed.
3.3 STATE MACHINE

State machine designs are widely used for sequential control logic, which forms the core of
many digital systems. State machines are required in a variety of applications covering a
broad range of performance and complexity; low-level controls of microprocessor-to- VLSI-
peripheral interfaces, bus arbitration and timing generation in conventional microprocessors,
custom bit slice microprocessors, data encryption and decryption, and transmission protocols
are but a few examples. Typically, the details of control logic are the last to be settled in the
design cycle, since they are continuously affected by changing system requirements and
feature enhancements. Programmable logic is a forgiving solution for control logic design
because it allows easy modifications to be made without disturbing PC board layout. Its
flexibility provides an escape valve that permits design changes without impacting time-to-
market. A state machine is a machine that makes predictable transitions through a defined
sequence of states, based on external inputs and the current state of the machine. In digital
electronics, the timing of the transition of the machine from one state to another is controlled
by a register and a system clock, while the next state of the machine is determined by a
combination of logic gates and embedded memory. State machines are a method of modeling
systems whose output depends on the entire history of their inputs, and not just on the most
recent input. State machine models can either be continuous time or discrete time.
There are two types of state machine.
ASM
FSM
3.3.1 ASM (Algorithmic State Machine)

The algorithmic state machine (ASM) is a method for designing finite state machines. It is
used to represent diagrams of digital integrated circuits. The algorithmic state diagram is like
a state diagram but less formal and thus easier to understand. In other words ASM stands for
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'Algorithm State Machine 'or simply state machine is the another name given to sequential
network is used to control a digital system which carries out a step by a step procedure. .It
should be noted that ASM charts represent physical hardware and offers several advantages.
Operation of a digital system can be easily understand by inspection of the SM chart.

ASM charts represent physical hardware.
The ASM chart are equivalent to a state graph, and it leads directly to a hardware
realization.
ASM charts can be described the operation of both combinational and sequential
circuits.
ASM charts are easier to understand and can be converted several equivalent form.
The ASM chart may be equivalently expressed as a state and output table.
Figure 11 (ASM)
3.3.2 FSM (finite state machine)
A finite state machine is one that has a limited or finite number of possible states. A finite
state machine can be used both as a development tool for approaching and solving problems
and as a formal way of describing the solution for later developers and system maintainers.
There are a number of ways to show state machines. Finite state machines may sound like a
very dry and boring topic but they reveal a lot about the power of different types of
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computing machine. Every Turing machine includes a finite state machine so there is a sense
in which they come first. They also turn out to be very useful in practice. The simplest type of
computing machine that is worth considering is called a finite state machine. The finite state
machine is also a useful approach to many problems in software architecture, only in this case
you dont build one you simulate it. When a symbol, a character from some alphabet say, is
input to the machine it changes state in such a way that the next state depends only on the
current state and the input symbol. State machines have long been a popular and effective
way of modeling the dynamic behavior of software systems at many different levels. The
previous section explicitly deals with a very low-level representation of a system, with the
understanding that the binary representation can be scaled up to more complex languages and
representations.
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Figure 12 (FSM)
3.3.3 DIFFERENCE BETWEEN ASM AND FSM
ASM FSM
1. An Algorithmic state machine (ASM) is the 1. A model of computation consisting of a

directed connected graph containing an initial set of states, a start state, an input alphabet,
vertex, a final vertex and a finite set of operator and a transition function that maps input
and conditional vertices. symbols and current states to a next state.
Computation begins in the start state with an
input string.
2 Diagram 2 Diagram
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3 The detecting performance as to only text 3 The detecting performance as to only text
typing in ASM was significantly lower than in typing in FSM was significantly higher than
FSM. in ASM.
4 In the case of ASM each condition was 4 As for FSM, the subjects could change
changed automatically every 30 seconds. each condition at their own speed.
TYPES OF FINITE STATE MACHINE
Mealy machine
Moore machine
3.3.4 MEALY MACHINE

Mealy machine is a finite-state machine whose output values are determined both by its
current state and the current inputs. (This is in contrast to a Moore machine, whose output
values are determined solely by its current state.) A Mealy machine is a deterministic finite
state transducer: for each state and input, at most one transition is possible. A Mealy Machine
is an FSM whose output depends on the present state as well as the present input.
It can be described by a 6 tuple (Q, , O, , X, q0) where
Q is a finite set of states.
is a finite set of symbols called the input alphabet.
O is a finite set of symbols called the output alphabet.
is the input transition function where : Q Q
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X is the output transition function where X: Q O
q0 is the initial state from where any input is processed (q0 Q).
Figure 13 (State diagram of mealy machine)
A Mealy machine has outputs that are a function of state and input, that is That is, z = f (qk -
1... q0, xm-1... x0). We usually indicate that the output is dependent on current state and input by
drawing the output on the edge. In the example below, look at the edge from state 00 to state
01. This edge has the value 1/1. This means, that if you are in state 00, and you see an input
of 1, then you output a 1, and transition to state 01. Thus, 1/1 is short hand for x = 1 / z = 1.
Here's a sample Mealy machine.
Figure 14 (Example of Mealy machine)
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3.3.5 MOORE MACHINE

Moore machine is a finite-state machine whose output values are determined solely by its
current state. This is in contrast to a Mealy machine, whose output values are determined
both by its current state and by the values of its inputs. Moore machine is an FSM whose
outputs depend on only the present state.
A Moore machine can be described by a 6 tuple (Q, , O, , X, q0) where
Q is a finite set of states.
is a finite set of symbols called the input alphabet.
O is a finite set of symbols called the output alphabet.
is the input transition function where : Q Q
X is the output transition function where X: Q O
q0 is the initial state from where any input is processed (q0 Q).
The state diagram of a Moore Machine is shown below
Figure 15(state diagram of a Moore Machine)

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Figure 16 (Example of a Moore machine)

.
3.3.6 DIFFRANCE BETWEEN MEALY MACHINE AND MOORE MACHINE
Mealy Machine Moore Machine
Output depends both upon present Output depends only upon the present state.
state and present input.
Generally, it has fewer states than Generally, it has more states than Mealy Machine.
Moore Machine.
Output changes at the clock edges. Input change can cause change in output change as
soon as logic is done.
Mealy machines react faster to In Moore machines, more logic is needed to decode
inputs. the outputs since it has more circuit delays.
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3.3.7 USES OF SEQUENCE DETECTOR

It can detect the beginning of a packet of asynchronous data, like that coming in over wireless
or a serial port. Suppose the only possible data content was 1111 or 0000, but there was a lot
of noise on the signal. The 1011 might signify the start or end of a packet. A sequence
detector could also be used on a remote control, such as for a TV or garage door opener. 1011
might correspond to a particular key being pressed.
4 THEORY
A sequence can be defined as a string of objects, like numbers, that follow a particular
pattern. In a sequence structure, an action, or event, leads to the next ordered action in a
predetermined order. The sequence can contain any number of actions, but no actions can be
skipped in the sequence. The program, when run, must perform each action in order with no
possibility of skipping an action or branching off to another action. All logic problems in
programming can be solved by forming algorithms using only the three logic structures, and
they can be combined in an infinite number of ways. The more complex the computing need,
the more complex the combination of structures. A sequence detector accepts as input a string
of bits: either 0 or 1. Its output goes to 1 when a target sequence has been detected. There are
two basic types: overlap and non-overlap. In a sequence detector that allows overlap, the final
bits of one sequence can be the start of another sequence. Our example will be an 1101
sequence detector. It raises an output of 1 when the last 4 binary bits received are 1101. At
this point, a detector with overlap will allow the last two 1 bits to serve at the first of a next
sequence
4.1 VHDL THEORY

VHDL stands for very high-speed integrated circuit hardware description language. Which is
one of the programming language used to model a digital system by dataflow, behavioral and
structural style of modeling. This language was first introduced in 1981 for the department of
Defense under the VHSIC program. VHDL is one of the standard hardware description
language used to design digital systems. VHDL can be used to design the lowest level or gate
level of a digital system to the highest level in VLSI module. VHDL though being a rigid
language with a standard set of rules allows the designer to use different methods of design
giving different perspectives to the digital system.
In VHDL an entity is used to describe a hardware module. An entity can be described using
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1 Entity declaration
The entity declaration should starts with entity and ends with end keywords. And the ports
are interfaces through which an entity can communicate with its environment. Each port must
have a name direction and a type. An entity may have no port declaration also. The direction
will be input, output. It defines the names input output signals and modes of a hardware
module.
Syntax:
entity entity_name is
port declaration;
end entity_name
2 Architecture
The architecture describes the internal description of design. Each entity has atleast one
architecture and an entity can have many architecture. Architecture defines what is in our
black box that we described using ENTITY. We can use either behavioral or structural models
to describe our system in the architecture. In Architecture we will have interconnections,
processes, components, etc
Syntax:
architecturearchitecture_name of entity_name
architecture_declaration_part;
begin
Statements;
end architecture_name;
3. Package body
The package body is used to declare the definitions and procedures that are declared in
corresponding package. Values can be assigned to constants declared in package in package
body.
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Syntax:
package body package_name is
function_procedure definitions;
end package_name
Types of modeling in VHDL
The internal details of entity are specified by an architecture body using following different
modeling styles:
Structural style of modeling: In Structural style of modeling the entity is described as

a set of interconnected components.
Dataflow style of modeling: In this type of modeling, the flow of data through the
entity is expressed primarily using concurrent signal assignment statements. The
structure of the entity is not explicitly specified in this modeling style, but it can be
implicitly deduced
Behavioral style of modeling: It specifies the behavior of an entity as a set of
statements that are executed sequentially in the specified order. The sequential
statements that are specified inside a process statement do not explicitly specify the
structure of the entity but merely specifies its functionality.
Mixed style of modeling: In mixed modeling, it is possible to mix all the three
modeling styles in a single architecture body. Within an architecture body, it uses
component instantiation statements that represent structure, concurrent signal
assignment statements that represent dataflow, and process statements that represent
behavior
The one of the primary reasons to use VHDL is its power as a test stimulus language. As
logic designs become more complex, comprehensive, up-front verification becomes critical to
the success of a design project. In fact, as you become proficient with simulation, it will
quickly find that your VHDL simulator becomes your primary design development tool. To
simulate project, you will need to develop an additional VHDL program called a test bench.
Test benches emulate a hardware breadboard into which you will "install" synthesizable
design description for the purpose of verification. Test benches can be quite simple, applying
a sequence of inputs to the circuit over time. They can also be quite complex, perhaps even
reading test data from a disk file and writing test results to the screen and to a report file. A
comprehensive test bench can, in fact, be more complex and lengthy (and take longer to
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develop) than the synthesizable circuit being tested. As you will begin to appreciate while
reading this chapter, test bench development will be where you make use of the full power of
VHDL and your own skills as a VHDL "coder". Depending on your needs (and whether
timing information related to your target device technology is available), you may develop
one or more test benches to verify the design functionally (with no delays), to check your
assumptions about timing relationships (using estimates or unit delays), or to simulate with
annotated post-route timing information so you can verify that your circuit will operate in-
system at speed. During simulation, the test bench will be the top level of a design hierarchy.
To the simulator, there is no distinction between those parts of the design that are being tested
and the test bench itself.
5 STATE TRANSITION DIAGRAM

State transition diagrams have been used right from the beginning in object-oriented
modeling. The basic idea is to define a machine that has a number of states (hence the term
finite state machine). The machine receives events from the outside world, and each event
can cause the machine to transition from one state to another.
Figure 17 (state transition diagram)

State S1
Beginning at state S1 when 0 is received it stays in the same state because it has nothing to
remember and the output is 0 because the sequence 1101 is not detected. Only at the instant
when 1101 sequence is detected the output is high, that is, 1. Also remember that the flip
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flops should be used when things are to be remembered by the circuit. When 1 arrives when
in state S1, then it goes to next state S2 and it remembers that 1 was received which is part of
the sequence 1101 which is to be detected.
State S2
When in state S2, when 1 arrives, since it is part of the sequence it goes to next state S3,
meaning it remembers 1. When 0 is received it cannot go to next state S3 (since 1 received
has occupied the transition condition and because 0 is not part of the sequence and there is
nothing to remember), and it cannot remain in the same state S2 because this would mean
010 indefinite loop while in state S2, therefore it goes back to the initial state S1. Consider
100 is received and machine remains in S2 when 0 is received, then because of 1 the state
changes from S1 to S2, then 0 is received then the machine stays in S2 and when another 0 is
received then it stays again in S2. But consider when 100 is received and machine goes back
to S1, then when 1 is received it changes state from S1 to S2, when 0 is received then goes
back to S1 and when another 0 is received it stays in S1.
State S3
When in state S3, when 0 is received then since it is part of the sequence 1101 it goes to new
state S4 because the machine has to remember the new bit 0 as part of the sequence detection
algorithm. When 1 is received it stays in the same state.
State S4
When in state S4, when 1 is received then since it is part of the sequence 1101 to be detected
it goes to S2. And when 0 is received then it goes back to initial state S1. At this point the
machine outputs 1.
5.1 STATE TABLE

A table can be described by its row headings and its column headings. Its entries occur at the
intersections of the rows and columns. To describe the operation of a synchronous machine, it
is customary to choose the row headings as the present states and the column headings as the
inputs. Since two outcomes (next state, output) result from an input to the circuit when the
circuit is in a particular state, it is conceivable to construct two separate tables. The entries in
one of these would be the circuit outputs hence it is called the output table. The entries in the
other table would be the next states. Since the table is intended to show transitions from a
present state to a next state, it might be tempting to call this table a state transition table. State
__________________________________________________________________________________________
transition diagrams were around long before object modeling. They give an explicit, even a
formal definition of behavior. A big disadvantage for them is that they mean that you have to
define all the possible states of a system. Whilst this is all right for small systems, it soon
breaks down in larger systems as there is an exponential growth in the number of states. This
state explosion problem leads to state transition diagrams becoming far too complex for much
practical use. A state diagram shows the behavior of classes in response to external output.
Specifically a state diagram describes the behavior of a single object in response to a series of
events in a system. Sometimes it's also known as a state machine diagram. This diagram
models the dynamic flow of control from state to state of a particular object within a system
Present state Input Next state Output Flip Flop/Input
A B X An+1 Bn+1 Y Da Db
0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 1
0 1 0 0 0 0 0 0
0 1 1 1 0 0 1 0
1 0 0 1 1 0 1 1
1 0 1 1 0 0 1 0
1 1 0 0 0 0 0 0
1 1 1 0 1 1 0 1
5.2 K-map for Output Y for X input
BA
00 01 11 10
X
(0) (1) (3) (2)

0 0 0 0 0
(4) (5) (7) (6)

1 0 0 11 0
By solving the K-Map we have got the Boolean expression for output
Y = BAX
__________________________________________________________________________________________
Figure 18 (Logic circuit of output of 1101 sequence)

K-map for Da
BA
00 01 11 10
X
(0) (1) (3) (2)
0 0 0 1 0
(4) (5) (7) (6)
1 1 1 0 0
By solving the K-Map for input of the D flip flop we get the expression for Da as
B X BA X
Da =
Figure 19 (Logic circuit diagram of Input of Da flip flop)
__________________________________________________________________________________________
K-map for Db
BA
00 01 11 10
X
0 0 (0) (1)
1 (1)
0 (3)
0 (2)
(4) (5) (7) (6)

1 1 0 1 0
Boolean expression
By solving the K-Map for input of the D flip flop we get the expression for Db as
ABX X A B X A B
Db =
Figure 20 (Logic circuit diagram of input of Db flip flop)
6 VHDL PROGRAM AND SIMULATION

The VHDL code for implementing this sequence detector is below
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity sequence_detector is
port (
clk: in STD_LOGIC;
rst: in STD_LOGIC;
x: in STD_LOGIC;
z: out STD_LOGIC);
__________________________________________________________________________________________
end sequence_detector;
architecture sequence_detector_arch of sequence_detector is
type seq_detect_type is (
a, b, c, d
);
signal seq_detect: seq_detect_type;
begin
seq_detect_machine: process (clk)
begin
if clk'event and clk = '1' then
if rst='1' then
seq_detect <= a;
else
case seq_detect is
when a =>
if x = '1' then
seq_detect <= b;
elsif x = '0' then
seq_detect <= a;
end if;
when b =>
if x = '1' then
seq_detect <= c;
elsif x = '0' then
seq_detect <= a;
end if;
when c =>
if x = '1' then
seq_detect <= c
elsif x = '0' then
seq_detect <= d;
end if;
__________________________________________________________________________________________
when d =>
if x = '1' then
seq_detect <= b;
elsif x = '0' then
seq_detect <= a;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
z_assignment:
z <= '0' when (seq_detect = a and x = '1') else
'0' when (seq_detect = a and (x = '0' and not (x = '1'))) else
'0' when (seq_detect = b and x = '1') else
'0' when (seq_detect = b and (x = '0' and not (x = '1'))) else
'0' when (seq_detect = c and x = '1') else
'0' when (seq_detect = c and (x = '0' and not (x = '1'))) else
'1' when (seq_detect = d and x = '1') else
'0' when (seq_detect = d and (x = '0' and not (x = '1'))) else
'0';
end sequence_detector_arch;
__________________________________________________________________________________________
Figure 21 Outer circuit of predefine sequence detector
Figure 22 (Internal circuit of predefine sequence detector)

__________________________________________________________________________________________
Figure 23 (Inner most circuit diagram of predefine sequence detector)
The testbench code for the sequence detector is,

library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity sequence_detector_tb is
end sequence_detector_tb;
architecture TB_ARCHITECTURE of sequence_detector_tb is

component sequence_detector
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
x : in STD_LOGIC;
__________________________________________________________________________________________
z : out STD_LOGIC );
end component;
signal clk : STD_LOGIC;
signal rst : STD_LOGIC;
signal x : STD_LOGIC;
signal z : STD_LOGIC;
begin
UUT : sequence_detector
port map (
clk => clk,
rst => rst,
x => x,
z => z
);
clk_process : process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
sti_process: process
begin
x <= '1';
wait for 20 ns;
x <= '0';
wait for 20 ns;
x <= '0';
wait for 20 ns;
x <= '0';
wait for 20 ns;
__________________________________________________________________________________________
x <= '1';
wait for 20 ns;
x <= '0';
wait for 20 ns;
x <= '1';
wait for 20 ns;
x <= '1';
wait for 20 ns;
x <= '0';
wait for 20 ns;
x <= '1';
wait for 20 ns;
x <= '0';
wait for 20 ns;
x <= '1';
wait for 20 ns;
x <= '0';
wait for 20 ns;
x <= '0';
wait for 20 ns;
x <= '1';
wait for 20 ns;
__________________________________________________________________________________________
x <= '0';
wait for 20 ns;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_sequence_detector of sequence_detector_tb is
for TB_ARCHITECTURE
for UUT : sequence_detector
use entity work.sequence_detector(sequence_detector_arch);end for;
end for;
end TESTBENCH_FOR_sequence_detector;
7 RESULT
Figure 24 (wave form of sequence 1101)
8 CONCLUSION
The design implemented in VHDL Hardware Description Language. It was simulated using
Xilinx simulator. State machines are such a general formalism, that a huge class of discrete-
time systems can be described as state machines. The system of defining primitive machines
and combinations gives us one discipline for describing complex systems. It will turn out that
there are some systems that are conveniently defined using this discipline, but that for other
kinds of systems, other disciplines would be more natural. State machines are such a general
class of systems that although it is a useful framework for implementing systems, we cannot
generally analyze the behavior of state machines. It has learnt about all the basic knowledge
of the digital circuit the design of Sequence detector was a full of knowledge with a live
operation on the software.
__________________________________________________________________________________________
9 REFRENCES
Ee.surrey.ac.uk. (2016). Introduction to Sequential Circuits. [online] Available at:
http://www.ee.surrey.ac.uk/Projects/Labview/Sequential/Course/03-Seq_Intro/Intro.html
[Accessed 12 Apr. 2016].
Electrosofts.com. (2016). INTRODUCTION TO VHDL : ElectroSofts.com. [online] Available

at: http://electrosofts.com/vhdl/ [Accessed 8 Apr. 2016].
Google.co.in. (2016). [online] Available at: https://www.google.co.in/url?

sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwju5qKCv4z
MAhUHKZQKHX7JDBIQFggcMAA&url=http%3A%2F%2Fwww.cse.uconn.edu%2F~zshi
%2Fcourse
%2Fcse2300%2Flecture11_statemachines.pdf&usg=AFQjCNF_2hGlA1uCR97hBTcC8EjO
MOhXQA [Accessed 10 Apr. 2016].
Google.co.in. (2016). [online] Available at: https://www.google.co.in/url?

sa=t&rct=j&q=&esrc=s&source=web&cd=3&cad=rja&uact=8&ved=0ahUKEwio1NDoy4z
MAhVHFJQKHUR9D6cQFggoMAI&url=https%3A%2F%2Fwww.ee.iitb.ac.in
%2Fvlabsfpga%2Fdocs
%2FExpt2%2Ftheory.pdf&usg=AFQjCNEyGspfSkEKad7SFGZOj_4NCL0JlQ [Accessed 11
Apr. 2016].
Mealy, G. (1955). A method for synthesizing sequential circuits. Bell Syst. Tech. J., 34(5),
pp.1045-1079.
Nair, A. (2013). Analysis of state machines. [online] Slideshare.net. Available at:

http://www.slideshare.net/abhilash128/lec3-16642917 [Accessed 10 Apr. 2016].
Safari. (2016). 9.7 Finite-State Machine Analysis [Book]. [online] Available at:
https://www.safaribooksonline.com/library/view/introduction-to-
digital/9780470900550/chap9-sec015.html [Accessed 4 Apr. 2016].
Slideshare.net. (2016). Introduction state machine. [online] Available at:

http://www.slideshare.net/ishonp98/introduction-state-machine [Accessed 11 Apr. 2016].
__________________________________________________________________________________________
Uhaweb.hartford.edu. (2016). Sequence Detection -- Introductory Notes. [online] Available

at: http://uhaweb.hartford.edu/kmhill/suppnotes/sequence/seqdet.htm [Accessed 12 Apr.
2016].
WhatIs.com. (2016). What is digital? - Definition from WhatIs.com. [online] Available at:
http://whatis.techtarget.com/definition/digital [Accessed 11 Apr. 2016].
Anon (2016). [Online]. 2016. Available from:

http://electronics.wikia.com/wiki/Digital_electronics. [Accessed: 10 April 2016].

http://www.technologystudent.com/elec1/dig1.htm. [Accessed: 14 April 2016].
Anon (2016). [Online]. 2016. Available from: http://www.ni.com/example/14493/en/.

[Accessed: 10 April 2016].

http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm.

http://www.thelearningpoint.net/home/electrical-science-and-engineering/introduction-
to-. [Accessed: 11 April 2016].
Anon (2016). [Online]. 2016. Available from: http://www.asic-

world.com/digital/seq1.html. [Accessed: 11 April 2016].
Anon (2016). [Online]. 2016. Available from: http://www.electronics-

tutorials.ws/sequential/seq_1.html. [Accessed: 13 April 2016].

http://whatis.techtarget.com/definition/sequential-logic. [Accessed: 11 April 2016].

http://www.allaboutcircuits.com/textbook/digital/chpt-9/combinational-logic-functions/.
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CE00057-6 Digital Systems Individual Assignment Page 1 of

Figure 1 (Example of digital form)

Figure 2 (Block Diagram of digital system)

THERE ARE MAINLY TWO TYPES OF CIRCUIT IN DIGITAL SYSTEM

2.1.1 Sequential Circuit

Figure 3(Sequential circuit)

Figure 4 (Block diagram OF SR flip-flop)

Figure 5 (Circuit diagram OF SR flip-flop)

Figure 6 (Truth table of SR flip-flop)

Description of operation of the truth table

S.N Condition Operation

2.1.2 Combinational circuit

Some of the characteristics of combinational circuits are following

The output of combinational circuit depends only on present input.

A combinational circuit can have an n number of inputs and m number of outputs.

Figure 7 (combinational circuit)

Figure 8 (Block diagram of half adder)

Figure 9 (Circuit diagram of half adder)

Figure 10 (Truth table of half adder)

2.1.3 ADVANTAGE OF DIGITAL SYSTEM OVER ANALOG SYSTEM

2.2 VHDL (VHSIC hardware description language)

a more conceptual arrangement. This allows designers to concentrate more on strategic

2.2.1 HISTORY OF VHDL

2.2.2 Uses of VHDL

3 RESEARCH IDEA AND CONCEPT

3.2 SEQUENCE DETECTOR

3.3 STATE MACHINE

There are two types of state machine.

3.3.1 ASM (Algorithmic State Machine)

Operation of a digital system can be easily understand by inspection of the SM chart.

1. An Algorithmic state machine (ASM) is the 1. A model of computation consisting of a

TYPES OF FINITE STATE MACHINE

3.3.4 MEALY MACHINE

It can be described by a 6 tuple (Q, , O, , X, q0) where

Q is a finite set of states.

is a finite set of symbols called the input alphabet.

O is a finite set of symbols called the output alphabet.

is the input transition function where : Q Q

X is the output transition function where X: Q O

Figure 13 (State diagram of mealy machine)

Figure 14 (Example of Mealy machine)

3.3.5 MOORE MACHINE

A Moore machine can be described by a 6 tuple (Q, , O, , X, q0) where

Q is a finite set of states.

is a finite set of symbols called the input alphabet.

O is a finite set of symbols called the output alphabet.

is the input transition function where : Q Q

X is the output transition function where X: Q O

The state diagram of a Moore Machine is shown below

Figure 15(state diagram of a Moore Machine)

Figure 16 (Example of a Moore machine)

3.3.7 USES OF SEQUENCE DETECTOR

4.1 VHDL THEORY

package body package_name is

Types of modeling in VHDL

Structural style of modeling: In Structural style of modeling the entity is described as

5 STATE TRANSITION DIAGRAM

Figure 17 (state transition diagram)

5.1 STATE TABLE

Present state Input Next state Output Flip Flop/Input

5.2 K-map for Output Y for X input

(0) (1) (3) (2)

(4) (5) (7) (6)