Beruflich Dokumente
Kultur Dokumente
eg in
er ) b
i p lex or b
t a
mul or
/ 2:1 @(sel <= b;
/
ays ) z
alw (sel <= a;
i f
e z
els
end
Ga on
te cti ry
Lib Instremo
u
0
r ar M B
A
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1
configurations;
Transistor-level simulators;
Software generators to create dense transistor layouts;
1980 : Circuits had 100K transistors
Tools:
Logic Synthesis tools to go from Gate netlists to a
standard cell netlist for a given cell library.
Powerful optimizations!
Simulation tools for gate netlists, RTL;
IBM and other companies had internal tools that emphasized top
down design methodology based on logic synthesis.
Idea: once a behavioral model has been finished why not use
it to automatically synthesize a logic implementation in much
the same way as a compiler generates executable code from a
source program?
a
b
assign z = (a & b) | c; c z
a
b
c z
// dataflow a 1
0 z
assign z = sel ? a : b; b
sel
a
sel z
b
As a default + is implemented as
a ripple carry editor
module parity(in,p);
parameter WIDTH = 2; // default width is 2
input [WIDTH-1 : 0] in;
output p;
// simple approach: assign p = ^in;
reg p;
integer i;
parity
reg parity = 0;
for (i = 0; i < WIDTH; i = i + 1) word[2]
parity = parity ^ in[i];
p <= parity; word[1]
end word[0]
endmodule XOR with 0 input has
been optimized away
reg q;
// D-latch d D Q q
always @(g or d) begin
if (g) q <= d; g G
end
reg q;
// register with synchronous clear
always @(posedge clk) begin d D Q q
reset
if (!reset) // reset is active low
q <= 0; clk
else
q <= d;
end
reg q;
// register with asynchronous clear
always @(posedge clk or negedge reset) d D Q q
begin
if (!reset) // reset is active low clk
q <= 0;
else // implicit posedge clk
q <= d; reset
end
// warning! async inputs are dangerous!
// theres a race between them and the
// rising edge of clk.
6.884 - Spring 2005 02/14/05 L05 Synthesis 10
Technology-independent* optimizations
** None
None of of these
these operations
operations isis completely
completely isolated
isolated from
from thethe
target technology. But experience has shown
target technology. But experience has shown that its that its
advantageous
advantageous to to reduce
reduce the
the size
size of
of the
the problem
problem asas much
much as as
possible before starting the technology-dependent
possible before starting the technology-dependent
optimizations.
optimizations. In In some
some places
places (e.g.
(e.g. the
the ratio
ratio of
of the
the size
size
of
of storage
storage elements
elements toto the
the size
size logic
logic gates)
gates) our
our assumptions
assumptions
will
will be
be valid
valid for
for several
several generations
generations of of the
the technology.
technology.
Optimization criteria:
- number of product terms
- number of literals
- a combination of both
W X Y Z label
Express your Boolean function using 0-terms 0 0 0 0 0
(product terms with no dont care care 0 1 0 1 5
0-terms:
entries). 0 1 1 1 7
1 0 0 0 8
Include only those entries where the output 1 0 0 1 9
of the function is 1 (label each entry with 1 0 1 0 10
its decimal equivalent). 1 0 1 1 11
1 1 1 0 14
1 1 1 1 15
1-terms:
8, 9 100-
8,10 10-0
Next 1-terms are examined in pairs to 9,11 10-1
see if the can be merged into 2-terms, 10,11 101-
etc. Mark k-terms that get merged into
10,14 1-10
2-terms:
Label unmerged terms:
8, 9,10,11 10--[D]
10,11,14,15 1-1-[E]
Example due to these terms are prime!
Srini Devadas
3-terms: none!
6.884 - Spring 2005 02/14/05 L05 Synthesis 13
Prime Term Table
Goal:
Goal: select
select the
the
A B C D E
minimum
minimum set set ofof primes
primes
0000 X . . . . A is essential
(columns)
(columns) such
such that
0101 . X . . . B is essential
that
there
there isis at
at least
least one
0111 . X X . .
one 1000 X . . X .
X in every
X in every row.row. 1001 . . . X . D is essential
This
This isis the
the classical
classical 1010 . . . X X
minimum
minimum covering
covering 1011 . . . X X
problem.
problem. 1110 . . . . X E is essential
1111 . . X . X
Some functions may not have essential primes (Fig. 1), so make
arbitrary selection of first prime in cover, say A (Fig. 2). A
column U of a prime term table dominates V if U contains every
row contained in V. Delete the dominated columns (Fig. 3).
A B C D E F G H B C D E F G H
C D E F G
0000 X . . . . . . X 0101 X X . . . . .
0101 X . . . . C is essential
0001 X X . . . . . . 0111 . X X . . . . 0111 X X . . .
0101 . X X . . . . . 1000 . . . . . X X
1000 . . . . X G is essential
0111 . . X X . . . . 1010 . . . . X X . 1010 . . . X X
1000 . . . . . . X X 1110 . . . X X . . 1110 . . X X .
1010 . . . . . X X . 1111 . . X X . . . 1111 . X X . .
1110 . . . . X X . .
CC dominates
dominates B,
B, Selecting
Selecting CC and
and GG
1111 . . . X X . . .
GG dominates H
dominates H shows
shows that
that only
only EE isis
needed
needed to
to complete
complete
the cover
the cover
1. Delete the dominated primes (columns) in T. Detect essential primes in T by checking to see if
any 0-term is contained by a single prime. Add these essential primes to the selected set. Repeat
until no new essential primes are detected.
2. If the size of the selected set of primes equals or exceeds the best solution thus far return from
this level of recursion. If there are no elements left to be contained, declare the selected set as the
best solution recorded thus far.
4. Add the chosen prime to the selected set and create a new table by deleting the prime and all 0-
terms that are contained by this prime in the original table. Set T to this new table and go to Step 1.
Then, create a new table by deleting the chosen prime from the original table without adding it to the
selected set. No 0-terms are deleted from the original table. Set T to new table and go to Step 1.
functions.
time.
Example due to
Kurt Keutzer
13
13
10
11
Possible Covers
Z
Y
Complexity:
Complexity:
To
To determine
determine the the optimal
optimal cover
cover for
for
aa tree
tree we
we only
only need
need to to consider
consider aa
best-cost
best-cost match
match at at the
the root
root of
of the
the P
tree
tree (constant
(constant timetime inin the
the number
number
of
of matched
matched cells),
cells), plus
plus the
the optimal
optimal
cover
cover for
for the
the subtrees
subtrees starting
starting at
at Best cover for
each
each input
input to
to the
the match
match (constant
(constant this match uses
time
time in
in the
the fanin
fanin ofof each match)
each match) best covers for
O(N)
O(N) P & Z
6.884 - Spring 2005 02/14/05 L05 Synthesis 22
Optimal tree covering example
Example (III)
Verilog Gate
Logic Synthesis netlist Place & route Mask
HDL logic create floorplan blocks
map to target library place cells in block
optimize speed, area route interconnect
optimize (iterate!)