International Conference on Communication and Signal Processing, April 6-8, 2016, India

Performance of Low Power BISTArchitecture for

UART
V. Thirunavukkarasu, R.Saravanan and V.Saminadan

AbstractUniversal Asynchronous Receiver Transmitter
(UART) is used for exchanging data between computer and
peripherals at a very short distance. In this paper, Built in Self
Test (BIST) architecture with Bit Swapping Linear Feedback
Shift Register (BS-LFSR) is used for testing UART. Generally,
BIST for UART consists of test patterns obtained from
conventional LFSR. BS-LFSR consists of shift registers,
Multiplexers and a XOR logic gate. Pattern generation in BS-
LFSR is similar to the normal LFSR but the sequence of the test
pattern will be different. This method reduces the power
consumption during testing of circuits by reducing number of
switching activities when compared to the conventional LFSR. In
the Bit-swapping LFSR maintaining randomness in the test
pattern generation is the most important factor. Because of this
randomness it gives high fault coverage. The main advantages of
this work are better power reduction and less hardware
requirement.
KeywordsBIST, UART,BS-LFSR,Switching activities.
To test a circuit, the circuit typically requires an additional
circuitry and some functionality that should be incorporated
into the design of the circuit for smooth functioning. This
additional functionality should be capable of generating test
patterns as well as it should be able to provide a mechanism to
determine whether the output response of the circuit under test
(CUT) have some fault or not. In this paper, UART is tested
using BS-LFSR. The BS-LFSR consumes low power while
testing the circuits, because of the reduced transition activity
when compared to the conventional LFSR [2].
This paper is organized as follows, Section II Introduces
Built In Self Test, Section III describes about UART, Section
IV describes the working of BS-LFSR, section V describes the
implementation of BS-LFSR architecture for UART, Section
VI gives the simulated results of the BS-LFSR BIST and
Section VII is the conclusion of the paper and finally
references.

I. INTRODUCTION
There are three phases in the life-cycle of a product in
which testing plays an important role. Many testing issues can
be addressed during the development and design of a product,
but the main aim is to give high quality standard testing at a
minimal cost. This criteria has become the most difficult task
to achieve because of increased component density in Very
Large Scale Integrated (VLSI) circuit. Many companies have
reported that cost of testing a circuit sometimes reaches to
about half of the total product cost. In such scenario, BIST
plays a vital role in the field of testing by reducing the cost of
testing without the need of external testing circuitry [1].The
concept of BIST is to design a circuit to test itself and
determine whether the circuit has some fault or not.
V. Thirunavukkarasu is with the Electronics and Communication Engineering
Department, Pondicherry Engineering College, Puducherry, India (email:
thirunavukkarasu.ec@gmail.com).
II. SYSTEM MODEL
A. BUILT IN SELF TEST
The BIST architecture is shown in Fig. 1. BIST consists of:
Circuit Under Test
Circuit under test is the portion of the circuit to be tested in
the BIST. It can be sequential circuits or combinational
circuits.
Test Pattern Generator
Test patterns are generated for Circuit under Test using the
test pattern generator. The generated test patterns can be of
random type. Normally, test pattern generator generates
exhaustive type of test patterns for the Circuit under Test to
cover the maximum fault.
Output Response Analysis
The ORA reduces the output of the CUT from many
patterns to a single Pass or Fail indication. The ORA is also
known as an output data compaction (ODC) circuit.

R. Saravanan is with the Electronics and Communication Engineering

Department, Pondicherry Engineering College, Puducherry, India(email:
saravananneo@gmail.com).

V. Saminadan is with the Electronics and Communication Engineering

Department, Pondicherry Engineering College, Puducherry, India(email:
saminadan@pec.edu).

978-1-5090-0396-9/16/$31.00 2016 IEEE

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B. ARCHITECTURE
Fig. 1. BIST Architecture
The test vectors are generated from the pattern generator
for the circuit under test [3]. The generated random test
pattern were fed into the multiplexer unit as input .The BIST
architecture consists of two modes former mode is Test mode
and the latter mode is Normal mode. In the normal mode the
primary inputs are given externally which is fed as the
multiplexer unit input. BIST operation is controlled by the
controller, when the test signal is high the test mode is
activated. During the test mode the pattern is generated by
using TPG which are fed as inputs to the circuit under test. If
the test signal is low, normal mode. In normal mode the
primary inputs are fed to the CUT through multiplexer .The
multiplexer is used to select the test pattern either from the
TPG or externally for the circuit under test. The expected
output response of the CUT is stored in the memory. In test
mode the test patterns are generated from the TPG using
LFSR and it is applied as input to the CUT. The output from
the CUT is stored in the Output Response Analyzer.
Comparator in the BIST compares the actual response and
expected responses. If both the responses matches then the
status will become 0, which indicated that the circuit is fault
free. If the output response and expected response mismatches
then the status will become 1, which indicates that the circuit
under test has some fault. During the normal mode circuit
under test (CUT) does its normal operation (i.e.) when an
input is forced to the CUT it produces an output but the status
will be always at 0 even though when there is any fault in the
circuit. In this mode the circuit will not be tested.
III. BIT SWAPPINGLFSR
The Bit swapping LFSR is shown in Fig.2.
power BS-LFSR is used instead of conventional LFSR. Based
on the observations of transition produced by LFSR at the
output leads to the Bit-Swapping LFSR. In modified form of
normal LFSR, swapping of bits were used in between the pair
of adjacent cells.
After swapping of bits from two adjacent cells, the BS-
LFSR have same number of 0s and 1s at the output of the
multiplexers, hence the chance of having 0 or 1 before
applying the test vectors will be equal. Therefore this design
maintains an important features of random Test Patter
generation. Further, the multiplexer output depends on three
different cells of the LFSR, where each cell contains a random
value. Hence, the desired value at the output of BS-LFSR will
a random value. Swapping arrangement will save number of
transitions upto 25%.
IV. UARTARCHITECTURE
Universal Asynchronous Receiver Transmitter (UART) is a
type of serial communication device which is used for short-
distance communication as shown in Fig.3. UART is used for
communicating serially by converting data to serial from
parallel at the transmitter side and again to parallel from serial
at the receiver side [4].
Fig. 3. UART Architecture
V. BS-LFSR ARCHITECTURE FOR UART
In this paper, Built In Self Test is implemented using Bit-
swapping linear feedback shift register (BS-LFSR) for testing
UART as shown in Fig. 4. This work uses the test pattern
obtained from BS-LFSR which can reduce switching activities
when compared to traditional LFSR. The BS-LFSR consists of
linear feedback shift register, counter and a gray code
generator.
BS-LFSR shown in Fig. 4 generates a new seed when
Clock1 is clocked for one time. The Johnson counter produces
a new test vector when clock2 is clocked. The step is repeated
until 2K Johnson vectors are generated [5]. The Output
Response Analyzer is used to compare the output data from
the Circuit under test and the serial to parallel converter to
gives the BIST status.

Fig. 2. Bit Swapping LFSR

Generally, BIST for UART consists of test patterns obtained

from conventional linear feedback shift register. Since the test
patterns are generated randomly it significantly increases the Fig. 4. UART testing using BS- LFSR.
power consumption and test storage during the testing of
circuit. In order to decrease the power consumption a low

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 VI. SIMULATED RESULTS
A. TEST PATTERN GENERATION
The BS-LFSR generates a new seed when clock1 is
clocked for one time. The new vector is generated from
Johnson counter by clocking Clock2 one time. The step is
repeated until 2K Johnson vectors are generated.
B. TRANSMITTER BLOCK
The K_stx indicates the start bit and the k_xtx denotes the
stop bit. The data given to the UART from the BS-LFSR is
shown as data_uart in the Fig. 5.

Fig. 7. RTL View of BS-LFSR BIST

E. TECHNOLOGY SCHEMATIC OF BS-LFSR BIST

Fig. 5.Transmitter block of BS-LFSR BIST
C. RECEIVER BLOCK
Data_a and data_b are transmitted and received data
respectively which are equal to each other as shown in the
fig.6. So it is evident that circuit is a good Circuit.
Technology schematic is generated after the
optimization and targeting phase of the synthesis process
which is shown in the Fig. 8. In this Technology
schematic the design is represented in terms of LUTs.
Technology schematic allows the designer to see a
technology level representation of HDL, which might
help the designer to discover any design issues.

Fig. 8. Technology Schematic BS-LFSR BIST

F. POWER ANALYSIS FOR BS-LFSR BIST

Fig. 6. Receiver block of BS-LFSR BIST
The power is estimated for the BIST with BS-LFSR. The
D. RTL VIEW OF BS-LFSR BIST BIST with BS-LFSR consumes 0.052 W during the testing of
The RTL view of BIST with BS-LFSR consists of a baud circuits as shown in Fig. 9 and in Table I.
clock generator, transmitter block, receiver block and a
comparator which is shown in the Fig. 7. The Baud Clock
Generator is the component which allows to vary the signaling
rate and communicate with a variety of devices. The
comparator in the BIST is used to compare the output from the
transmitter block and the receiver block. If both the data are
equal then the comparator output will be 0 otherwise the
output will be 1.
Fig. 9. Power Analysis of BS-LFSR BIST

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 TABLE - 1 REFERENCES
[1] Charles E. Stroud, A Designer's Guide to Built-in Self-Test, Kluwer
POWER CONSUMPTION COMPARISON Academic Publisher, 2002, pp. 1-80.

[2] Abdallatif and S. Abu-Issa, Bit-Swapping LFSR and Scan-Chain

LFSR BS-LFSR Ordering: A Novel Technique for Peak- and Average-Power Reduction in
Parameter Scan-Based BIST, IEEE Transactions on Computer-Aided Design of
BIST BIST Integrated Circuits and Systems, vol. 28, pp. 755-759, April 2009.
Power Consumption 0.081 W 0.052 W [3] Nourani, M.; Tehranipoor, M.; Ahmed, N., "Low-Transition Test Pattern
Generation for BIST-Based Applications," IEEE Transactions on
Computers, vol.57, no.3, pp.303-315, March 2008

VII. CONCLUSION
In this paper, the UART is tested using the BS-LFSR BIST.
The BIST with BS-LFSR consumes 0.052 W during the
testing of circuits whereas the BIST with conventional LFSR
consumes 0.081W [6] during the testing of circuits as given in
Table I.
[4] Naresh Patel, Vatsal Patel, and Vikas Patel, VHDL Implementation of
UART with BIST Capability, IEEE conference on Computing,
Communications and Networking Technologies,vol.4, pp. 1450- 1454,
July 2013.
[5] Feng Liang, Luwen Zhang, Shaochong Lei, Guohe Zhang, KaileGao,
And Bin Liang, Test Patterns of Multiple SIC Vectors: Theory and
application in BIST Schemes, IEEE Transactions on Very Large Scale
Integration Systems, vol. 21, no. 4, pp. 614-623, April 2013.
[6] V. Thirunavukkarasu, V. Saminadan and R.Saravanan, Performance
Evaluation of Testing Methodologies for Digital VLSI
Circuits,International Journal of Applied Engineering research (special
issue), Volume-10, No.20, pp.18822-18825, 2015

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