Proceedings of the 11th European Microwave Integrated Circuits Conference
A Design Approach to Mitigate the Phase Distortion
in GaN MMIC Doherty Power Ampliers
Rocco Giofre, Paolo Colantonio, and Franco Giannini
Electronic Engineering Departement, University of Roma Tor Vergata, via del Politecnico 1, 00133 Roma, Italy
Email: giofr@ing.uniroma2.it
AbstractA Gallium Nitride (GaN) Monolithic Microwave
Integrated Circuit (MMIC) Doherty Power Amplier (DPA)
for 7 GHz microwave backhaul radio links is presented. The
MMIC is based on a novel design approach that allows for
a drastic reduction of the phase distortion (AM/PM) without
worsening other key features, such as efciency and gain. In the
proposed architecture, a nonlinear driver stage is introduced in
both Carrier and Peaking branches, with the aim to actualize
a phase distortion compensation mechanism directly at MMIC
level, thus heavily mitigating the linearity issues at system level.
In addition, the power consumption of the driver stages has
been minimized by adopting an uneven drain bias voltage. The
design has been carried out on a commercial 0.25 m GaN power
process, resulting in an overall chip area of 3x3mm2 . The MMIC
shows 38 dBm of saturated output power, 16 dB of gain, and less
than 3 of phase distortion at 7 GHz. The power added efciency
is higher than 47% in 7 dB of output power back off.
Index TermsGallium Nitride, Doherty Amplier, Microwave
Backhaul, phase distortion.
I. I NTRODUCTION
Wireless communication systems are growing fast aiming
to provide ubiquitous data access, with higher throughput to
an increasing number of users [1]. At digital coding level,
complex modulation schemes are considered to be the best
solution to meet the targeted requirements. On the other hand,
to optimize the system resources, this evolution has to be ac-
companied by an efcient management of the available power
and spectrum resources at each level of the network infrastruc-
ture. Consequently, the physical layer of such technologies is
typically bounded by very stringent requirements in terms of
bandwidth, efciency and linearity [2]. Due to the dominant
effect onto the performance of every Radio Frequency (RF)
transmitter, the Power Amplier (PA) represents one of the
most crucial subsystem in this challenge [3].
In this framework, the Doherty Power Amplier (DPA) is
considered to be an attractive and effective solution. Indeed,
thanks to the ability to achieve high average efciency in a
wide range of output power, it represents a valid, and widely
adopted solution to realize PAs dealing with amplitude mod-
ulated signals [4], [5]. In recent years, a lot of research effort
has been devoted to nd design guidelines and architectural
solutions to optimize and improve the performance of DPA
in terms of efciency, gain, and bandwidth [4], [5]. On the
other side, DPAs usually show worsen linearity performance as
compared to single ended PA. Besides this, the high levels of
integration required to reduce production costs, together with
the demand of increasing output power and center frequency,
978-2-87487-044-6 2016 EuMA 133
are moving the focus towards Gallium Nitride (GaN) Mono-
lithic Microwave Integrated Circuit (MMIC) DPAs. Hence,
design approaches aiming to maximize the linearity-efciency
trade-off in GaN DPAs can be of great interest.
The generation mechanisms at the base of the amplitude
(AM/AM) and phase (AM/PM) distortion in GaN DPAs have
been described in recent papers [6][9]. It was demonstrated
that the nonlinear behavior of the device trasconductance is
the main responsible of the AM/AM, while the AM/PM is
mainly related to the nonlinear variation of the transistor input
impedance. Moreover, it is also shown that, even if an almost
at behavior of the AM/AM can be achieved by properly
optimizing the bias point and the splitting factor of the DPA,
its AM/PM is always higher as compared to class AB PA [10].
The reason relies on the higher variation of the device input
impedance due to the higher, and not longer constant value
of the Miller reected input capacitance. Indeed, the latter is
directly proportional to the output load resistance of the device,
that in a DPA is modulated along the RF dynamic range.
In this contribution, the classical DPA architecture is mod-
ied by introducing a nonlinear driver stage in both Carrier
and Peaking branches, with the aim to introduce an AM/PM
distortion compensation mechanism directly at MMIC level,
thus mitigating the need of complex digital pre-distortion
algorithms, typically required to t the DPA output spectrum
within the specied limits. The MMIC GaN DPA designed as
a proof of concept shows 38 dBm of saturated output power,
16 dB of gain, and less than 3 of phase distortion at 7 GHz.
The power added efciency is higher than 47% in 7 dB of
output power back off.
II. D ESIGN S TRATEGY
The proposed DPA architecture is shown in Fig. 1. As
mentioned before, both Carrier and Peaking branches are based
on a two stages approach, in which the driver stage acts as
linearizer for the nal one. To better clarify this concept, lets
start considering the simplied equivalent circuit of a GaN
HEMT reported in Fig. 2.
The device has been modeled through a voltage controlled
current source (gm vgs ), an input resistance (Rg ) and, ac-
cording to Millers approximation [9], an input (Cin ) and an
output (Cout ) equivalent capacitance. The latter, knowing that
the low frequency voltage gain, AV = vL /vgs gm /GL ,
is much higher than unity, can be written as:
34 Oct 2016, London, UK




  

 

1


 
    vL = tan1 (Zin ) = tan1 =
2 Zin
    (5)
 1 1
    tan
RG (Cgs + Cgd + Cgd gm /GL


 The AM/PM is dened as the variation of vL along the

   RF input signal. Looking at (5), it is clear that, in xed load

PAs, such as class AB, where GL =GL,opt along the whole
  RF input signal range, the AM/PM is a function of the device
   nonlinearities (i.e., Cgs , Cds , Cgd , and gm ) only. Conversely,
Fig. 1. Proposed DPA architecture. in load modulated PAs, such as DPAs, where GL is usually
modulated from GL,opt /2 to GL,opt for the Carrier device,
and from zero to GL,opt for the Peaking one, also the output
%# % 
conductance plays a key role due to the presence of the term

#   Cgd gm /GL in (5). Therefore, the variation of Zin due to
the contribution of the output load modulation, mirrored at

 !" 
#$%#  the input through the feedback drain-gate capacitance, is the

 principal responsible of the higher AM/PM typically registered
 in a classical DPA as compared to class AB PA.

In [11] is shown that the AM/PM of a GaN PA tends to be
Fig. 2. Simplied model of a FET device. opposite to the AM/AM shape, while in [9], it is demonstrated
that the AM/PM of a DPA can be estimated by investigating
the phase distortion of the Carrier branch only. On these bases,
  and adopting the architecture reported in Fig. 1, the AM/PM
GL + g m
Cin = Cgs + Cgd (1) of a DPA can be reduced without affecting the output load
GL modulation, that is mandatory to obtain the expected efciency
 
GL + g m behavior. Indeed, the input impedance variation of the nal
Cout = Cds + Cgd (2)
gm stage, caused by the output load modulation, can be exploited
to achieve, in the driver stage, an opposite AM/PM behavior
being Cgs , Cds , and Cgd , the input, output, and feedback
as compared to the one of the nal stage, thus signicantly
device intrinsic capacitances, while GL is the output load
reducing the DPA overall phase distortion.
conductance (GL = Re(YL )). Moreover, since Cds and Cgd
show negligible nonlinearities with respect to the amplitude
III. MMIC D ESIGN
of the RF signal [11], the output capacitance can be assumed
to be almost constant and equal to Cout Cds + Cgd . The MMIC has been oriented to microwave backhaul links
This reactive contribution is typically compensated through applications. The latter are usually based on quadrature am-
the output matching network of the PA, by synthesizing a plitude modulation (QAM) schemes, having a peak-to-average
susceptance value of BL = Im(YL ) = Cout . In this way, power ratio (PAPR) of roughly 7 dB. Consequently, the DPA
and having GL = GL,opt , the power delivered by the device has been designed targeting a ``Doherty region (i.e., the
nonlinear current source (gm vgs ) is maximized, being GL,opt output power range in which the efciency is almost constant)
the output conductance value for maximum power. of the same value, while 37 dBm of saturated output power
Referring to Fig. 2, Zin is given by: were required by system specications.
Of course, the approach described in the previous section
1
Zin = RG + = has been adopted to realize both Carrier and Peaking ampli-
jCin ers. The nal layout of the DPA is reported in Fig. 3, resulting
j
RG   (3) in a chip size of 3x3 mm2 .
Cgs + Cgd + Cgd gm /GL Considering the power density of the selected process
(about 4.5 W/mm), the nal stage of both Carrier and Peaking
while the output voltage (vL ) as a function of the voltage branches has been implemented with a 8x100 m HEMTs.
applied to the device gate terminal (vG ) can be written as: The same active device has been used in the driver stages
for compactness purpose, and also to avoid an eventual early
gm 1 saturation due to the lower and lower value of Gout,CD along
vL = vG (4)
GL jCin Zin the RF dynamic range. Nevertheless, the efciency of the
Consequently, it is straightforward to evaluate the phase of overall DPA has been maximized by reducing the drain bias
the output voltage resulting in: voltage for the driver stage, as compared to the nal ones.

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 Fig. 4. Scattering parameters of the designed GaN MMIC DPA.

Fig. 3. Layout of the designed GaN MMIC DPA.

The unconditional stability at all frequencies of the

8x100 m device has been achieved by adding a resistive-
capacitive network in series to the gate. The values of such
elements have been selected in order to minimize the losses in
the operating band and, thus, maximizing the achievable gain.
The output combiner network is highlighted with an orange
box in Fig. 3. As can be noted, the output /4 between Carrier
and Peaking has been implemented through a semi-lumped
capacitor-inductance-capacitor network, while the contribution
of the output capacitor Cout of the active devices has been
compensated by optimizing the length of the bias lines.
The uneven input splitter is highlighted with a blue box in
Fig. 3. It has to guarantee the uneven splitting factor between
Carrier and Peaking branches in the whole bandwidth. Even
if a distributed solution allows to achieve better performance,
Fig. 5. Expected large signal performance of the designed DPA.
in this project, in order to fulll the 3x3 mm2 requirement for
the occupied area, a lumped solution (shunt capacitor, series
inductance and shunt capacitor) has been preferred. Moreover,
the input capacitors (Cin ) of the active devices have been Expected large signal performance at 7 GHz is shown in
absorbed in the network, leading to a very compact solution. Fig. 5. The saturated output power is larger than 38 dBm. The
Finally, the design has been completed by adding a low pass peak of power added efciency (PAE) is about 50% and it is
lter in each access point of the dc bias voltage. obtained at less than 1 dB of gain compression. Moreover, in
IV. R ESULTS the 7 dB of output power back-off, the PAE remains almost
constant with a minimum value of 47%.
The simulated scattering parameters of the designed DPA
are reported in Fig. 4. The comparison between the AM/PM of the overall DPA
At 7 GHz the small-signal gain is higher than 17.5 dB and the one of the Carrier nal stage alone is shown in Fig. 6.
and the input return losses is better than 13 dB. More- As can be noted, thanks to the introduction of the nonlinear
over, the small-signal gain is higher than 16.6 dB in driver stage, the AM/PM of the DPA has been limited to less
the 6.6-7.4 GHz frequency range (yellow box in the g- than 3, with respect to the expected 10 from the nal stage
ure), resulting in more than 10% of fractional band- alone.
width at 1 dB of gain ripple. Simulations refer to the A comparison between the expected performance of the
nominal bias point given by: VDD,CF = VDD,P F =28 V, presented DPA with recently published GaN MMIC DPAs is
VDD,CD = VDD,P D =10 V, VGG,CF = VGG,CD =-2.9 V, and reported in Table I. The improvement with respect to the actual
VGG,P D = -4.1 V & VGG,P F = -3.8 V. state-of-the-art, especially in terms of AM/PM, is appreciable.

135
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V. C ONCLUSION
A novel design approach to drastically reduce the phase
distortion in DPAs without worsening other key features, such
as efciency and gain, has been presented. The proposed
architecture has been adopted to design a GaN MMIC DPA
for 7 GHz microwave backhaul radio links applications. The
MMIC, realized in 0.25 m channel length GaN process from
TriQuint foundry, has shown 38 dBm of saturated output
power, 16 dB of gain, and less than 3 of phase distortion at
7 GHz. The power added efciency is higher than 47% in 7 dB
of output power back off. The overall chip area is 3x3mm2 .
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