DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

Ri
L0

Step-by-Step Design
VS C0 RO VO
Guide for Digital Peak Slope
Comp
PWM

Current Mode Control: A Comparator PWM

C1
C3

R2
C2 R3

Single-Chip Solution R1

Dr. Ali Shirsavar Error Amp

VREF
Rb

1. Abstract
Figure 1. Analog Peak Current Mode Buck
This application note investigates the Converter
implementation of peak current mode control with
slope compensation using an single Ri
L0
TMS320F28027 (Piccolo A) MCU from Texas
Instruments. This MCU is ideal for peak current VS PWM C0 RO VO
mode implementation due to its dedicated internal
circuitry which enables a fully digital slope
compensation scheme. The theory of operation,
mathematical modeling and all relevant equations PWM
Comparator Blanking C-by-C Trip
are presented along with a detailed step-by-step D=100%
R1
design procedure in both analog and digital DAC
domains. + 2p2z
- K + ADC
Controller -
Rb
A design example and associated experimental Slope Compensation REF
Piccolo A
results are also presented with two methods of
implementation; one using TIs ControlSUITE Figure 2. Digital Peak Current Mode Buck
and one using Birichas Chip Support Library Converter
(CSL).
TIs ControlSUITE whilst the second method
Further information with regards to the CSL and uses Birichas Chip Support Library (CSL).
digital power design workshops can be found at
www.biricha.com/workshops/ The Biricha Digital Chip Support Library provides
a fast and simple method of configuring Texas
2. Introduction Instruments C2000 MCUs for use in digital power
applications. In-depth knowledge of the MCUs
The operation of a digital peak current mode internal registers and associated configuration
converter is similar to its analog counterpart as bits are not required; in place of this, simple
shown in Figure 1. However, the compensation function calls are used.
network, error amplifier, slope compensation and
PWM generator are all replaced by a single The Biricha Digital CSL documentation contains
microprocessor in the digital converter shown in full descriptions and examples of all of the
Figure 2. This application note describes the functions used in the implementation presented
processes involved in setting up a Piccolo MCU here. The user guides and an evaluation copy of
for use within a digital peak current mode power CSL can be downloaded from
supply. www.biricha.com/resources/

A complete design example and two complete Referring to Figure 2, the operation of the peak
implementations are given; the first method uses current mode controlled power supply is as
follows. Initially, the duty is set to 100% and the

October 2012 BAN105 Page 1

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution
PWM is driven high. The output voltage of the
converter is applied to a sampling divider network
which is connected to the Piccolos ADC. The
voltage is sampled and converted to a digital
value. A digital reference (REF) is subtracted from
the digital value and the resulting error value is
used as an input to the digital controller (2p2z
Controller). This represents the error amplifier and
compensation network of the analog equivalent. A
full design procedure for this controller will be
given later on in this paper.
The output of the controller is then multiplied by a
gain term K. This gain scales the output of the
controller to a digital value that is suitable for use
with the DAC of the comparator module,
counteracting the effects of the various gains
within the closed loop system. The value of this
gain term can be calculated to obtain the correct
crossover frequency; details are given in the
design example.
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October 2012 BAN105
This scaled output is then used as an input to the
DAC connected to the comparators inverting
input. The non-inverting input is connected to the
current sense transformer; the gain of this is
represented by the Ri block. The current spike
associated with turning the MOSFET switch on is
ignored through the use of leading edge blanking
within the Piccolos blanking block. The output of
the comparator will change state when the
inductor current reaches the level of the voltage
on the DAC output. This causes a cycle-by-cycle
trip event to occur within the digital compare sub-
module of the PWM module. The PWM signal will
be low for the remainder of the switching period.
Therefore, as with the analog equivalent, the duty
is determined by the peak of the inductor current
in the power stage of the converter. The digital
implementation of peak current mode control
achieves the desirable cycle-by-cycle peak
current limiting effect of the analog equivalent.
Full experimental results will be given shortly.
Page 2
 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

3. Peak Current Mode Model
The Buck converter in Figure 3 is used to
describe the peak current mode model used in
this application note. However the same
procedure can be applied to other topologies.
L0
VO
damped this resonant peak and reduces the gain
at FS 2 .
For a Buck converter, the required peak-to-peak
value of the external compensation ramp has
been calculated in [2] and is given in Equation (2).
This compensating ramp reduces the Q of the
high frequency transfer function to 1.

VPP =
(0.18 D )RiTSVIN
VS C0 RO
PWM L0
(2)

Where:
Figure 3. A typical Buck converter Current-sense transformer gain: Ri
In order to design a stable compensator, we first
need a mathematical model of the Buck converter Switching period: TS
plant. According to [3], this can be described by
three terms: Input voltage: VIN

1. FH (s ) , a high frequency transfer function. Output inductor: L0

2. H DC , a DC gain. The duty, D , is:

3. H B (s ) , a power stage small signal model. VO

D=
V IN
The complete control-to-output transfer function
for a Buck converter under peak current mode Where VO is the output voltage.
control, as described in [1], is a combination of
these three terms: With Q set to 1 FH (s ) simplifies to that given in
Equation (3).
V (s )
H CO (s ) = OUT = FH (s ) H B (s ) H DC
VERR (s ) 1
FH (s ) =
(1) s s2
1+ +
N N2
High Frequency Transfer Function
(3)
The high frequency transfer function, FH (s ) , has
a double pole at half the switching frequency, Where:
FS 2 . Inevitably this will result in a resonant peak
1
occurring at this frequency. Therefore this peak N = FS in rad / s i.e. Fs in Hz
2
needs to be damped in order to avoid the gain
Bode plot crossing the 0dB axis at resonance and
causing instability.

A compensating ramp is added to the system to

effectively damp resonant peak; this called slope
compensation. This is achieved by setting the Q
of this double pole system to 1. A low Q forces a

October 2012 BAN105 Page 3

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

DC Gain margin of the closed loop system. A Type II

compensator is used to control the Buck
Using Ridleys model in [1] and critically damping converter under peak current mode. The transfer
the resonance peak by setting its Q to 1, the DC function of a Type II compensation network is:
gain of the system simplifies to:
s
R 1 1 +
H DC = O CP 0 CZ 1
Ri 1 + ROTS H c (s ) =
s s
L0 1 +
CP1
Where the load resistance is RO . (7)

Power Stage Small Signal Model The pole, CP1 , of the compensator is set to the
With current mode control, the inductor of the frequency of the ESR zero in the control-to-output
Buck converter in Figure 3 becomes a current transfer function in order to approximately cancel
controlled source. In [3] the small-signal model of out its effects.
the Buck power stage is given as:
1
CP1 =
s RESRC0
1+
ESR (8)
H B (s ) =
s
1+ The zero, CZ 1 , is set to achieve a suitable
OP
phase margin and the pole at origin, CP 0 , is set
(4)
to achieve the desired crossover frequency. The
The pole, OP , is formed from the output frequency of the compensator zero should be set
capacitance and load resistance. With Q set to 1, to 20% of the required crossover frequency.
this pole can be calculated in Equation (5). Under most circumstances this will give a
reasonable phase margin.
1 TS
OP = + 1
R0C0 L0C0 CZ 1 = 2 f X
(5) 5
(9)
Furthermore, the zero, ESR , formed from the
Where f X is the crossover frequency in Hertz.
output capacitance and its equivalent series
resistance is: Finally, the pole at origin (or gain of the
compensator) is calculated. This is the frequency
1 at which the gain solely due to the pole at origin
ESR =
RESR C0 would be unity. This value sets the desired
(6) crossover frequency, f X . After analyzing the
Please note that these are in rad/s and not Hz. Buck converters control-to-output transfer
function, Equation (10) has been derived for
4. Compensator Poles and directly calculating CP 0 of the compensator [2].

Zeros 1.23 f X Ri (L0 + 0.32R0T ) R1 R2

CP 0 =
The poles and zeros of the compensation network L0 R0
can now be placed according to the analysis of (10)
the control-to-output transfer function in order to
set the desired crossover frequency and phase

October 2012 BAN105 Page 4

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

Where: 2 z 1
s
TS z + 1
2
R1 = 1 4 f X Ts2 + 16 f X4Ts4 (11)

Where TS is the sampling period which is equal

39.48C02 f X2 L20 R02
R2 = 1 + to the switching period. Equation (11) is then
(L0 + 0.32 R0 Ts )2
substituted in to the Type II controller transfer
function given in (7). The result is given in (12).
Please note that these values are calculated in
rad/s and not Hz.
2 z 1
A complete design example using these TS z + 1
1+
equations will be given later in this application CP 0 CZ1
note. H C [z ] =
2 z 1 2 z 1
Please be aware that in this application note only TS z + 1 TS z + 1
1+
an approximate solution is given. Both the zero CP1
and pole at the origin can be calculated (12)
analytically and full details of the analytical
method is taught in the Biricha Digital workshops. After simplification, the two-pole two-zero discrete
controller transfer function is found:
See www.biricha.com/workshops/ for more
information. Y [z ] B2 z 2 + B1 z 1 + B0
H C [z ] = =
X [z ] A2 z 2 A1 z 1 + 1
5. Digital Controller Design (13)

The poles and zeros of the analog compensation Where:

network have been calculated based on the
model given in Section 3. These poles and zeros
B0 =
(T s CP1 (2 + Ts CZ1 ))
CP 0
must be converted in to the digital domain. This (2(2 + TsCP1 )CZ1 )
involves converting from the continuous time s-
domain to the discrete time z-domain. There are
various methods to achieve this. The Bilinear or B1 =
(T s
2
CP1 )
CP 0

Tustin transform is a relatively simple and (2 + TsCP1 )

effective method.
B2 =
(T
s CP1 ( 2 + TsCZ1 ))
CP 0
There is no need for this transform to be (2(2 + TsCP1 )CZ 1 )
calculated by hand as an automated tool exists
on the Biricha Digital website to convert from s- 4
domain poles and zeros to the coefficients A1 =
required by the discrete time digital controller.
(2 + Ts CP1 )
Please visit www.biricha.com/resources/ to
A2 =
( 2 + T ) s CP1
access these tools free of charge. (2 + T ) s CP1

However, the process is described in detail here

Equation (13) can now be rearranged to find the
for completeness. The transfer function of a Type
linear difference equation (LDE):
II compensation network can be converted in to
the z-domain by replacing the s terms with the
y[n] = B2 x[n 2] + B1 x[n 1] + B0 x[n]
approximation:
+ A2 y[n 2] + A1 y[n 1]
(14)

October 2012 BAN105 Page 5

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

Where x[n] is the error input to the controller for
this sampling period and y[n] is the controller
output for this sampling period. [n 1] denotes
the pervious sampling period and [n 2] is two
sampling periods in the past.
The coefficients of the discrete time controller are
used with this linear difference equation.
Please note that it is now possible to calculate all
of these controller coefficients analytically as all
the variables within the coefficients are known;
we will give a design example shortly.
damped by setting the Q to 1 through calculating
the compensation ramp in Equation (2). Now we
will discuss the digital implementation of this
compensation ramp.
The Piccolo range of MCUs from TI are ideally
suited for this purpose due to the presence of
dedicated ramp generating modules.
The DAC module of the Piccolo includes a ramp
sub-module which is used to implement slope
compensation. This slope compensation method
uses a digital staircase to remove the
subharmonic oscillations [6].

V DACn-1(.t)
6. Digital Slope Compensation RAMPMAX

DECVAL
As mentioned earlier, sufficient ramp needs to be
added such that no subharmonic oscillations
occur; this is called slope compensation. The I(L0)
oscillations are caused by the current feedback
loop which has a double pole in the high ts

frequency term, FH (s ) , in the control-to-output Dn-1.TS Dn-1.TS Dn-1.TS Dn-1.TS t

transfer function. The resonant peak of the double Figure 4. Slope compensation using a digital
pole (at half the switching frequency) was staircase

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October 2012 BAN105 Page 6

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution
In Figure 4, the DAC is initially loaded with the
output of the controller after being scaled by K.
This sets the initial value of our demand current
reference signal before slope compensation. The
sensed current is compared to this reference
current. The counter sub-module then
decrements the DAC by a set value at each
system clock tick. This generates a negative ramp
on the current reference signal, just as slope
compensation would in analog, and effectively
damps the oscillations.
The required compensation ramp height must first
be converted to a digital value using the gain of
the DAC:
2 DACBITS 1
DigitalRampHeight = V PP 64
V DAC
(15)
The value to be decremented at each system
clock tick can therefore be found using the digital
ramp height, switching frequency and system
clock frequency:
DigitalRampHeight FS
DecVal =
FCLK
(16)
If using the CotnrolSuite these equations can be
used to set up the correct values in the relevant
registers; please see the appendix. However, if
using the CSL dedicated CSL functions can be
called within the initialization in order to
automatically set these values
A selection of Biricha CSL functions needed for
slope compensation are described below. Further
practical examples as well as hands-on exercises
are provided during the workshops run by Biricha.
The ramp sub-module is first configured using the
function CMP_rampConfig(). This connects the
specified ramp sub-module with a PWM module.
The PWM module synchronization pulse is used
to reset the ramp back to the initial value at the
beginning of every period.
CMP_rampConfig( CMP_MOD_2,
PWM_MOD_1 );
October 2012
The value DECVAL is decremented from the DAC
at each system clock tick. This value is set using
CMP_setRampDec() after the ramp module has
been configured. The peak-to-peak value of the
analog compensation ramp was calculated in (2).
The Biricha CSL function CMP_calcRampDec()
takes this analog voltage value and returns the
correct digital decrement value.
This function requires the digital equivalent of the
ramp height along with the period of the PWM
output. The digital equivalent of the ramp height is
calculated using CMP_mVtoRampValue(). For
example, if a 1500mV ramp is required to
compensate a 200kHz PWM output the following
functions would be called during initialization:
period = PWM_freqToTicks(200000);
decval = CMP_calcRampDec(
CMP_mVtoRampValue(1500),
period );
CMP_setRampDec( CMP_MOD_2, decval );
The controller output, or reference current, is set
as the initial value of the ramp at the beginning of
the period using the function
CMP_setRampMax(). This is called in the ADC
interrupt routine after the controller output has
been calculated.
7. Leading Edge Blanking
Sensed Current
420ns 420ns
0
Ts = 1/fs
Figure 5. The required amount of leading edge
blanking
The sensed inductor current signal contains
switching noise. During turn on there is a large
spike which would potentially cause the
comparator to trigger and a trip event to occur. To
prevent this, a leading edge blanking block is
provided within the Piccolos comparator module.
For a specified window period the comparators
BAN105 Page 7
 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

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output is ignored by the digital compare sub- PWM module to use the output of the comparator
module within the Piccolo. as an event trigger.

The designer must specify the number of

nanoseconds required for the duration of the
8. Design Example
blanking window. This can either be set using the In this example a 12V to 3.3V digital peak current
TIs ControlSUITE or by calling CLSs mode Buck converter is designed, however, the
PWM_setBlankingWindow() function. An design principles used here can be applied to
initial value should be set and its suitability can be most other topologies with slight modifications.
confirmed using an oscilloscope. In the example
The converter specification is as follows:
shown in Figure 5 a window of 420ns is shown.
This can be set up using the functions described Parameter Value
below. VIN 12V
VO 3.3V
PWM_configBlanking( PWM_MOD_1, IO 2A
PWM_CMP_COMP2, RL 1.65
GPIO_NON_INVERT,
L0 22H
true );
C0 440F
PWM_setBlankingWindow( PWM_MOD_1, RESR 31m
PWM_nsToTicks(420) ); Ri 0.48
D 0.275
The PWM_configBlanking() function fs 200kHz
configures the digital compare sub-module of the fx 10kHz

October 2012 BAN105 Page 8

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

The switching frequency is chosen as CP 0 = 162464 rads 1

f S = 200 kHz and the desired crossover
frequency is f X = 10 kHz . (= 25,857Hz )

Step 1: Calculate the size of the

compensating ramp
Calculate the peak-to-peak value of the external
compensation ramp required to achieve Qc = 1
using Equation (2):
Figure 6 shows the frequency response of the
plant (i.e. control-to-output transfer function). This
clearly shows the double-pole at half the
switching frequency. The choice of compensation
ramp has effectively damped the resonant peak

VPP =
(0.18 D )RiTSVIN of this double pole.
L0 10
Simulated Plant
5

VPP =
(0.18 0.275) 0.48 5s 12 0

22H -5

Gain (dB)
-10
VPP = 0.124V -15
(17)
-20

-25
Step 2: Calculate the positions the poles
-30
and zeros of our analog compensator 10
2
10
3
10
4
10
5

In the case of our Buck converter a Type II

compensator is used. The transfer function is
0
given in (7). The pole, CP1 , is used to cancel out
-20
the ESR zero of the output capacitor and -40
equivalent series resistance: -60
Phase (degrees)

-80
CP1 = ESR -100

-120
CP1 = 73314 rads 1 -140

-160

(= 11,668Hz ) -180
10
2
10
3
10
4
10
5

Frequency (Hz)

The zero of the compensator is used to set the

phase margin of the open loop system at the
crossover frequency. An approximate solution
which gives reasonable results is to set the zero
to one fifth of the crossover frequency.
CZ 1 = 12566 rads 1
(= 2,000Hz )
Finally, the pole at the origin (or gain of the
compensator) is calculated to achieve the desired
crossover frequency using Equation (10):
Figure 6. Bode plot of the plant (control-to-output
transfer function)
The frequency response of the compensator is
represented by the dotted trace in Figure 7 whilst
the solid trace on this plot represents the
combined plant and controller transfer function;
this is the open loop frequency response of our
system. The gain and phase margins of our
system and hence its relative stability are
determined from this trace.
The controller has been designed to achieve
large phase margin at the crossover frequency of

October 2012 BAN105 Page 9

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

10kHz. The Bode diagram of the open loop cz1

system indicates that the poles and zeros of the Frequency of first zero: f cz1 = = 2000Hz
2
controller achieve a phase margin of 74.5 at the
crossover frequency. Switching frequency: f s = 200kHz
60
Controller The result is automatically calculated as:
40 Open-loop
U [z ] B2 z 2 + B1 z 1 + B0
H [z ] = =
Gain (dB)

20
E [z ] A2 z 2 A1 z 1 + 1
0 (18)
-20
Where:
-40
10
2 3
10 10
4
10
5
A1 = 1.6902106568
A2 = -0.6902106568
0
B0 = 2.0654678327
B1 = 0.1258242849
-50
Phase (degrees)

B2 = -1.9396435478

-100 These are the coefficients that the designer

should use with the two-pole two-zero controller
-150 equation. The CSL of course provides a
dedicated function of this type of controller.
2 3 4 5
10 10 10 10
Frequency (Hz) Step 4: Initialize the controller
When using either the Biricha CSL or
Figure 7. Bode plots of Controller and Open-loop
controlSUITE the digital current mode controller
system (GM = 20.1dB, PM=74.5)
parameters are entered at the top of the C file
Step 3: Convert the analog compensator using #define statements.
to digital A reference is used to calculate the digital error
In the previous step we designed an analog value by subtracting the ADC output from the
compensator to stabilize our power supply. We reference. The digital error value is then used as
now convert this into its digital equivalent. an input to the controller. Therefore the reference
value must be equal to the digital equivalent of
We use the bilinear transform for this purpose
the output voltage multiplied by the sampling
using the automated tool available at
divider gain.
www.biricha.com/resources/.
RB 2 ADC BITS 1
REF = VO
R1 + R B V ADC
The following information is entered into the (19)
online form:
For the 3.3V output, with a sampling divider gain
Crossover frequency of analog pole at zero: of 0.5 and 12 bit ADC:
cp 0
f cp 0 = = 25857Hz 4095
2 REF = 3.3 0.5
3 .3
cp1 REF = 2048
Frequency of second pole: f cp1 = = 11668Hz (20)
2

October 2012 BAN105 Page 10

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

The 2p2z controller can now be configured by Start

defining the following constants at the top of the
main C file.

/* Set up the coefficients for the Initialization

2p2z controller */
No
#define REF (_IQ15toF(2048))
#define MIN_DUTY 0
#define MAX_DUTY 65535 Interrupts to
#define A1 +1.6902106568 service?
#define A2 -0.6902106568
#define B0 +2.0654678327
#define B1 +0.1258242849
Yes
#define B2 -1.9396435478
#define PERIOD_NS 5000 /* Period in
ns for fs = 200kHz */ Service interrupt

The final term to be calculated is that of the

scaling factor K. This is used to negate the effects
Figure 8. Main function program flow
of the gains within the microcontroller and thus
achieve the correct crossover frequency. The Initialization
value of K can be calculated accurately; however
this is beyond the scope of this text and is
discussed in detail in Birichas digital power Initialize system
design workshops.

For the purpose of this application note we start PWM B falling

with an initial value of K of say 10, implement the Configure PWM triggers start of
ADC conversion
software and then measure the loop using a Bode
100 network analyzer from OMICRON Lab. K is
then adjusted in software to achieve the correct
cross over frequency. In Section 9 we describe End of conversion
how the code is implemented, we measure the Configure ADC triggers ADC
loop and adjust K for a perfect cross over. interrupt (IsrAdc)

9. Real Life Implementation

Figure 8, Figure 9 and Figure 10 represent the Configure 2p2z
flowcharts for our system. Both ControlSUITE controller
and CSL implementations follow the same
software structure and hence the flowcharts are
Configure
valid for both. Complete listings for both comparator
implementations are given in the appendix.

Configure slope
compensation

Return

Figure 9. Main function initialization routine

October 2012 BAN105 Page 11

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

/* Setup PWM_MOD_1 for fs = 200kHz.

IsrAdc
PWM1 Ch A is used for switching
* the MOSFET.
*/
Acknowledge ADC PWM_config( PWM_MOD_1,
interrupt
PWM_nsToTicks(PERIOD_NS),
PWM_COUNT_UP );
PWM_pin( PWM_MOD_1, PWM_CH_A,
Read ADC GPIO_NON_INVERT );
PWM_pin( PWM_MOD_1, PWM_CH_B,
GPIO_NON_INVERT );

Execute 2p2z /* Set the maximum duty to 100%. The

controller trip zones (configured later)
* will end the high output of the
PWM when the current reaches
Set max ramp * the slope level.
height of DAC */
PWM_setDutyA( PWM_MOD_1,
PWM_nsToTicks(PERIOD_NS) );
Return
/* Sets the PWM1 Ch B such that the
calculations are complete
Figure 10. ADC and CLA interrupts * just before the rising edge PWM A.
*/
An analysis of the code within the main() function PWM_setDutyB( PWM_MOD_1,
PWM_nsToTicks( PERIOD_NS-2450+0 ) );
will now be presented. First of all, the system and
peripherals must be initialized before they can be /* This sets up the PWM Mod1 to start
used. the ADC conversion whenever
* PWM1 Channel B timebase counter
/* Initialize the MCU and ADC */ matches Ch Bs duty.
SYS_init(); */
ADC_init(); PWM_setAdcSoc( PWM_MOD_1, PWM_CH_B,
PWM_INT_CMPB_UP );
The PWM module is configured to operate at the
switching frequency of 200kHz. Channel A is /* This sets up PWM Mod1 to generate
connected to the MOSFET Driver IC and controls an interrupt every PWM
the switching of the MOSFET in the Buck power * cycle whenever timebase counter =
0.
stage.
*/
PWM_setCallback( PWM_MOD_1, 0,
The duty of channel A is set to 100% duty as with PWM_INT_ZERO, PWM_INT_PRD_1 );
peak current mode control the effective duty is
determined when the current through the switch The following functions set up the cycle-by-cycle
reaches the output of the controller. At this point trip of the PWM output triggered by the
the PWM signal goes low and the MOSFET turns comparator output. The
off. PWM_configBlanking() function effectively
connects the comparator output to the PWM
The counter register resetting to zero is used to module using the digital compare sub-module.
trigger the sampling and conversion of the output The blanking window size is set within the digital
voltage. At the end of conversion an ADC compare sub-module and the digital compare
interrupt is automatically triggered and the 2p2z event is used for the trip zones configured within
algorithm is executed. PWM module.
The initialization code within the main() /* This effectively feeds the output
function is discussed below. of comparator Mod2 into
* PWM Mod1 and activates the
blanking by setting the digital

October 2012 BAN105 Page 12

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution
* compare event PWM_DCEVT at the
correct time.
*/
PWM_configBlanking( PWM_MOD_1,
PWM_CMP_COMP2, GPIO_NON_INVERT,
true );
/* Sets the size of the blanking
window to 420ns */
PWM_setBlankingWindow( PWM_MOD_1,
PWM_nsToTicks(420) );
/* Sets the relevant trip zones: i.e.
when PWM_DCEVT occurs clear
* PWM1 Ch A on a cycle by cycle
basis but takes no action on
* PWM1 Ch B
*/
PWM_setTripZone( PWM_MOD_1,
PWM_DCEVT, PWM_TPZ_CYCLE_BY_CYCLE );
PWM_setTripState( PWM_MOD_1,
PWM_CH_A, GPIO_CLR );
PWM_setTripState( PWM_MOD_1,
PWM_CH_B, GPIO_NO_ACTION );
The ADC Module 1 is configured to read and
convert the output voltage from Channel B2. The
conversion is triggered from the start of
conversion event of PWM module 1. When the
conversion is complete an interrupt is called and
the interrupt service routine IsrAdc()is entered.
This interrupt service routine is included in the
appendix.
/* Configures ADC to sample Vo when
triggered by PWM1 Ch B's
* falling edge
*/
ADC_config( ADC_MOD_1,
ADC_SH_WIDTH_7, ADC_CH_B2,
ADC_TRIG_EPWM1_SOCB );
/* When conversion is finished, cause
interrupt and jump to IsrAdc
*/
ADC_setCallback( ADC_MOD_1, IsrAdc,
ADC_INT_1 );
The control structure is initialized with the values
determined from the bilinear transform of the
compensator transfer function. A soft start can
also be configured.
/* Initalise the 2p2z control
structure */
CNTRL_2p2zInit(&MyCntrl
,_IQ15(REF)
,_IQ26(A1),_IQ26(A2)
October 2012
,_IQ26(B0),_IQ26(B1),_IQ26(B2)
,_IQ23(K),MIN_DUTY,MAX_DUTY
);
/* Set up a 500ms soft-start */
CNTRL_2p2zSoftStartConfig(&MyCntrl,
500, PERIOD_NS );
The comparator is configured in asynchronous
mode with a non-inverted output. The inverting
input of the comparator is tied to the internal
DAC. The DAC value is set by the control
algorithm.
/* Configures the comparator Mod2 */
CMP_config( CMP_MOD_2, CMP_ASYNC,
GPIO_NON_INVERT, CMP_DAC );
Slope compensation is achieved using the ramp
sub-module of the comparator. First, the sub-
module must be synchronized with the PWM
period using CMP_rampConfig(). The required
ramp height must be converted to a digital value
before being passed as an argument to
CMP_setRampDec().
CMP_rampConfig( CMP_MOD_2, PWM_MOD_1
);
decval = CMP_calcRampDec(
CMP_mVtoRampValue(124),
PWM_freqToTicks(200000) );
CMP_setRampDec( CMP_MOD_2, decval );
Global interrupts must be enabled before any of
the interrupts can be serviced. After this, the
execution waits in an idle loop as all of the events
will now occur using interrupts.
/* Enables global interrupts and wait
in idle loop */
INT_enableGlobal(true);
while(1) {}
The complete code listing, including the interrupt
functions, can be found in the appendix.
The code entry is now complete. The final value
to be determined is that of the gain term, K ,
which determines the correct crossover. This
scales the output of the controller to a digital
value that is suitable for use with the DAC of the
comparator module and negates the effects of the
gains within the system. Initially this scaling factor
BAN105 Page 13
 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

was set to 10. The most effective way to 1

determine the correct scaling factor is to measure
K = K INIT dB
20
10
the frequency response of the complete system (21)
using a network analyzer.
In this case, at the required crossover frequency
The Bode 100 Vector Network Analyzer from of 10kHz, the magnitude response of the open
OMICRON Lab is used to measure the frequency loop system is recorded as -12.47dB. Therefore,
response of the converter by injecting a small- for this system, K is calculated in (22).
signal perturbation on to the output voltage and
measuring the response of the system. 1
K = 10 12.47
= 42.0243
20
The code is compiled and downloaded to the 10
microcontroller. The working converter is (22)
connected to the Bode 100 by means of a small 60
injection resistor (9.1) in the output voltage Simulated Loop Gain
40 Measured Loop Gain (K=42.0243)
feedback path to the ADC of the microcontroller.

Gain (dB)
20
60
Simulated Loop Gain
0
40 Measured Loop Gain (K=10)

-20
Gain (dB)

20

-40
0 2 3 4 5
10 10 10 10

-20

0
-40
2 3 4 5 Simulated phase @ 10khz: 74.3
10 10 10 10
Measured phase @ 10khz: 70.5
-50
Phase (degrees)

0
-100

-50
Phase (degrees)

-150

-100 2 3 4 5
10 10 10 10
Frequency (Hz)
-150
Figure 12. Frequency response of open loop
10
2 3
10
4
10 10
5 system. Measured using Bode 100 from OMICRON
Frequency (Hz) Lab

Figure 11. Frequency response of open loop The code is updated with the new calculated
system. Measured using Bode 100 from OMICRON value for K . After recompiling and updating the
Lab
microcontroller the frequency response sweep is
performed again to confirm the correct crossover
The correct value for K can be determined from frequency. The result in Figure 12 shows a
the frequency response data shown in Figure 11 crossover of 10kHz with 70.5 degrees of phase
as follows. Record the gain, in decibels, at the margin. The system is stable and has a fast
desired crossover frequency. Using (21) the transient response.
required value of K can be calculated using the An accurate analytical method for calculating the
initial value for K , K INIT . scaling gain K is taught in the workshops
presented by Biricha Digital. Visit

October 2012 BAN105 Page 14

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

www.biricha.com/workshops/ for more to perform other tasks such as predicting possible

information. failures.

In Figure 12 the simulated open loop model
(dashed line) is compared with the measured
results (solid line). The low frequency
discontinuities are to be expected.
The top magnitude plot of Figure 12 shows a
particular characteristic of digital converters that is
apparent at low frequencies. The gain is less than
the simulated model. This is due to a combination
of the quantization effects of the ADC and the
precision of the fixed point arithmetic. This result
draws parallels to the gain-bandwidth-product
limitation of analog operational amplifiers and a
similar result also found in the analog domain [6].
The lower phase plot of Figure 12 shows good
agreement with the predicted model around the
crossover frequency. Phase roll-off becomes
apparent as the perturbation frequency
approaches the switching frequency. At lower
frequencies the quantization and fixed point
arithmetic again mask the effects of the pole at
origin.
This application note has explained one possible
implementation of a digital power supply. Further
applications of digital power are explored from a
hardware designers perspective in the Digital
Power Workshops available from Biricha Digital.
Visit www.biricha.com for more information.
References
[1] Ridley, R.B., A new, continuous-time model for
current-mode control [power convertors], Power
Electronics, IEEE Transactions on (1991), pp.
271-280
[2] Biricha Digital Power Ltd. Digital Power Multi-
Day Workshop (2010), pp. 168
[3] Ridley, R.B., A New Small-Signal Model for
Current-Mode Control, Virginia Polytechnic
Institute and State University, PhD. Thesis (1990)
[4] Cooke, P., Modeling average current mode
control [of power convertors] (2000), pp. 256-262
vol.1

Overall the measured results show a good [5] Tang, W. and Lee, F.C. and Ridley, R.B.,
correlation to the results of the model. The Small-signal modeling of average current-mode
measured open loop gain crosses the 0dB axis at control (1992), pp. 747-755
the desired crossover frequency with
[6] Hallworth, M. and Shirsavar, S.A.,
approximately 70.5 of phase margin and a 10dB
Microcontroller Based Peak Current Mode Control
gain margin.
Using Digital Slope Compensation, Power
Electronics, IEEE Transactions on (2012)
10. Conclusion
This application note has described a method for
designing a digital peak current mode power
supply. An example of a Buck converter is used
to illustrate this process. The measured small-
signal frequency response of the digital power
supply matches with the predicted response from
the current mode model.

The digital power supply offers advantages over

the analog equivalent. This is a software solution
which can easily be modified to meet end user
requirements. One Piccolo can be used to control
multiple power supplies and advanced or non-
linear control methods are possible. The designer
can use the remaining microprocessor bandwidth

October 2012 BAN105 Page 15

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

Appendix A - TI controlSUITE Implementation

/******************************************************************************
* (c) Copyright 2011 Biricha Digital Power Limited
* FILE : main.c
* AUTHOR : Dr A. Shirsavar / Dr C. Hossack
* PROJECT : Piccolo A DPCM
* Target System : DSP C2802x
* CREATION DATE : 24/11/2011
* COPYRIGHT : Copyright Biricha Digital Power Limited 2011
* All rights reserved. Reproduction in whole or part is
* prohibited without written consent of the copyright
* owner.
* DESCRIPTION :
*
* This project demonstrates Peak Current Mode Control of BDP-105 Buck board
* using the Piccolo A microcontroller from Texas Instruments using TI
* controlSUITE files.
*
* The processor runs a 2p2z controller and performs slope compensation to
* remove subharmonic oscillations. The Piccolo's comparator 2 is being used
* to detect when the peak current reaches its demand value.
*
* IMPORTANT:
* Current sense pin connects to A4 - comparator 2 non-inverting input.
* Output voltage sense pin connects to B2.
*
******************************************************************************/

/****************************** INCLUDES SECTION *****************************/

typedef unsigned int Uint16;
typedef unsigned long Uint32;
#include "DSP2802x_Comp.h"
#include "DSP2802x_EPwm.h"
#include "DSP28x_Project.h"
#include "IQmathLib.h"

/**************************** DECLARATIONS SECTION ***************************/

/* These set up the coefficients for our 2p2z controller for a Buck
* Converter with a 200kHz switching frequency and a crossover of 10kHz
*/

#define period 300 /* 200kHz when PLL is set to 0xC (60MHz) */

#define slopeval 8 /* Required slope compensation */
#define K (42.0243)
#define REF (_IQ15toF(2048))
#define MIN_DUTY 0
#define MAX_DUTY 65535
#define A1 +1.6902106568
#define A2 -0.6902106568
#define B0 +2.0654678327
#define B1 +0.1258242849
#define B2 -1.9396435478

// Define iq31 type

typedef long _iq31;
typedef union CNTRL_ARG CNTRL_ARG;
typedef struct CNTRL_2p2zData CNTRL_2p2zData;

// Access to int and IQ

union CNTRL_ARG

October 2012 BAN105 Page 16

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

{
_iq15 m_IQ;
int m_Int;
};

// Controller
struct CNTRL_2p2zData
{
CNTRL_ARG Ref; /* +0 This is a range of +1 */
CNTRL_ARG Fdbk; /* +2 This is a range of +1 */
CNTRL_ARG Out; /* +4 This is a range of +1 */
long temp; /* +6 */
_iq24 m_U1; /* +8 */
_iq24 m_U2; /* +10 */
_iq31 m_E0; /* +12 */
_iq31 m_E1; /* +14 */
_iq31 m_E2; /* +16 */
_iq26 m_B2; /* +18 */
_iq26 m_B1; /* +20 */
_iq26 m_B0; /* +22 */
_iq26 m_A2; /* +24 */
_iq26 m_A1; /* +26 */
_iq23 m_K; /* +28 */
_iq15 m_max; /* +30 */
_iq15 m_min; /* +32 */
};

/************************** POST DECLARATIONS SECTION ************************/

interrupt void adc_isr(void);

/* Data align memory before instantiating a 2p2z controller. */

#pragma DATA_ALIGN ( CNTRL_2p2z , 64 );

CNTRL_2p2zData CNTRL_2p2z;
CNTRL_2p2zData* CNTRL_ptr;

main()
{

/* DSP2803x_SysCtrl.c */
InitSysCtrl();

/* DSP2802x_EPwm.c */
InitEPwm1Gpio();

/* Disable CPU interrupts */

DINT;

/* DSP2802x_PieCtrl.c */
InitPieCtrl();

/* Clear all CPU interrupt flags */

IER = 0x0000;
IFR = 0x0000;

/* DSP2802x_PieVect.c */
InitPieVectTable();

/* Interrupt re-mapped to ISR function */

EALLOW;
PieVectTable.ADCINT1 = &adc_isr;
EDIS;

October 2012 BAN105 Page 17

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

/* DSP2802x_InitPeripherals.c */
InitAdc();

/* Enable ADCINT1 in PIE */

PieCtrlRegs.PIEIER1.bit.INTx1 = 1;/* Enable INT 1.1 in the PIE */
IER |= M_INT1;/* Enable CPU Interrupt 1 */
EINT;/* Enable Global interrupt INTM */
ERTM;/* Enable Global realtime interrupt DBGM */

/* Configure ADC */
EALLOW;
AdcRegs.INTSEL1N2.bit.INT1E = 1;/* Enabled ADCINT1 */
AdcRegs.INTSEL1N2.bit.INT1CONT = 0;/* Disable ADCINT1 Continuous mode */
AdcRegs.INTSEL1N2.bit.INT1SEL = 0;/* setup EOC0 to trigger ADCINT1 to fire */
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0xA;/* Set SOC0 channel select to ADCINB2 */
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 6;/* Set SOC0 start trigger on EPWM1B, due to
round-robin SOC0 converts first then SOC1 */
AdcRegs.ADCSOC0CTL.bit.ACQPS = 6;/* Set SOC0 S/H Window to 7 ADC Clock Cycles, (6
ACQPS plus 1) */
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 0;/* Configure early interrupts */
EDIS;

/* Assumes ePWM1 clock is already enabled in InitSysCtrl(); */

EPwm1Regs.ETSEL.bit.SOCBEN = 1;/* Enable SOC on B group */
EPwm1Regs.ETSEL.bit.SOCBSEL = 6;/* Select SOC from from CPMB on upcount */
EPwm1Regs.ETPS.bit.SOCBPRD = 1;/* Generate pulse on 1st event */

/* Set period / duty / count mode */

EPwm1Regs.TBPHS.half.TBPHS = 0;/* Set Phase register to zero */
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;/* Phase loading disabled */
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;/* Clock ratio to SYSCLKOUT */
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;/* Set PWM1A on Zero */
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;/* Clear PWM1A on match on count A up */
EPwm1Regs.AQCTLB.bit.ZRO = AQ_SET;/* Set PWM1B on Zero */
EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR;/* Clear PWM1B on match on count B up */
EPwm1Regs.CMPB = 180;/* Set compare B value */
EPwm1Regs.CMPA.half.CMPA = 250;/* Set compare A value */
EPwm1Regs.TBPRD = period;/* Set period for ePWM1 */
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;/* Count up and start */

/* Configure trip zone based on Comparator 2 output and configure blanking */

EALLOW;
EPwm1Regs.TZSEL.bit.DCAEVT2 = 1;/* Digital compare, output A, cycle by cycle */
EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO;/* EPWM1A will go low */
EPwm1Regs.TZCTL.bit.TZB = TZ_NO_CHANGE;/* EPWM1B has no action */
EPwm1Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_HI;/* DCAEVT2 = DCAH high (will become
active as comparator output goes high) */
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP2OUT;/* DCAH = Comparator 2 output
*/
EPwm1Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT2;/* DCAEVT2 = DCAEVT2 (not filtered) */
EPwm1Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC;/* Take async path */
EPwm1Regs.DCFCTL.bit.PULSESEL = 0;/* Time-base counter equal to period (TBCTR =
TBPRD) */
EPwm1Regs.DCFCTL.bit.BLANKINV = 0;/* Blanking window inverted */
EPwm1Regs.DCFCTL.bit.BLANKE = 1;/* Blanking Window Enable */
EPwm1Regs.DCFCTL.bit.SRCSEL = 0;/* Source Is DCAEVT1 Signal */
EDIS;
EPwm1Regs.DCFWINDOW = 0;/* 0 length blanking window */
EPwm1Regs.DCFOFFSET = 25;/* 420ns blanking window offset & then blanking window
begins */

October 2012 BAN105 Page 18

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

/* Configure Comparator 2 */
EALLOW;
SysCtrlRegs.PCLKCR3.bit.COMP2ENCLK = 1;/* Enable comparator clock */
Comp2Regs.COMPCTL.bit.SYNCSEL = 0;/* Aysnc output */
Comp2Regs.COMPCTL.bit.QUALSEL = 0;/* No qualification */
Comp2Regs.COMPCTL.bit.CMPINV = 0;/* Non invert */
Comp2Regs.COMPCTL.bit.COMPSOURCE = 0;/* Internal DAC connection */
Comp2Regs.COMPCTL.bit.COMPDACEN = 1;/* Enable */
EDIS;

/* Configure DAC and slope compensation */

Comp2Regs.DACVAL.all = 0;
EALLOW;
Comp2Regs.DACCTL.bit.FREE_SOFT = 0;/* Emulation mode behavior, stop immediately */
Comp2Regs.DACCTL.bit.DACSOURCE = 1;/* Enable slope */
Comp2Regs.DACCTL.bit.RAMPSOURCE = 0;/* ePWM1 is sync source */
EDIS;
Comp2Regs.RAMPDECVAL_SHDW = slopeval;/* Set slope decrement */

/* Configure GPIO12 pin for toggling */

EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1;/* Disable pull-up on GPIO12 */
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 0;/* Configure GPIO0 as GPIO */
GpioCtrlRegs.GPADIR.bit.GPIO12 = 1;/* Configure as output */
EDIS;

/* Initialize controller */
CNTRL_2p2z.Ref.m_IQ = _IQ15(REF);
CNTRL_2p2z.m_U1 = _IQ24(0.0);
CNTRL_2p2z.m_U2 = _IQ24(0.0);
CNTRL_2p2z.m_E1 = _IQ30(0.0);
CNTRL_2p2z.m_E2 = _IQ30(0.0);
CNTRL_2p2z.m_B2 = _IQ26(B2);
CNTRL_2p2z.m_B1 = _IQ26(B1);
CNTRL_2p2z.m_B0 = _IQ26(B0);
CNTRL_2p2z.m_A2 = _IQ26(A2);
CNTRL_2p2z.m_A1 = _IQ26(A1);
CNTRL_2p2z.m_K = _IQ24(K);
CNTRL_2p2z.m_max = _IQ15(MAX_DUTY);
CNTRL_2p2z.m_min = _IQ15(MIN_DUTY);
CNTRL_ptr = &CNTRL_2p2z;

while(1)
{
}

interrupt void adc_isr(void)

{
GpioDataRegs.GPADAT.bit.GPIO12 = 1;/* Set GPIO12 (for timing purposes) */
AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;/* Clr ADCINT1 flag for next SOC */
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;/* Acknowledge interrupt to PIE */

/* Get feedback value */

CNTRL_2p2z.Fdbk.m_Int = AdcResult.ADCRESULT0;

/* The following is an embedded assembly function which executes the

* two-pole, two-zero controller. It has been hard coded by Biricha
* to execute in the shortest time possible.
*/

October 2012 BAN105 Page 19

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

asm(""
"\t\n PUSH XAR7 "
"\t\n PUSH XT "
"\t\n PUSH ACC "
"\n\t.global _CNTRL_2p2z "
"\n_CNTRLstart: "
"\t\n MOVW DP, #_CNTRL_2p2z+0 "
"\t\n MOVL XAR7,#_CNTRL_2p2z+18 "

"\t\n SETC SXM,OVM"

"\t\n MOV ACC,@_CNTRL_2p2z+0 "
"\t\n SUB ACC,@_CNTRL_2p2z+2 "
"\t\n LSL ACC,#16 "

"\t\n ; Diff equation"

"\t\n MOVL @_CNTRL_2p2z+8+4,ACC "
"\t\n MOVL XT,@_CNTRL_2p2z+8+8 "
"\t\n QMPYL ACC,XT,*XAR7++ "

"\t\n MOVDL XT,@_CNTRL_2p2z+8+6 "

"\t\n QMPYL P,XT,*XAR7++ "
"\t\n ADDL ACC,P "

"\t\n MOVDL XT,@_CNTRL_2p2z+8+4 "

"\t\n QMPYL P,XT,*XAR7++ "

"\t\n ADDL ACC,P "

"\t\n SFR ACC,#1"
"\t\n MOVL @_CNTRL_2p2z+6,ACC "

"\t\n MOVL XT,@_CNTRL_2p2z+8+2 "

"\t\n QMPYL ACC,XT,*XAR7++ "

"\t\n MOVDL XT,@_CNTRL_2p2z+8+0 "

"\t\n QMPYL P,XT,*XAR7++ "
"\t\n "
"\t\n ADDL ACC,P "

"\t\n LSL ACC,#5 "

"\t\n ADDL ACC,ACC "
"\t\n ADDL ACC,@_CNTRL_2p2z+6 "
"\t\n MOVL @_CNTRL_2p2z+8+0,ACC "

"\t\n MOVL XT,ACC "

"\t\n QMPYL ACC,XT,*XAR7++ "

"\t\n MINL ACC,*XAR7++ "

"\t\n MAXL ACC,*XAR7++ "

"\t\n MOV @_CNTRL_2p2z+4, AL "

"\t\n POP ACC "
"\t\n POP XT "
"\t\n POP XAR7 ");

Comp2Regs.RAMPMAXREF_SHDW = CNTRL_2p2z.Out.m_Int;/* Set DAC current reference */

GpioDataRegs.GPADAT.bit.GPIO12 = 0;/* Clr GPIO12 (for timing purposes) */

return;
}

October 2012 BAN105 Page 20

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

Appendix B - Biricha CSL Implementation

/******************************************************************************
* (c) Copyright 2011 Biricha Digital Power Limited
* FILE : main.c
* AUTHOR : Dr A. Shirsavar / Dr C. Hossack
* PROJECT : Piccolo A DPCM
* Target System : MCU C2802x
* CREATION DATE : 14/11/2011
* COPYRIGHT : Copyright Biricha Digital Power Limited 2011
* All rights reserved. Reproduction in whole or part is
* prohibited without written consent of the copyright
* owner.
* DESCRIPTION :
*
* This project demonstrates Peak Current Mode Control of BDP-105 Buck board
* using the Piccolo A microcontroller from Texas Instruments.
*
* The processor runs a 2p2z controller and performs slope compensation to
* remove subharmonic oscillations. The Piccolo's comparator 2 is being used
* to detect when the peak current reaches its demand value.
*
* Phase and gain margins of the digital PSU have been measured using a
* frequency response analyzer:
*
* phase margin = 65 degrees
* cross over frequency = 10 kHz
* switching frequency = 200kHz
*
* IMPORTANT: BDP-105 should be connected to Port 1 of the daughter card. switch
* current IL needs to be connected to the non-inverting pin of Piccolo's
* comparator. This connection is not implemented on the daughter card.
* Therefore a link wire needs to be connected from IL pin of the daughter card
* (i.e. ADC pin B0) to the Comparator 2's non-inverting pin (i.e. ADC Pin A4)
* Please ask an instructor for a link wire and make this connection.
*
* LINKS
* file:///C:/tidcs/c28/CSL_C2802x/v100/doc/CSL_C2802x.pdf
******************************************************************************/

/****************************** INCLUDES SECTION *****************************/

typedef unsigned int Uint16;

typedef unsigned long Uint32;
#include "DSP2802x_Comp.h"
#include "DSP2802x_EPwm.h"
#include "csl.h"

/**************************** DECLARATIONS SECTION ***************************/

/* These set up the coefficients for our 2p2z controller for BDP-105 Buck
* Converter with a 200kHz switching frequency and a crossover of 10kHz
*/

#define K (42.0243)
#define REF (_IQ15toF(2048))
#define MIN_DUTY 0
#define MAX_DUTY 65535
#define A1 +1.6902106568

October 2012 BAN105 Page 21

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

#define A2 -0.6902106568
#define B0 +2.0654678327
#define B1 +0.1258242849
#define B2 -1.9396435478

#define PERIOD_NS 5000 /*Our period in ns for fs = 200kHz */

/************************** POST DECLARATIONS SECTION ************************/

/* Data align memory before instantiating a 2p2z controller. */

#pragma DATA_ALIGN ( MyCntrl , 64 );

/* This effectively declares a 2p2z controller called MyCntrl */

CNTRL_2p2zData MyCntrl;

//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// GLOBAL VARIABLES
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

uint16_t slope;

/******************************************************************************
* FUNCTION : IsrAdc
* DESCRIPTION :
* This interrupt is called when the ADC sequencer has finished sampling.
******************************************************************************/
interrupt void IsrAdc( void )
{

/* Sets GPIO pin 12 tied to TZ test pin on hardware */

GPIO_set( GPIO_12);

/* Ack group and ADC SEQ interrupt. Re-enable the ADC interrupts -Int1 */
ADC_ackInt( ADC_INT_1 );

/* These three lines read the ADC, call the 2p2z control loop & then update
* the duty cycle respectively.
*/
MyCntrl.Fdbk.m_Int = ADC_getValue(ADC_MOD_1);
CNTRL_2p2z(&MyCntrl);

/* This inputs the "initial" value of the demand current (from the 2p2z)
* controller to the DAC of the comparator. i.e. the demand current before
* slope compensation is fed to the inverting pin of the on board
* comparator 2. This initial DAC value will later get updated by
* the DAC's slope compensation algorithm counter
*/
CMP_setRampMax( CMP_MOD_2, MyCntrl.Out.m_Int );

/* Clears GPIO12 pin */

GPIO_clr( GPIO_12);

/* Sets up soft-start*/
CNTRL_2p2zSoftStartUpdate(&MyCntrl);
}

October 2012 BAN105 Page 22

 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

/******************************************************************************
* FUNCTION : main
* DESCRIPTION :
*
******************************************************************************/
void main( void )
{
/* Initialize the MCU, ADC & GPIO12 */
SYS_init();
ADC_init();
GPIO_config( GPIO_12, GPIO_DIR_OUT, false );

/* Setup PWM Mod1 for fs = 200kHz. PWM1 Ch A is being used for switching
* the converter. PWM1 Ch B is being used for timing purposes - more on this
* later.
*/
PWM_config( PWM_MOD_1, PWM_nsToTicks(PERIOD_NS), PWM_COUNT_UP );
PWM_pin( PWM_MOD_1, PWM_CH_A, GPIO_NON_INVERT );
PWM_pin( PWM_MOD_1, PWM_CH_B, GPIO_NON_INVERT );

/* Typically for digital current mode we set the PWM Ch A duty 100%; then
* use the cycle by cycle trip function to pull the PWM pin low when the
* current reaches our demand peak value. However for safty we have set the
* maximum duty to 60%. i.e if your control algorithm fails, the PWM will
* reset after 60% rather than staying at 100%.
*/
PWM_setDutyA(PWM_MOD_1, PWM_nsToTicks(PERIOD_NS)*0.6 );

/* PWM1 Channel A is being used for the PWM drive of the MOSFET. Hence, the
* sampling, conversion, ADC interrupt entry, 2p2z, scaling and then DAC &
* comparator set up must happen just before PWM1 Ch A goes high. For this
* reason we use PWM1 Channel B to start the sampling process. The falling
* edge of PWM1 Ch B is used to start the sampling process followed by all
* relevant calculations. Therefore the duty of Ch B should be set such that
* all sampling and calculations are completed just as PWM1 Ch A goes high.
* This time has been measured on the scope as 2.45us.
*
* <---PERIOD_NS-->
* ___ ___
* PWM A: _______| |___________| |___________|
*
* PERIOD_NS-2450
* ________<-----> ________
* PWM B: _______| |______| |______|
* ^ ^
* PWM B triggers ADC SOC here^ ^ here PWM B starts CLA slope
* This falling edge needs to be compensation function for the next
* adjusted such that all cycle
* calculations are completed
* before the next cycle
* (i.e. before the next rising edge)
*/

/* This function sets the PWM1 Ch B such that the calculations are complete
* just before the rising edge PWM B. PERIOD_NS is our period and set to
* 5000 ns. Therefore we are setting our pulse width to (5000 - 2450) ns

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 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

*/
PWM_setDutyB(PWM_MOD_1, PWM_nsToTicks( PERIOD_NS-2500 ) );

/* This sets up the PWM Mod1 to start the ADC conversion whenever PWM1
* Channel B timebase counter matches Ch Bs duty. i.e. falling edge of PWM
* Ch B triggers ADC SoC, As discussed above.
*/
PWM_setAdcSoc( PWM_MOD_1, PWM_CH_B, PWM_INT_CMPB_UP );

/* This sets up PWM Mod1 to generate an interrupt every PWM cycle whenever
* timebase counter = 0. the "0" instead of an ISR function name means that
* an interrupt is generated but no jump to an ISR function is carried out.
* The CLA will detect this interrupt and run the CLA code instead. Finally
* PWM_INT_PRD_1 indicates that an interrupt should be generated every cycle
* as opposed to every other cycle
*/
PWM_setCallback(PWM_MOD_1, 0, PWM_INT_ZERO, PWM_INT_PRD_1 );

/* This effectively feeds the output of the comparator Mod2 into PWM Mod1
* and activates the blanking by setting the digital compare event
* PWM_DCEVT at the correct time. We will use PWM_DCEVT later to trip our
* PWM.
* The input to the blanking block is not inverted & "true" ensures that
* the output is not synchronized with the PWM's time-base
* clock.
*/
PWM_configBlanking( PWM_MOD_1, PWM_CMP_COMP2, GPIO_NON_INVERT, true );

/* Sets the size of the blanking window to 420ns */

PWM_setBlankingWindow( PWM_MOD_1, PWM_nsToTicks(420) );

/* sets up the relevant trip zones: i.e. when PWM_DCEVT occurs clear
* PWM1 Ch A on a cycle by cycle basis but take no action on PWM1 Ch B
* PWM_DCEVT was set up in PWM_configBlanking().
*/
PWM_setTripZone( PWM_MOD_1, PWM_DCEVT, PWM_TPZ_CYCLE_BY_CYCLE );
PWM_setTripState( PWM_MOD_1, PWM_CH_A, GPIO_CLR );
PWM_setTripState( PWM_MOD_1, PWM_CH_B, GPIO_NO_ACTION );

/* Configures ADC to sample Vo when triggered by PWM1 Ch B's falling edge

*/
ADC_config( ADC_MOD_1, ADC_SH_WIDTH_7, ADC_CH_B2, ADC_TRIG_EPWM1_SOCB );

/* When conversion is finished, cause interrupt and jump to IsrAdc */

ADC_setCallback( ADC_MOD_1, IsrAdc, ADC_INT_1 );

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 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

/* Initalise the 2p2z control structure */

CNTRL_2p2zInit(&MyCntrl
,_IQ15(REF)
,_IQ26(A1),_IQ26(A2)
,_IQ26(B0),_IQ26(B1),_IQ26(B2)
,_IQ23(K),MIN_DUTY,MAX_DUTY
);

/* Configures the comparator Mod2 with 0 qualification window

* i.e. asynchronous. The comparator output is not inverted & the inverting
* input of the comparator is tied to the on board DAC.
*/
CMP_config( CMP_MOD_2, CMP_ASYNC, GPIO_NON_INVERT, CMP_DAC );

/* DAC counter sub-module is configured

* This generates a slope on the current reference signal
* using a digital staircase.
*/
CMP_rampConfig( CMP_MOD_2, PWM_MOD_1 );
decval = CMP_calcRampDec( CMP_mVtoRampValue(124), PWM_freqToTicks(200000) );
CMP_setRampDec( CMP_MOD_2, decval );

/* Set up a 500ms soft-start */

CNTRL_2p2zSoftStartConfig(&MyCntrl, 500, PERIOD_NS );

/* Enables global interrupts and wait in idle loop */

INT_enableGlobal(true);

while(1)
{

}
}

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 DIGITAL Step-by-Step Design Guide for Digital Peak Current Mode Control: A Single-Chip Solution

IMPORTANT NOTICE

All material presented in this application note, associated software, exercises, appendices and any oral
presentations made by or on behalf of Biricha Digital Power Ltd are for educational purposes only, are not
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Copyright Biricha Digital Power Ltd 2012

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